^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (C) 2020 Spreadtrum Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SPRD_THM_CTL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SPRD_THM_INT_EN 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SPRD_THM_INT_STS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SPRD_THM_INT_RAW_STS 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SPRD_THM_DET_PERIOD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SPRD_THM_INT_CLR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SPRD_THM_INT_CLR_ST 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SPRD_THM_MON_PERIOD 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPRD_THM_MON_CTL 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SPRD_THM_INTERNAL_STS1 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPRD_THM_RAW_READ_MSK 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPRD_THM_OFFSET(id) ((id) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPRD_THM_TEMP(id) (SPRD_THM_OFFSET(id) + 0x5c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPRD_THM_THRES(id) (SPRD_THM_OFFSET(id) + 0x2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPRD_THM_SEN(id) BIT((id) + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPRD_THM_SEN_OVERHEAT_EN(id) BIT((id) + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPRD_THM_SEN_OVERHEAT_ALARM_EN(id) BIT((id) + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* bits definitions for register THM_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPRD_THM_SET_RDY_ST BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPRD_THM_SET_RDY BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPRD_THM_MON_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPRD_THM_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* bits definitions for register THM_INT_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPRD_THM_BIT_INT_EN BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPRD_THM_OVERHEAT_EN BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SPRD_THM_OTP_TRIP_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* bits definitions for register SPRD_THM_INTERNAL_STS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPRD_THM_TEMPER_RDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPRD_THM_DET_PERIOD_DATA 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPRD_THM_DET_PERIOD_MASK GENMASK(19, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPRD_THM_MON_MODE 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPRD_THM_MON_MODE_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPRD_THM_MON_PERIOD_DATA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPRD_THM_MON_PERIOD_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPRD_THM_THRES_MASK GENMASK(19, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPRD_THM_INT_CLR_MASK GENMASK(24, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* thermal sensor calibration parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPRD_THM_TEMP_LOW -40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPRD_THM_TEMP_HIGH 120000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPRD_THM_OTP_TEMP 120000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SPRD_THM_HOT_TEMP 75000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPRD_THM_RAW_DATA_LOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SPRD_THM_RAW_DATA_HIGH 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPRD_THM_SEN_NUM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPRD_THM_DT_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SPRD_THM_RATION_OFFSET 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPRD_THM_RATION_SIGN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SPRD_THM_RDYST_POLLING_TIME 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SPRD_THM_RDYST_TIMEOUT 700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SPRD_THM_TEMP_READY_POLL_TIME 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SPRD_THM_TEMP_READY_TIMEOUT 600000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SPRD_THM_MAX_SENSOR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct sprd_thermal_sensor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct thermal_zone_device *tzd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct sprd_thermal_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int cal_slope;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int cal_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct sprd_thermal_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) const struct sprd_thm_variant_data *var_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct sprd_thermal_sensor *sensor[SPRD_THM_MAX_SENSOR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 ratio_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int ratio_sign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int nr_sensors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * The conversion between ADC and temperature is based on linear relationship,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * and use idea_k to specify the slope and ideal_b to specify the offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Since different Spreadtrum SoCs have different ideal_k and ideal_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * we should save ideal_k and ideal_b in the device data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct sprd_thm_variant_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 ideal_k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 ideal_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const struct sprd_thm_variant_data ums512_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .ideal_k = 262,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .ideal_b = 66400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static inline void sprd_thm_update_bits(void __iomem *reg, u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 tmp, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) orig = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) tmp = orig & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) tmp |= val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) writel(tmp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int sprd_thm_cal_read(struct device_node *np, const char *cell_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct nvmem_cell *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) cell = of_nvmem_cell_get(np, cell_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (IS_ERR(cell))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return PTR_ERR(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) buf = nvmem_cell_read(cell, &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) nvmem_cell_put(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (IS_ERR(buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return PTR_ERR(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (len > sizeof(u32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) memcpy(val, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int sprd_thm_sensor_calibration(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct sprd_thermal_data *thm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct sprd_thermal_sensor *sen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * According to thermal datasheet, the default calibration offset is 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * and the default ratio is 1000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int dt_offset = 64, ratio = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = sprd_thm_cal_read(np, "sen_delta_cal", &dt_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ratio += thm->ratio_sign * thm->ratio_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * According to the ideal slope K and ideal offset B, combined with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * calibration value of thermal from efuse, then calibrate the real
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * slope k and offset b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * k_cal = (k * ratio) / 1000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * b_cal = b + (dt_offset - 64) * 500.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) sen->cal_slope = (thm->var_data->ideal_k * ratio) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) sen->cal_offset = thm->var_data->ideal_b + (dt_offset - 128) * 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int sprd_thm_rawdata_to_temp(struct sprd_thermal_sensor *sen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 rawdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) clamp(rawdata, (u32)SPRD_THM_RAW_DATA_LOW, (u32)SPRD_THM_RAW_DATA_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * According to the thermal datasheet, the formula of converting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * adc value to the temperature value should be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * T_final = k_cal * x - b_cal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return sen->cal_slope * rawdata - sen->cal_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int sprd_thm_temp_to_rawdata(int temp, struct sprd_thermal_sensor *sen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) clamp(temp, (int)SPRD_THM_TEMP_LOW, (int)SPRD_THM_TEMP_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * According to the thermal datasheet, the formula of converting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * adc value to the temperature value should be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * T_final = k_cal * x - b_cal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) val = (temp + sen->cal_offset) / sen->cal_slope;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return clamp(val, val, (u32)(SPRD_THM_RAW_DATA_HIGH - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int sprd_thm_read_temp(void *devdata, int *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct sprd_thermal_sensor *sen = devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) data = readl(sen->data->base + SPRD_THM_TEMP(sen->id)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) SPRD_THM_RAW_READ_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *temp = sprd_thm_rawdata_to_temp(sen, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const struct thermal_zone_of_device_ops sprd_thm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .get_temp = sprd_thm_read_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int sprd_thm_poll_ready_status(struct sprd_thermal_data *thm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * Wait for thermal ready status before configuring thermal parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = readl_poll_timeout(thm->base + SPRD_THM_CTL, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) !(val & SPRD_THM_SET_RDY_ST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) SPRD_THM_RDYST_POLLING_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) SPRD_THM_RDYST_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) sprd_thm_update_bits(thm->base + SPRD_THM_CTL, SPRD_THM_MON_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) SPRD_THM_MON_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) sprd_thm_update_bits(thm->base + SPRD_THM_CTL, SPRD_THM_SET_RDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) SPRD_THM_SET_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int sprd_thm_wait_temp_ready(struct sprd_thermal_data *thm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Wait for first temperature data ready before reading temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return readl_poll_timeout(thm->base + SPRD_THM_INTERNAL_STS1, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) !(val & SPRD_THM_TEMPER_RDY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) SPRD_THM_TEMP_READY_POLL_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) SPRD_THM_TEMP_READY_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int sprd_thm_set_ready(struct sprd_thermal_data *thm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ret = sprd_thm_poll_ready_status(thm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * Clear interrupt status, enable thermal interrupt and enable thermal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * The SPRD thermal controller integrates a hardware interrupt signal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * which means if the temperature is overheat, it will generate an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * interrupt and notify the event to PMIC automatically to shutdown the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * system. So here we should enable the interrupt bits, though we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * not registered an irq handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) writel(SPRD_THM_INT_CLR_MASK, thm->base + SPRD_THM_INT_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) sprd_thm_update_bits(thm->base + SPRD_THM_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) SPRD_THM_BIT_INT_EN, SPRD_THM_BIT_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) sprd_thm_update_bits(thm->base + SPRD_THM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) SPRD_THM_EN, SPRD_THM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static void sprd_thm_sensor_init(struct sprd_thermal_data *thm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct sprd_thermal_sensor *sen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 otp_rawdata, hot_rawdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) otp_rawdata = sprd_thm_temp_to_rawdata(SPRD_THM_OTP_TEMP, sen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) hot_rawdata = sprd_thm_temp_to_rawdata(SPRD_THM_HOT_TEMP, sen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Enable the sensor' overheat temperature protection interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) sprd_thm_update_bits(thm->base + SPRD_THM_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) SPRD_THM_SEN_OVERHEAT_ALARM_EN(sen->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) SPRD_THM_SEN_OVERHEAT_ALARM_EN(sen->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Set the sensor' overheat and hot threshold temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) sprd_thm_update_bits(thm->base + SPRD_THM_THRES(sen->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) SPRD_THM_THRES_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) (otp_rawdata << SPRD_THM_OTP_TRIP_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) hot_rawdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Enable the corresponding sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) sprd_thm_update_bits(thm->base + SPRD_THM_CTL, SPRD_THM_SEN(sen->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) SPRD_THM_SEN(sen->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static void sprd_thm_para_config(struct sprd_thermal_data *thm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Set the period of two valid temperature detection action */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) sprd_thm_update_bits(thm->base + SPRD_THM_DET_PERIOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) SPRD_THM_DET_PERIOD_MASK, SPRD_THM_DET_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Set the sensors' monitor mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) sprd_thm_update_bits(thm->base + SPRD_THM_MON_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) SPRD_THM_MON_MODE_MASK, SPRD_THM_MON_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Set the sensors' monitor period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) sprd_thm_update_bits(thm->base + SPRD_THM_MON_PERIOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) SPRD_THM_MON_PERIOD_MASK, SPRD_THM_MON_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void sprd_thm_toggle_sensor(struct sprd_thermal_sensor *sen, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct thermal_zone_device *tzd = sen->tzd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) thermal_zone_device_enable(tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) thermal_zone_device_disable(tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static int sprd_thm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct device_node *sen_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct sprd_thermal_data *thm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct sprd_thermal_sensor *sen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) const struct sprd_thm_variant_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) pdata = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_err(&pdev->dev, "No matching driver data found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) thm = devm_kzalloc(&pdev->dev, sizeof(*thm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (!thm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) thm->var_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) thm->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (IS_ERR(thm->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return PTR_ERR(thm->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) thm->nr_sensors = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (thm->nr_sensors == 0 || thm->nr_sensors > SPRD_THM_MAX_SENSOR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_err(&pdev->dev, "incorrect sensor count\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) thm->clk = devm_clk_get(&pdev->dev, "enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (IS_ERR(thm->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_err(&pdev->dev, "failed to get enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return PTR_ERR(thm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = clk_prepare_enable(thm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) sprd_thm_para_config(thm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = sprd_thm_cal_read(np, "thm_sign_cal", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (val > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) thm->ratio_sign = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) thm->ratio_sign = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ret = sprd_thm_cal_read(np, "thm_ratio_cal", &thm->ratio_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) for_each_child_of_node(np, sen_child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) sen = devm_kzalloc(&pdev->dev, sizeof(*sen), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!sen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) goto of_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) sen->data = thm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) sen->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ret = of_property_read_u32(sen_child, "reg", &sen->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_err(&pdev->dev, "get sensor reg failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) goto of_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ret = sprd_thm_sensor_calibration(sen_child, thm, sen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dev_err(&pdev->dev, "efuse cal analysis failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) goto of_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) sprd_thm_sensor_init(thm, sen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) sen->tzd = devm_thermal_zone_of_sensor_register(sen->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) sen->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) sen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) &sprd_thm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (IS_ERR(sen->tzd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev_err(&pdev->dev, "register thermal zone failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) sen->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ret = PTR_ERR(sen->tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) goto of_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) thm->sensor[sen->id] = sen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* sen_child set to NULL at this point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ret = sprd_thm_set_ready(thm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) goto of_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ret = sprd_thm_wait_temp_ready(thm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) goto of_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) for (i = 0; i < thm->nr_sensors; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) sprd_thm_toggle_sensor(thm->sensor[i], true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) platform_set_drvdata(pdev, thm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) of_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) of_node_put(sen_child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) clk_disable_unprepare(thm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static void sprd_thm_hw_suspend(struct sprd_thermal_data *thm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) for (i = 0; i < thm->nr_sensors; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) sprd_thm_update_bits(thm->base + SPRD_THM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) SPRD_THM_SEN(thm->sensor[i]->id), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) sprd_thm_update_bits(thm->base + SPRD_THM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) SPRD_THM_EN, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int sprd_thm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct sprd_thermal_data *thm = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) for (i = 0; i < thm->nr_sensors; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) sprd_thm_toggle_sensor(thm->sensor[i], false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) sprd_thm_hw_suspend(thm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) clk_disable_unprepare(thm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int sprd_thm_hw_resume(struct sprd_thermal_data *thm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) for (i = 0; i < thm->nr_sensors; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) sprd_thm_update_bits(thm->base + SPRD_THM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) SPRD_THM_SEN(thm->sensor[i]->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) SPRD_THM_SEN(thm->sensor[i]->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ret = sprd_thm_poll_ready_status(thm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) writel(SPRD_THM_INT_CLR_MASK, thm->base + SPRD_THM_INT_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) sprd_thm_update_bits(thm->base + SPRD_THM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) SPRD_THM_EN, SPRD_THM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return sprd_thm_wait_temp_ready(thm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int sprd_thm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct sprd_thermal_data *thm = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ret = clk_prepare_enable(thm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ret = sprd_thm_hw_resume(thm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) for (i = 0; i < thm->nr_sensors; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) sprd_thm_toggle_sensor(thm->sensor[i], true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) clk_disable_unprepare(thm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int sprd_thm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct sprd_thermal_data *thm = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) for (i = 0; i < thm->nr_sensors; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) sprd_thm_toggle_sensor(thm->sensor[i], false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) devm_thermal_zone_of_sensor_unregister(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) thm->sensor[i]->tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) clk_disable_unprepare(thm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const struct of_device_id sprd_thermal_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) { .compatible = "sprd,ums512-thermal", .data = &ums512_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) MODULE_DEVICE_TABLE(of, sprd_thermal_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static const struct dev_pm_ops sprd_thermal_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) SET_SYSTEM_SLEEP_PM_OPS(sprd_thm_suspend, sprd_thm_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static struct platform_driver sprd_thermal_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .probe = sprd_thm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .remove = sprd_thm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .name = "sprd-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .pm = &sprd_thermal_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .of_match_table = sprd_thermal_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) module_platform_driver(sprd_thermal_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) MODULE_AUTHOR("Freeman Liu <freeman.liu@unisoc.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) MODULE_DESCRIPTION("Spreadtrum thermal driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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