^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Caesar Wang <wxt@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/rockchip/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * If the temperature over a period of time High,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * the resulting TSHUT gave CRU module,let it reset the entire chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * or via GPIO give PMIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) enum tshut_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) TSHUT_MODE_CRU = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) TSHUT_MODE_OTP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * The system Temperature Sensors tshut(tshut) polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * the bit 8 is tshut polarity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * 0: low active, 1: high active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) enum tshut_polarity {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) TSHUT_LOW_ACTIVE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) TSHUT_HIGH_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * The system has two Temperature Sensors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * sensor0 is for CPU, and sensor1 is for GPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) enum sensor_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SENSOR_CPU = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SENSOR_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * The conversion table has the adc value and temperature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) enum adc_sort_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ADC_DECREMENT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ADC_INCREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include "thermal_hwmon.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * The max sensors is seven in rockchip SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SOC_MAX_SENSORS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * struct chip_tsadc_table - hold information about chip-specific differences
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @id: conversion table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @length: size of conversion table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @data_mask: mask to apply on data inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @kNum: linear parameter k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @bNum: linear parameter b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @mode: sort mode of this adc variant (incrementing or decrementing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct chip_tsadc_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) const struct tsadc_table *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 data_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Tsadc is linear, using linear parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int kNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int bNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) enum adc_sort_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * struct rockchip_tsadc_chip - hold the private data of tsadc chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @chn_id: array of sensor ids of chip corresponding to the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @chn_num: the channel number of tsadc chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @conversion_time: the conversion time of tsadc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @tshut_temp: the hardware-controlled shutdown temperature value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @initialize: SoC special initialize tsadc controller method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @irq_ack: clear the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @control: enable/disable method for the tsadc controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @get_temp: get the temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @set_alarm_temp: set the high temperature interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @set_tshut_temp: set the hardware-controlled shutdown temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @set_tshut_mode: set the hardware-controlled shutdown mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @get_trim_code: get the trim code by otp value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @trim_temp: get trim temp by trim code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @set_clk_rate: set clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @table: the chip-specific conversion table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct rockchip_tsadc_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* The sensor id of chip correspond to the ADC channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int chn_id[SOC_MAX_SENSORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int chn_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* The sensor electrical characteristics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int conversion_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* The hardware-controlled tshut property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int tshut_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) enum tshut_mode tshut_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) enum tshut_polarity tshut_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Chip-wide methods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) void (*initialize)(struct regmap *grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void __iomem *reg, enum tshut_polarity p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void (*irq_ack)(void __iomem *reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void (*control)(void __iomem *reg, bool on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Per-sensor methods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int (*get_temp)(const struct chip_tsadc_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int chn, void __iomem *reg, int *temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int (*set_alarm_temp)(const struct chip_tsadc_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int chn, void __iomem *reg, int temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int (*set_tshut_temp)(const struct chip_tsadc_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int chn, void __iomem *reg, int temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void (*set_tshut_mode)(struct regmap *grf, int chn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) void __iomem *reg, enum tshut_mode m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int (*get_trim_code)(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int code, int trim_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int (*trim_temp)(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int (*set_clk_rate)(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Per-table methods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct chip_tsadc_table table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * struct rockchip_thermal_sensor - hold the information of thermal sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @thermal: pointer to the platform/configuration data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @tzd: pointer to a thermal zone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @id: identifier of the thermal sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct rockchip_thermal_sensor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct rockchip_thermal_data *thermal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct thermal_zone_device *tzd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * struct rockchip_thermal_data - hold the private data of thermal driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @chip: pointer to the platform/configuration data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @pdev: platform device of thermal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @reset: the reset controller of tsadc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @sensors: array of thermal sensors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @clk: the bulk clk of tsadc, include controller clock and peripherals bus clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * @num_clks: the number of tsadc clks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * @grf: the general register file will be used to do static set by software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @regs: the base address of tsadc controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @tshut_temp: the hardware-controlled shutdown temperature value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @trim: trimmed value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @pinctrl: the pinctrl of tsadc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @gpio_state: pinctrl select gpio function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @otp_state: pinctrl select otp out function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @panic_nb: panic notifier block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct rockchip_thermal_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) const struct rockchip_tsadc_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct reset_control *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int tshut_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int trim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) enum tshut_mode tshut_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) enum tshut_polarity tshut_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct pinctrl_state *gpio_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct pinctrl_state *otp_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct notifier_block panic_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * TSADC Sensor Register description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TSADCV2_USER_CON 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TSADCV2_AUTO_CON 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TSADCV2_INT_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TSADCV2_INT_PD 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TSADCV3_AUTO_SRC_CON 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TSADCV3_HT_INT_EN 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TSADCV3_HSHUT_GPIO_INT_EN 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TSADCV3_HSHUT_CRU_INT_EN 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TSADCV3_INT_PD 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TSADCV3_HSHUT_PD 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TSADCV2_AUTO_PERIOD 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TSADCV2_AUTO_PERIOD_HT 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TSADCV3_AUTO_PERIOD 0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TSADCV3_AUTO_PERIOD_HT 0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TSADCV9_Q_MAX 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define TSADCV9_FLOW_CON 0x218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TSADCV2_AUTO_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TSADCV2_AUTO_EN_MASK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TSADCV3_AUTO_SRC_EN(chn) BIT(chn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + chn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define TSADCV3_AUTO_Q_SEL_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TSADCV2_INT_SRC_EN(chn) BIT(chn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define TSADCV2_DATA_MASK 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define TSADCV3_DATA_MASK 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define TSADCV4_DATA_MASK 0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define TSADCV9_AUTO_SRC (0x10001 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define TSADCV9_PD_MODE (0x10001 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define TSADCV9_Q_MAX_VAL (0xffff0400 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define GRF_SARADC_TESTBIT 0x0e644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define GRF_TSADC_TESTBIT_L 0x0e648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define GRF_TSADC_TESTBIT_H 0x0e64c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define PX30_GRF_SOC_CON0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define PX30_GRF_SOC_CON2 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define RK1808_BUS_GRF_SOC_CON0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define RK3568_GRF_TSADC_CON 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define RK3568_GRF_TSADC_TSEN (0x10001 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define RV1106_VOGRF_TSADC_CON 0x6000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define RV1106_VOGRF_TSADC_TSEN (0x10001 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define RV1106_VOGRF_TSADC_ANA (0xff0007 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define RV1126_GRF0_TSADC_CON 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define RV1126_GRF0_TSADC_TRM (0xff0077 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define RV1126_GRF0_TSADC_SHUT_2CRU (0x30003 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define RV1126_GRF0_TSADC_SHUT_2GPIO (0x70007 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define GRF_TSADC_BANDGAP_CHOPPER_EN (0x10001 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define GRF_TSADC_VCM_EN_L (0x10001 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define GRF_TSADC_VCM_EN_H (0x10001 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define GRF_CON_TSADC_CH_INV (0x10001 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define PX30S_TSADC_TDC_MODE (0x10001 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define PX30S_TSADC_TRIM (0xf0007 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define MIN_TEMP (-40000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define LOWEST_TEMP (-273000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define MAX_TEMP (125000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define MAX_ENV_TEMP (85000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * struct tsadc_table - code to temperature conversion table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * @code: the value of adc channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * @temp: the temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * code to temperature mapping of the temperature sensor is a piece wise linear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * curve.Any temperature, code faling between to 2 give temperatures can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * linearly interpolated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * Code to Temperature mapping should be updated based on manufacturer results.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct tsadc_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const struct tsadc_table rv1106_code_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {396, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {504, 25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {605, 85000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {673, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {TSADCV2_DATA_MASK, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const struct tsadc_table rv1108_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {374, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {382, -35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {389, -30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {397, -25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {405, -20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {413, -15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {421, -10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {429, -5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {436, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {444, 5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {452, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {460, 15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {468, 20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {476, 25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {483, 30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {491, 35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {499, 40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {507, 45000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {515, 50000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {523, 55000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {531, 60000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {539, 65000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {547, 70000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {555, 75000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {562, 80000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {570, 85000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {578, 90000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {586, 95000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {594, 100000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {602, 105000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {610, 110000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {618, 115000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {626, 120000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {634, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {TSADCV2_DATA_MASK, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const struct tsadc_table rk1808_code_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {3455, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {3463, -35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {3471, -30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {3479, -25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {3487, -20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {3495, -15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {3503, -10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {3511, -5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {3519, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {3527, 5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {3535, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {3543, 15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {3551, 20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {3559, 25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {3567, 30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {3576, 35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {3584, 40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {3592, 45000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {3600, 50000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {3609, 55000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {3617, 60000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {3625, 65000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {3633, 70000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {3642, 75000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {3650, 80000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {3659, 85000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {3667, 90000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {3675, 95000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {3684, 100000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {3692, 105000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {3701, 110000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {3709, 115000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {3718, 120000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {3726, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {TSADCV2_DATA_MASK, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const struct tsadc_table rk3228_code_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {588, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {593, -35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {598, -30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {603, -25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {608, -20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {613, -15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {618, -10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {623, -5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {629, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {634, 5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {639, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {644, 15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {649, 20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {654, 25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {660, 30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {665, 35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {670, 40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {675, 45000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {681, 50000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {686, 55000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {691, 60000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {696, 65000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {702, 70000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {707, 75000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {712, 80000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {717, 85000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {723, 90000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {728, 95000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {733, 100000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {738, 105000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {744, 110000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {749, 115000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {754, 120000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {760, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {TSADCV2_DATA_MASK, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static const struct tsadc_table rk3288_code_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {TSADCV2_DATA_MASK, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {3800, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {3792, -35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {3783, -30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {3774, -25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {3765, -20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {3756, -15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {3747, -10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {3737, -5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {3728, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {3718, 5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {3708, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {3698, 15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {3688, 20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {3678, 25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {3667, 30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {3656, 35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {3645, 40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {3634, 45000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {3623, 50000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {3611, 55000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {3600, 60000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {3588, 65000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {3575, 70000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {3563, 75000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {3550, 80000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {3537, 85000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {3524, 90000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {3510, 95000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {3496, 100000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {3482, 105000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {3467, 110000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {3452, 115000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {3437, 120000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {3421, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static const struct tsadc_table rk3328_code_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {296, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {304, -35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {313, -30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {331, -20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {340, -15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {349, -10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {359, -5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {368, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {378, 5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {388, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {398, 15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {408, 20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {418, 25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {429, 30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {440, 35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {451, 40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {462, 45000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {473, 50000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {485, 55000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {496, 60000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {508, 65000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {521, 70000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {533, 75000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {546, 80000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {559, 85000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {572, 90000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {586, 95000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {600, 100000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {614, 105000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {629, 110000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {644, 115000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {659, 120000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {675, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {TSADCV2_DATA_MASK, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const struct tsadc_table rk3368_code_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {106, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {108, -35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {110, -30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {112, -25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {114, -20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {116, -15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {118, -10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {120, -5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {122, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {124, 5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {126, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {128, 15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {130, 20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {132, 25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {134, 30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {136, 35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {138, 40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {140, 45000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {142, 50000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {144, 55000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {146, 60000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {148, 65000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {150, 70000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {152, 75000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {154, 80000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {156, 85000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {158, 90000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {160, 95000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {162, 100000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {163, 105000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {165, 110000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {167, 115000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {169, 120000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {171, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {TSADCV3_DATA_MASK, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static const struct tsadc_table rk3399_code_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {402, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {410, -35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {419, -30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {427, -25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {436, -20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {444, -15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {453, -10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {461, -5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {470, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {478, 5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {487, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {496, 15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {504, 20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {513, 25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {521, 30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {530, 35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {538, 40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {547, 45000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {555, 50000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {564, 55000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {573, 60000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {581, 65000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {590, 70000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {599, 75000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {607, 80000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {616, 85000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {624, 90000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {633, 95000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {642, 100000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {650, 105000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {659, 110000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {668, 115000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {677, 120000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {685, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {TSADCV3_DATA_MASK, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static const struct tsadc_table rk3568_code_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {0, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {1584, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {1620, -35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {1652, -30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {1688, -25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {1720, -20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {1756, -15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {1788, -10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {1824, -5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {1856, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {1892, 5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {1924, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {1956, 15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {1992, 20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {2024, 25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {2060, 30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {2092, 35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {2128, 40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {2160, 45000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {2196, 50000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {2228, 55000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {2264, 60000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {2300, 65000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {2332, 70000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {2368, 75000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {2400, 80000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {2436, 85000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {2468, 90000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {2500, 95000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {2536, 100000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {2572, 105000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {2604, 110000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {2636, 115000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {2672, 120000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {2704, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {TSADCV2_DATA_MASK, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static const struct tsadc_table rk3588_code_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {0, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {215, -40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {285, 25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {350, 85000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {395, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {TSADCV4_DATA_MASK, 125000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) int temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int high, low, mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) unsigned long num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) unsigned int denom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u32 error = table->data_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (table->kNum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return (((temp / 1000) * table->kNum) / 1000 + table->bNum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) low = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) high = (table->length - 1) - 1; /* ignore the last check for table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) mid = (high + low) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* Return mask code data when the temp is over table range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (temp < table->id[low].temp || temp > table->id[high].temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) while (low <= high) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (temp == table->id[mid].temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return table->id[mid].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) else if (temp < table->id[mid].temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) high = mid - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) low = mid + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) mid = (low + high) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * The conversion code granularity provided by the table. Let's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * assume that the relationship between temperature and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * analog value between 2 table entries is linear and interpolate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * to produce less granular result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) num = abs(table->id[mid + 1].code - table->id[mid].code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) num *= temp - table->id[mid].temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) denom = table->id[mid + 1].temp - table->id[mid].temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) switch (table->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) case ADC_DECREMENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return table->id[mid].code - (num / denom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) case ADC_INCREMENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return table->id[mid].code + (num / denom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) pr_err("%s: invalid temperature, temp=%d error=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) __func__, temp, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u32 code, int *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) unsigned int low = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) unsigned int high = table->length - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) unsigned int mid = (low + high) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) unsigned int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) unsigned long denom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (table->kNum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) *temp = (((int)code - table->bNum) * 10000 / table->kNum) * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (*temp < MIN_TEMP || *temp > MAX_TEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) WARN_ON(table->length < 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) switch (table->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case ADC_DECREMENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) code &= table->data_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (code <= table->id[high].code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return -EAGAIN; /* Incorrect reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) while (low <= high) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (code >= table->id[mid].code &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) code < table->id[mid - 1].code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) else if (code < table->id[mid].code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) low = mid + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) high = mid - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) mid = (low + high) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) case ADC_INCREMENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) code &= table->data_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (code < table->id[low].code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return -EAGAIN; /* Incorrect reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) while (low <= high) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (code <= table->id[mid].code &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) code > table->id[mid - 1].code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) else if (code > table->id[mid].code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) low = mid + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) high = mid - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) mid = (low + high) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * The 5C granularity provided by the table is too much. Let's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * assume that the relationship between sensor readings and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * temperature between 2 table entries is linear and interpolate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * to produce less granular result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) num = table->id[mid].temp - table->id[mid - 1].temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) num *= abs(table->id[mid - 1].code - code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) denom = abs(table->id[mid - 1].code - table->id[mid].code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) *temp = table->id[mid - 1].temp + (num / denom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * rk_tsadcv2_initialize - initialize TASDC Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * @grf: the general register file will be used to do static set by software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * @regs: the base address of tsadc controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * (1) Set TSADC_V2_AUTO_PERIOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * Configure the interleave between every two accessing of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * TSADC in normal operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * (2) Set TSADCV2_AUTO_PERIOD_HT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * Configure the interleave between every two accessing of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * TSADC after the temperature is higher than COM_SHUT or COM_INT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * If the temperature is higher than COMP_INT or COMP_SHUT for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * "debounce" times, TSADC controller will generate interrupt or TSHUT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) enum tshut_polarity tshut_polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (tshut_polarity == TSHUT_HIGH_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) regs + TSADCV2_HIGHT_INT_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) regs + TSADCV2_AUTO_PERIOD_HT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * rk_tsadcv3_initialize - initialize TASDC Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * @grf: the general register file will be used to do static set by software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * @regs: the base address of tsadc controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * (1) The tsadc control power sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * (2) Set TSADC_V2_AUTO_PERIOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * Configure the interleave between every two accessing of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * TSADC in normal operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * (2) Set TSADCV2_AUTO_PERIOD_HT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * Configure the interleave between every two accessing of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * TSADC after the temperature is higher than COM_SHUT or COM_INT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * If the temperature is higher than COMP_INT or COMP_SHUT for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * "debounce" times, TSADC controller will generate interrupt or TSHUT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) enum tshut_polarity tshut_polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* The tsadc control power sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (IS_ERR(grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* Set interleave value to workround ic time sync issue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) TSADCV2_USER_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) regs + TSADCV2_AUTO_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) regs + TSADCV2_HIGHT_INT_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) regs + TSADCV2_AUTO_PERIOD_HT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* Enable the voltage common mode feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) usleep_range(15, 100); /* The spec note says at least 15 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) usleep_range(90, 200); /* The spec note says at least 90 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) writel_relaxed(TSADCV3_AUTO_PERIOD_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) regs + TSADCV2_AUTO_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) regs + TSADCV2_HIGHT_INT_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) regs + TSADCV2_AUTO_PERIOD_HT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (tshut_polarity == TSHUT_HIGH_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static void rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) enum tshut_polarity tshut_polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) rk_tsadcv2_initialize(grf, regs, tshut_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static void rk_tsadcv5_initialize(struct regmap *grf, void __iomem *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) enum tshut_polarity tshut_polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (tshut_polarity == TSHUT_HIGH_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) writel_relaxed(TSADCV5_USER_INTER_PD_SOC, regs + TSADCV2_USER_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) writel_relaxed(TSADCV5_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) regs + TSADCV2_HIGHT_INT_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) writel_relaxed(TSADCV5_AUTO_PERIOD_HT_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) regs + TSADCV2_AUTO_PERIOD_HT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (!IS_ERR(grf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) regmap_write(grf, RK1808_BUS_GRF_SOC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) GRF_TSADC_BANDGAP_CHOPPER_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static void rk_tsadcv6_initialize(struct regmap *grf, void __iomem *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) enum tshut_polarity tshut_polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) rk_tsadcv2_initialize(grf, regs, tshut_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (!IS_ERR(grf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) regmap_write(grf, RV1126_GRF0_TSADC_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) RV1126_GRF0_TSADC_TRM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static void rk_tsadcv7_initialize(struct regmap *grf, void __iomem *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) enum tshut_polarity tshut_polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) writel_relaxed(TSADCV5_USER_INTER_PD_SOC, regs + TSADCV2_USER_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) writel_relaxed(TSADCV5_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) regs + TSADCV2_HIGHT_INT_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) writel_relaxed(TSADCV5_AUTO_PERIOD_HT_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) regs + TSADCV2_AUTO_PERIOD_HT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (tshut_polarity == TSHUT_HIGH_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (!IS_ERR(grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) udelay(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static void rk_tsadcv8_initialize(struct regmap *grf, void __iomem *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) enum tshut_polarity tshut_polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) writel_relaxed(TSADCV6_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) writel_relaxed(TSADCV6_AUTO_PERIOD_HT_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) regs + TSADCV3_AUTO_PERIOD_HT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) regs + TSADCV3_HIGHT_INT_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (tshut_polarity == TSHUT_HIGH_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) TSADCV2_AUTO_TSHUT_POLARITY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static void rk_tsadcv9_initialize(struct regmap *grf, void __iomem *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) enum tshut_polarity tshut_polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) regmap_write(grf, RV1106_VOGRF_TSADC_CON, RV1106_VOGRF_TSADC_TSEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) regmap_write(grf, RV1106_VOGRF_TSADC_CON, RV1106_VOGRF_TSADC_ANA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) regs + TSADCV3_AUTO_PERIOD_HT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) regs + TSADCV3_HIGHT_INT_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) writel_relaxed(TSADCV9_AUTO_SRC, regs + TSADCV2_INT_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) writel_relaxed(TSADCV9_PD_MODE, regs + TSADCV9_FLOW_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) writel_relaxed(TSADCV9_Q_MAX_VAL, regs + TSADCV9_Q_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (tshut_polarity == TSHUT_HIGH_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) TSADCV2_AUTO_TSHUT_POLARITY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | (TSADCV3_AUTO_Q_SEL_EN << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static void rk_tsadcv10_initialize(struct regmap *grf, void __iomem *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) enum tshut_polarity tshut_polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) rk_tsadcv2_initialize(grf, regs, tshut_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (!IS_ERR(grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) regmap_write(grf, PX30_GRF_SOC_CON0, PX30S_TSADC_TDC_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) regmap_write(grf, PX30_GRF_SOC_CON0, PX30S_TSADC_TRIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static void rk_tsadcv2_irq_ack(void __iomem *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) val = readl_relaxed(regs + TSADCV2_INT_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static void rk_tsadcv3_irq_ack(void __iomem *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) val = readl_relaxed(regs + TSADCV2_INT_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static void rk_tsadcv4_irq_ack(void __iomem *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) val = readl_relaxed(regs + TSADCV3_INT_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) writel_relaxed(val & TSADCV4_INT_PD_CLEAR_MASK, regs + TSADCV3_INT_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) val = readl_relaxed(regs + TSADCV3_HSHUT_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) regs + TSADCV3_HSHUT_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static void rk_tsadcv2_control(void __iomem *regs, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) val = readl_relaxed(regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) val |= TSADCV2_AUTO_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) val &= ~TSADCV2_AUTO_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) writel_relaxed(val, regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * rk_tsadcv3_control - the tsadc controller is enabled or disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * @regs: the base address of tsadc controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * @enable: boolean flag to enable the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * NOTE: TSADC controller works at auto mode, and some SoCs need set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * adc value if setting this bit to enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static void rk_tsadcv3_control(void __iomem *regs, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) val = readl_relaxed(regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) val &= ~TSADCV2_AUTO_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) writel_relaxed(val, regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static void rk_tsadcv4_control(void __iomem *regs, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) val = TSADCV2_AUTO_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) writel_relaxed(val, regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) int chn, void __iomem *regs, int *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) val = readl_relaxed(regs + TSADCV2_DATA(chn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return rk_tsadcv2_code_to_temp(table, val, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) static int rk_tsadcv4_get_temp(const struct chip_tsadc_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) int chn, void __iomem *regs, int *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) val = readl_relaxed(regs + TSADCV3_DATA(chn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return rk_tsadcv2_code_to_temp(table, val, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) int chn, void __iomem *regs, int temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) u32 alarm_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) u32 int_en, int_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * In some cases, some sensors didn't need the trip points, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * in the end, ignore this case and disable the high temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (temp == INT_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) int_clr = readl_relaxed(regs + TSADCV2_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) int_clr &= ~TSADCV2_INT_SRC_EN(chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) writel_relaxed(int_clr, regs + TSADCV2_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* Make sure the value is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) alarm_value = rk_tsadcv2_temp_to_code(table, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (alarm_value == table->data_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) writel_relaxed(alarm_value & table->data_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) regs + TSADCV2_COMP_INT(chn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) int_en = readl_relaxed(regs + TSADCV2_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) int_en |= TSADCV2_INT_SRC_EN(chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) writel_relaxed(int_en, regs + TSADCV2_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static int rk_tsadcv3_alarm_temp(const struct chip_tsadc_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) int chn, void __iomem *regs, int temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) u32 alarm_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * In some cases, some sensors didn't need the trip points, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * in the end, ignore this case and disable the high temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (temp == INT_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) writel_relaxed(TSADCV2_INT_SRC_EN_MASK(chn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) regs + TSADCV3_HT_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) /* Make sure the value is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) alarm_value = rk_tsadcv2_temp_to_code(table, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (alarm_value == table->data_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) writel_relaxed(alarm_value & table->data_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) regs + TSADCV3_COMP_INT(chn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) writel_relaxed(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) regs + TSADCV3_HT_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) int chn, void __iomem *regs, int temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) u32 tshut_value, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /* Make sure the value is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) tshut_value = rk_tsadcv2_temp_to_code(table, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (tshut_value == table->data_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /* TSHUT will be valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) val = readl_relaxed(regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static int rk_tsadcv3_tshut_temp(const struct chip_tsadc_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) int chn, void __iomem *regs, int temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) u32 tshut_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) /* Make sure the value is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) tshut_value = rk_tsadcv2_temp_to_code(table, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (tshut_value == table->data_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) writel_relaxed(tshut_value, regs + TSADCV3_COMP_SHUT(chn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* TSHUT will be valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) writel_relaxed(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) regs + TSADCV3_AUTO_SRC_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static void rk_tsadcv2_tshut_mode(struct regmap *grf, int chn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) void __iomem *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) enum tshut_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) val = readl_relaxed(regs + TSADCV2_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (mode == TSHUT_MODE_OTP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) writel_relaxed(val, regs + TSADCV2_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) static void rk_tsadcv3_tshut_mode(struct regmap *grf, int chn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) void __iomem *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) enum tshut_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) val = readl_relaxed(regs + TSADCV2_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (mode == TSHUT_MODE_OTP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (!IS_ERR(grf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) regmap_write(grf, RV1126_GRF0_TSADC_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) RV1126_GRF0_TSADC_SHUT_2GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (!IS_ERR(grf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) regmap_write(grf, RV1126_GRF0_TSADC_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) RV1126_GRF0_TSADC_SHUT_2CRU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) writel_relaxed(val, regs + TSADCV2_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static void rk_tsadcv4_tshut_mode(struct regmap *grf, int chn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) void __iomem *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) enum tshut_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) u32 val_gpio, val_cru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (mode == TSHUT_MODE_OTP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) val_cru = TSADCV2_INT_SRC_EN_MASK(chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) val_gpio = TSADCV2_INT_SRC_EN_MASK(chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static int rk_tsadcv1_get_trim_code(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) int code, int trim_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) const struct chip_tsadc_table *table = &thermal->chip->table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) u32 base_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) int trim_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) base_code = trim_base * table->kNum / 1000 + table->bNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) trim_code = code - base_code - 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return trim_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static int rk_tsadcv1_trim_temp(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) return thermal->trim * 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) static int rk_tsadcv1_set_clk_rate(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) clk = devm_clk_get(&pdev->dev, "tsadc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) error = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) dev_err(&pdev->dev, "failed to get tsadc clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) error = clk_set_rate(clk, 4000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (error < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) devm_clk_put(&pdev->dev, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) "failed to set tsadc clk rate to 4000000Hz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) devm_clk_put(&pdev->dev, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) static const struct rockchip_tsadc_chip px30_tsadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .chn_num = 2, /* 2 channels for tsadc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .tshut_temp = 95000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .initialize = rk_tsadcv4_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .irq_ack = rk_tsadcv3_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .control = rk_tsadcv3_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .get_temp = rk_tsadcv2_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .set_alarm_temp = rk_tsadcv2_alarm_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .set_tshut_temp = rk_tsadcv2_tshut_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .set_tshut_mode = rk_tsadcv2_tshut_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .id = rk3328_code_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .length = ARRAY_SIZE(rk3328_code_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .data_mask = TSADCV2_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .mode = ADC_INCREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) static const struct rockchip_tsadc_chip px30s_tsadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .chn_num = 2, /* 1 channels for tsadc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .conversion_time = 2100, /* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .tshut_temp = 95000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .initialize = rk_tsadcv10_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .irq_ack = rk_tsadcv3_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .control = rk_tsadcv2_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .get_temp = rk_tsadcv2_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .set_alarm_temp = rk_tsadcv2_alarm_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .set_tshut_temp = rk_tsadcv2_tshut_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .set_tshut_mode = rk_tsadcv2_tshut_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .set_clk_rate = rk_tsadcv1_set_clk_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .kNum = 2699,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .bNum = 2796,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .data_mask = TSADCV2_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .mode = ADC_INCREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) static const struct rockchip_tsadc_chip rv1106_tsadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) /* top, big_core0, big_core1, little_core, center, gpu, npu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .chn_num = 1, /* seven channels for tsadc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .tshut_temp = 95000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .initialize = rk_tsadcv9_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .irq_ack = rk_tsadcv4_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .control = rk_tsadcv4_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .get_temp = rk_tsadcv4_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .set_alarm_temp = rk_tsadcv3_alarm_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .set_tshut_temp = rk_tsadcv3_tshut_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .set_tshut_mode = rk_tsadcv4_tshut_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .id = rv1106_code_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .length = ARRAY_SIZE(rv1106_code_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .data_mask = TSADCV2_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .mode = ADC_INCREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) static const struct rockchip_tsadc_chip rv1108_tsadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .chn_num = 1, /* one channel for tsadc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .tshut_temp = 95000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .initialize = rk_tsadcv2_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .irq_ack = rk_tsadcv3_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .control = rk_tsadcv3_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .get_temp = rk_tsadcv2_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .set_alarm_temp = rk_tsadcv2_alarm_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .set_tshut_temp = rk_tsadcv2_tshut_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .set_tshut_mode = rk_tsadcv2_tshut_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .id = rv1108_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .length = ARRAY_SIZE(rv1108_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .data_mask = TSADCV2_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .mode = ADC_INCREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static const struct rockchip_tsadc_chip rv1126_tsadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .chn_num = 1, /* one channel for tsadc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .tshut_temp = 95000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .initialize = rk_tsadcv6_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .irq_ack = rk_tsadcv3_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .control = rk_tsadcv2_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .get_temp = rk_tsadcv2_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .set_alarm_temp = rk_tsadcv2_alarm_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .set_tshut_temp = rk_tsadcv2_tshut_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .set_tshut_mode = rk_tsadcv3_tshut_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .get_trim_code = rk_tsadcv1_get_trim_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .trim_temp = rk_tsadcv1_trim_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .kNum = 2263,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .bNum = 2704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .data_mask = TSADCV2_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .mode = ADC_INCREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static const struct rockchip_tsadc_chip rk1808_tsadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .chn_num = 1, /* one channel for tsadc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .tshut_temp = 95000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .initialize = rk_tsadcv5_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .irq_ack = rk_tsadcv3_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .control = rk_tsadcv3_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .get_temp = rk_tsadcv2_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .set_alarm_temp = rk_tsadcv2_alarm_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .set_tshut_temp = rk_tsadcv2_tshut_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .set_tshut_mode = rk_tsadcv2_tshut_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .id = rk1808_code_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .length = ARRAY_SIZE(rk1808_code_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .data_mask = TSADCV2_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .mode = ADC_INCREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .chn_num = 1, /* one channel for tsadc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .tshut_temp = 95000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .initialize = rk_tsadcv2_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .irq_ack = rk_tsadcv3_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .control = rk_tsadcv3_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .get_temp = rk_tsadcv2_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .set_alarm_temp = rk_tsadcv2_alarm_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .set_tshut_temp = rk_tsadcv2_tshut_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .set_tshut_mode = rk_tsadcv2_tshut_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .id = rk3228_code_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .length = ARRAY_SIZE(rk3228_code_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .data_mask = TSADCV3_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .mode = ADC_INCREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .chn_num = 2, /* two channels for tsadc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .tshut_temp = 95000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .initialize = rk_tsadcv2_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .irq_ack = rk_tsadcv2_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .control = rk_tsadcv2_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .get_temp = rk_tsadcv2_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .set_alarm_temp = rk_tsadcv2_alarm_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .set_tshut_temp = rk_tsadcv2_tshut_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .set_tshut_mode = rk_tsadcv2_tshut_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .id = rk3288_code_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .length = ARRAY_SIZE(rk3288_code_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .data_mask = TSADCV2_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .mode = ADC_DECREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static const struct rockchip_tsadc_chip rk3308_tsadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .chn_num = 2, /* 2 channels for tsadc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .tshut_temp = 95000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .initialize = rk_tsadcv2_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .irq_ack = rk_tsadcv3_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .control = rk_tsadcv3_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .get_temp = rk_tsadcv2_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .set_alarm_temp = rk_tsadcv2_alarm_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .set_tshut_temp = rk_tsadcv2_tshut_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .set_tshut_mode = rk_tsadcv2_tshut_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .id = rk3328_code_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .length = ARRAY_SIZE(rk3328_code_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .data_mask = TSADCV2_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .mode = ADC_INCREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) static const struct rockchip_tsadc_chip rk3308bs_tsadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .chn_num = 1, /* 1 channels for tsadc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .conversion_time = 2100, /* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .tshut_temp = 95000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .initialize = rk_tsadcv2_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .irq_ack = rk_tsadcv3_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .control = rk_tsadcv2_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .get_temp = rk_tsadcv2_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .set_alarm_temp = rk_tsadcv2_alarm_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .set_tshut_temp = rk_tsadcv2_tshut_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .set_tshut_mode = rk_tsadcv2_tshut_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .set_clk_rate = rk_tsadcv1_set_clk_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .kNum = 2699,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .bNum = 2796,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .data_mask = TSADCV2_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .mode = ADC_INCREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .chn_num = 1, /* one channels for tsadc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .tshut_temp = 95000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .initialize = rk_tsadcv2_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .irq_ack = rk_tsadcv3_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .control = rk_tsadcv3_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .get_temp = rk_tsadcv2_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .set_alarm_temp = rk_tsadcv2_alarm_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .set_tshut_temp = rk_tsadcv2_tshut_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .set_tshut_mode = rk_tsadcv2_tshut_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .id = rk3328_code_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .length = ARRAY_SIZE(rk3328_code_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .data_mask = TSADCV2_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .mode = ADC_INCREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .chn_num = 2, /* two channels for tsadc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .tshut_temp = 95000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .initialize = rk_tsadcv3_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .irq_ack = rk_tsadcv3_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .control = rk_tsadcv3_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .get_temp = rk_tsadcv2_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .set_alarm_temp = rk_tsadcv2_alarm_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .set_tshut_temp = rk_tsadcv2_tshut_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .set_tshut_mode = rk_tsadcv2_tshut_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .id = rk3228_code_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .length = ARRAY_SIZE(rk3228_code_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .data_mask = TSADCV3_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .mode = ADC_INCREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .chn_num = 2, /* two channels for tsadc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .tshut_temp = 95000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .initialize = rk_tsadcv2_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .irq_ack = rk_tsadcv2_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .control = rk_tsadcv2_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .get_temp = rk_tsadcv2_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .set_alarm_temp = rk_tsadcv2_alarm_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .set_tshut_temp = rk_tsadcv2_tshut_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .set_tshut_mode = rk_tsadcv2_tshut_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .id = rk3368_code_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .length = ARRAY_SIZE(rk3368_code_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .data_mask = TSADCV3_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .mode = ADC_INCREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .chn_num = 2, /* two channels for tsadc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .tshut_temp = 95000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .initialize = rk_tsadcv3_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .irq_ack = rk_tsadcv3_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .control = rk_tsadcv3_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .get_temp = rk_tsadcv2_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .set_alarm_temp = rk_tsadcv2_alarm_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .set_tshut_temp = rk_tsadcv2_tshut_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .set_tshut_mode = rk_tsadcv2_tshut_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .id = rk3399_code_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .length = ARRAY_SIZE(rk3399_code_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .data_mask = TSADCV3_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .mode = ADC_INCREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .chn_num = 2, /* two channels for tsadc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .tshut_temp = 95000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .initialize = rk_tsadcv7_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .irq_ack = rk_tsadcv3_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .control = rk_tsadcv3_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .get_temp = rk_tsadcv2_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .set_alarm_temp = rk_tsadcv2_alarm_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .set_tshut_temp = rk_tsadcv2_tshut_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .set_tshut_mode = rk_tsadcv2_tshut_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .id = rk3568_code_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .length = ARRAY_SIZE(rk3568_code_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .data_mask = TSADCV2_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .mode = ADC_INCREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) static const struct rockchip_tsadc_chip rk3588_tsadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) /* top, big_core0, big_core1, little_core, center, gpu, npu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .chn_id = {0, 1, 2, 3, 4, 5, 6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .chn_num = 7, /* seven channels for tsadc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .tshut_temp = 95000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .initialize = rk_tsadcv8_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .irq_ack = rk_tsadcv4_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .control = rk_tsadcv4_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .get_temp = rk_tsadcv4_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .set_alarm_temp = rk_tsadcv3_alarm_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .set_tshut_temp = rk_tsadcv3_tshut_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .set_tshut_mode = rk_tsadcv4_tshut_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .id = rk3588_code_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .length = ARRAY_SIZE(rk3588_code_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .data_mask = TSADCV4_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .mode = ADC_INCREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) static const struct of_device_id of_rockchip_thermal_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) #ifdef CONFIG_CPU_PX30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) { .compatible = "rockchip,px30-tsadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .data = (void *)&px30_tsadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) { .compatible = "rockchip,px30s-tsadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .data = (void *)&px30s_tsadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) #ifdef CONFIG_CPU_RV1106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .compatible = "rockchip,rv1106-tsadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .data = (void *)&rv1106_tsadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) #ifdef CONFIG_CPU_RV1108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .compatible = "rockchip,rv1108-tsadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .data = (void *)&rv1108_tsadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) #ifdef CONFIG_CPU_RV1126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .compatible = "rockchip,rv1126-tsadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .data = (void *)&rv1126_tsadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) #ifdef CONFIG_CPU_RK1808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .compatible = "rockchip,rk1808-tsadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .data = (void *)&rk1808_tsadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) #ifdef CONFIG_CPU_RK322X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .compatible = "rockchip,rk3228-tsadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .data = (void *)&rk3228_tsadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) #ifdef CONFIG_CPU_RK3288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .compatible = "rockchip,rk3288-tsadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .data = (void *)&rk3288_tsadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) #ifdef CONFIG_CPU_RK3308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .compatible = "rockchip,rk3308-tsadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .data = (void *)&rk3308_tsadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .compatible = "rockchip,rk3308bs-tsadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .data = (void *)&rk3308bs_tsadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) #ifdef CONFIG_CPU_RK3328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .compatible = "rockchip,rk3328-tsadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .data = (void *)&rk3328_tsadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) #ifdef CONFIG_CPU_RK3366
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .compatible = "rockchip,rk3366-tsadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .data = (void *)&rk3366_tsadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) #ifdef CONFIG_CPU_RK3368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .compatible = "rockchip,rk3368-tsadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .data = (void *)&rk3368_tsadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) #ifdef CONFIG_CPU_RK3399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .compatible = "rockchip,rk3399-tsadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .data = (void *)&rk3399_tsadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) #ifdef CONFIG_CPU_RK3568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .compatible = "rockchip,rk3568-tsadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .data = (void *)&rk3568_tsadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) #ifdef CONFIG_CPU_RK3588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .compatible = "rockchip,rk3588-tsadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .data = (void *)&rk3588_tsadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) { /* end */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) struct thermal_zone_device *tzd = sensor->tzd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) thermal_zone_device_enable(tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) thermal_zone_device_disable(tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) struct rockchip_thermal_data *thermal = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) thermal->chip->irq_ack(thermal->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) for (i = 0; i < thermal->chip->chn_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) thermal_zone_device_update(thermal->sensors[i].tzd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) THERMAL_EVENT_UNSPECIFIED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) static int rockchip_thermal_set_trips(void *_sensor, int low, int high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) struct rockchip_thermal_sensor *sensor = _sensor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) struct rockchip_thermal_data *thermal = sensor->thermal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) const struct rockchip_tsadc_chip *tsadc = thermal->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) __func__, sensor->id, low, high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) if (tsadc->trim_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) high += tsadc->trim_temp(thermal->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) return tsadc->set_alarm_temp(&tsadc->table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) sensor->id, thermal->regs, high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) static int rockchip_thermal_get_temp(void *_sensor, int *out_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) struct rockchip_thermal_sensor *sensor = _sensor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) struct rockchip_thermal_data *thermal = sensor->thermal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) retval = tsadc->get_temp(&tsadc->table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) sensor->id, thermal->regs, out_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) if (tsadc->trim_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) *out_temp -= tsadc->trim_temp(thermal->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) sensor->id, *out_temp, retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .get_temp = rockchip_thermal_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .set_trips = rockchip_thermal_set_trips,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) static void thermal_pinctrl_select_otp(struct rockchip_thermal_data *thermal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) if (!IS_ERR(thermal->pinctrl) && !IS_ERR_OR_NULL(thermal->otp_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) pinctrl_select_state(thermal->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) thermal->otp_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) static void thermal_pinctrl_select_gpio(struct rockchip_thermal_data *thermal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (!IS_ERR(thermal->pinctrl) && !IS_ERR_OR_NULL(thermal->gpio_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) pinctrl_select_state(thermal->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) thermal->gpio_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) static int rockchip_get_efuse_value(struct device_node *np, char *porp_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) int *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) struct nvmem_cell *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) unsigned char *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) cell = of_nvmem_cell_get(np, porp_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) if (IS_ERR(cell))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) return PTR_ERR(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) buf = (unsigned char *)nvmem_cell_read(cell, &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) nvmem_cell_put(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) if (IS_ERR(buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) return PTR_ERR(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) *value = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) static int rockchip_configure_from_dt(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) struct rockchip_thermal_data *thermal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) const struct rockchip_tsadc_chip *tsadc = thermal->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) u32 shut_temp, tshut_mode, tshut_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) int trim_l = 0, trim_h = 0, trim_bsae = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) "Missing tshut temp property, using default %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) thermal->chip->tshut_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) thermal->tshut_temp = thermal->chip->tshut_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (shut_temp > INT_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) dev_err(dev, "Invalid tshut temperature specified: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) shut_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) thermal->tshut_temp = shut_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) "Missing tshut mode property, using default (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) thermal->chip->tshut_mode == TSHUT_MODE_OTP ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) "gpio" : "cru");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) thermal->tshut_mode = thermal->chip->tshut_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) thermal->tshut_mode = tshut_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) if (thermal->tshut_mode > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) dev_err(dev, "Invalid tshut mode specified: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) thermal->tshut_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) if (of_property_read_u32(np, "rockchip,hw-tshut-polarity",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) &tshut_polarity)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) "Missing tshut-polarity property, using default (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) "low" : "high");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) thermal->tshut_polarity = thermal->chip->tshut_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) thermal->tshut_polarity = tshut_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) if (thermal->tshut_polarity > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) dev_err(dev, "Invalid tshut-polarity specified: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) thermal->tshut_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) /* The tsadc wont to handle the error in here since some SoCs didn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) * need this property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (IS_ERR(thermal->grf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) dev_warn(dev, "Missing rockchip,grf property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) if (tsadc->trim_temp && tsadc->get_trim_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) /* The tsadc won't to handle the error in here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) * since some SoCs didn't need this property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) * rv1126 need trim tsadc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) if (rockchip_get_efuse_value(np, "trim_l", &trim_l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) dev_warn(dev, "Missing trim_l property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (rockchip_get_efuse_value(np, "trim_h", &trim_h))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) dev_warn(dev, "Missing trim_h property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) if (rockchip_get_efuse_value(np, "trim_base", &trim_bsae))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) dev_warn(dev, "Missing trim_base property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) if (trim_l && trim_h && trim_bsae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) thermal->trim = tsadc->get_trim_code(thermal->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) (trim_h << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) trim_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) trim_bsae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) dev_info(dev, "tsadc trimmed value = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) thermal->trim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) thermal->tshut_temp += tsadc->trim_temp(thermal->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) rockchip_thermal_register_sensor(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) struct rockchip_thermal_data *thermal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) struct rockchip_thermal_sensor *sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) const struct rockchip_tsadc_chip *tsadc = thermal->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) tsadc->set_tshut_mode(thermal->grf, id, thermal->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) thermal->tshut_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) thermal->tshut_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) __func__, thermal->tshut_temp, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) sensor->thermal = thermal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) sensor->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) sensor, &rockchip_of_thermal_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) if (IS_ERR(sensor->tzd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) error = PTR_ERR(sensor->tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) dev_err(&pdev->dev, "failed to register sensor %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) id, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) * Reset TSADC Controller, reset all tsadc registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) * @reset: the reset controller of tsadc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) static void rockchip_thermal_reset_controller(struct reset_control *reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) reset_control_assert(reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) reset_control_deassert(reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) static void rockchip_dump_temperature(struct rockchip_thermal_data *thermal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) if (!thermal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) pdev = thermal->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) for (i = 0; i < thermal->chip->chn_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) struct thermal_zone_device *tz = sensor->tzd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) if (tz->temperature != THERMAL_TEMP_INVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) dev_warn(&pdev->dev, "channal %d: temperature(%d C)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) i, tz->temperature / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) if (thermal->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) pr_warn("THERMAL REGS:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) 32, 4, thermal->regs, 0x88, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) static int rockchip_thermal_panic(struct notifier_block *this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) unsigned long ev, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) struct rockchip_thermal_data *thermal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) thermal = container_of(this, struct rockchip_thermal_data, panic_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) rockchip_dump_temperature(thermal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) static int rockchip_thermal_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) struct rockchip_thermal_data *thermal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) match = of_match_node(of_rockchip_thermal_match, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) if (!thermal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) thermal->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) if (!thermal->chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) if (soc_is_px30s())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) thermal->chip = &px30s_tsadc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) if (soc_is_rk3308bs())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) thermal->chip = &rk3308bs_tsadc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) thermal->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) if (IS_ERR(thermal->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) return PTR_ERR(thermal->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) if (IS_ERR(thermal->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) if (PTR_ERR(thermal->reset) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) dev_err(&pdev->dev, "failed to get tsadc reset lines\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) return PTR_ERR(thermal->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) thermal->num_clks = devm_clk_bulk_get_all(&pdev->dev, &thermal->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) if (thermal->num_clks < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) error = clk_bulk_prepare_enable(thermal->num_clks, thermal->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) dev_err(&pdev->dev, "failed to prepare enable tsadc bulk clks: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) platform_set_drvdata(pdev, thermal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) if (thermal->chip->set_clk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) thermal->chip->set_clk_rate(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) thermal->chip->control(thermal->regs, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) rockchip_thermal_reset_controller(thermal->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) goto err_disable_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) thermal->chip->initialize(thermal->grf, thermal->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) thermal->tshut_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) if (thermal->tshut_mode == TSHUT_MODE_OTP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) thermal->pinctrl = devm_pinctrl_get(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) if (IS_ERR(thermal->pinctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) dev_err(&pdev->dev, "failed to find thermal pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) thermal->gpio_state = pinctrl_lookup_state(thermal->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) "gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) if (IS_ERR_OR_NULL(thermal->gpio_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) dev_err(&pdev->dev, "failed to find thermal gpio state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) thermal->otp_state = pinctrl_lookup_state(thermal->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) "otpout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) if (IS_ERR_OR_NULL(thermal->otp_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) dev_err(&pdev->dev, "failed to find thermal otpout state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) thermal_pinctrl_select_otp(thermal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) for (i = 0; i < thermal->chip->chn_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) error = rockchip_thermal_register_sensor(pdev, thermal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) &thermal->sensors[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) thermal->chip->chn_id[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) "failed to register sensor[%d] : error = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) i, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) goto err_disable_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) &rockchip_thermal_alarm_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) "rockchip_thermal", thermal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) "failed to request tsadc irq: %d\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) goto err_disable_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) thermal->chip->control(thermal->regs, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) if (thermal->chip->conversion_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) usleep_range(thermal->chip->conversion_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) thermal->chip->conversion_time + 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) for (i = 0; i < thermal->chip->chn_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) thermal->sensors[i].tzd->tzp->no_hwmon = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) "failed to register sensor %d with hwmon: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) i, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) thermal->panic_nb.notifier_call = rockchip_thermal_panic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) atomic_notifier_chain_register(&panic_notifier_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) &thermal->panic_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) dev_info(&pdev->dev, "tsadc is probed successfully!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) err_disable_clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) clk_bulk_disable_unprepare(thermal->num_clks, thermal->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) static int rockchip_thermal_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) for (i = 0; i < thermal->chip->chn_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) thermal_remove_hwmon_sysfs(sensor->tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) rockchip_thermal_toggle_sensor(sensor, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) thermal->chip->control(thermal->regs, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) clk_bulk_disable_unprepare(thermal->num_clks, thermal->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) static void rockchip_thermal_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) for (i = 0; i < thermal->chip->chn_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) int id = thermal->sensors[i].id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) if (thermal->tshut_mode != TSHUT_MODE_CRU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) thermal->chip->set_tshut_mode(thermal->grf, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) thermal->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) TSHUT_MODE_CRU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) if (thermal->tshut_mode == TSHUT_MODE_OTP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) thermal_pinctrl_select_gpio(thermal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) for (i = 0; i < thermal->chip->chn_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) thermal->chip->control(thermal->regs, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) clk_bulk_disable(thermal->num_clks, thermal->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) if (thermal->tshut_mode == TSHUT_MODE_OTP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) thermal_pinctrl_select_gpio(thermal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) static int __maybe_unused rockchip_thermal_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) error = clk_bulk_enable(thermal->num_clks, thermal->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) dev_err(dev, "failed to enable tsadc bulk clks: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) rockchip_thermal_reset_controller(thermal->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) thermal->chip->initialize(thermal->grf, thermal->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) thermal->tshut_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) for (i = 0; i < thermal->chip->chn_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) int id = thermal->sensors[i].id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) thermal->chip->set_tshut_mode(thermal->grf, id, thermal->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) thermal->tshut_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) error = thermal->chip->set_tshut_temp(&thermal->chip->table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) id, thermal->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) thermal->tshut_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) dev_err(dev, "%s: invalid tshut=%d, error=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) __func__, thermal->tshut_temp, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) thermal->chip->control(thermal->regs, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) if (thermal->chip->conversion_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) usleep_range(thermal->chip->conversion_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) thermal->chip->conversion_time + 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) for (i = 0; i < thermal->chip->chn_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) if (thermal->tshut_mode == TSHUT_MODE_OTP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) thermal_pinctrl_select_otp(thermal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) rockchip_thermal_suspend, rockchip_thermal_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) static struct platform_driver rockchip_thermal_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .name = "rockchip-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .pm = &rockchip_thermal_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .of_match_table = of_rockchip_thermal_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .probe = rockchip_thermal_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .remove = rockchip_thermal_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .shutdown = rockchip_thermal_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) module_platform_driver(rockchip_thermal_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) MODULE_AUTHOR("Rockchip, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) MODULE_ALIAS("platform:rockchip-thermal");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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