^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * under the terms and conditions of the GNU General Public License,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * version 2, as published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed in the hope it will be useful, but WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/pm_qos.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <soc/rockchip/scpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * If the temperature over a period of time High,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * the resulting TSHUT gave CRU module,let it reset the entire chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * or via GPIO give PMIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum tshut_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) TSHUT_MODE_CRU = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) TSHUT_MODE_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) enum tsadc_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) TSADC_AUTO_MODE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) TSHUT_USER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * the system Temperature Sensors tshut(tshut) polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * the bit 8 is tshut polarity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 0: low active, 1: high active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) enum tshut_polarity {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) TSHUT_LOW_ACTIVE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) TSHUT_HIGH_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define NUM_SENSORS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* TSADC V2 Sensor info define: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TSADCV2_USER_CON 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TSADCV2_AUTO_CON 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TSADCV2_INT_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TSADCV2_INT_PD 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TSADC_CLK_CYCLE_TIME 32 /* usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TSADCV3_DATA_MASK 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * The conversion table has the adc value and temperature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) enum adc_sort_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ADC_DECREMENT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ADC_INCREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TIME_OUT_TOTAL 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define INVALID_EFUSE_VALUE 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ACCESS_FORBIDDEN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MIN_TEMP (-40000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MAX_TEMP (125000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define INVALID_TEMP INT_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define BASE (1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define BASE_SHIFT (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define START_BOUNDING_COUNT (100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define HIGHER_BOUNDING_TEMP (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LOWER_BOUNDING_TEMP (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * struct tsadc_table - hold information about code and temp mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @code: raw code from tsadc ip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @temp: the mapping temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct tsadc_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned long code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * struct chip_tsadc_table - hold information about chip-specific differences
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @id: conversion table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @length: size of conversion table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @data_mask: mask to apply on data inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @mode: sort mode of this adc variant (incrementing or decrementing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct chip_tsadc_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const struct tsadc_table *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 data_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) enum adc_sort_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * struct rk3368_tsadc_chip - hold the private data of tsadc chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @chn_id[SOC_MAX_SENSORS]: the sensor id of chip correspond to the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @chn_num: the channel number of tsadc chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @tshut_temp: the hardware-controlled shutdown temperature value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @chip_tsadc_table: the chip-specific conversion table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @get_temp: get the temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @set_alarm_temp: set the high temperature interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @set_tshut_temp: set the hardware-controlled shutdown temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @set_tshut_mode: set the hardware-controlled shutdown mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct rk3368_tsadc_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int chn_id[NUM_SENSORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int chn_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) long hw_shut_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) enum tshut_mode tshut_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) enum tsadc_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) enum tshut_polarity tshut_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int latency_bound;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const struct chip_tsadc_table *temp_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Per-sensor methods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int (*get_temp)(const struct chip_tsadc_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int chn, void __iomem *reg, int *temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) void (*set_alarm_temp)(const struct chip_tsadc_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int chn, void __iomem *reg, int temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) void (*set_tshut_temp)(const struct chip_tsadc_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int chn, void __iomem *reg, int temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * struct rk3368_thermal_sensor - hold the information of thermal sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @ctx: pointer to the platform/configuration data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @tzd: pointer to a thermal zone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * @id: identifier of the thermal sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct rk3368_thermal_sensor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct rk3368_thermal_data *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct thermal_zone_device *tzd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * struct rk3368_thermal_data - hold the private data of thermal driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @chip: pointer to the platform/configuration data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @pdev: platform device of thermal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @reset: the reset controller of tsadc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @sensors[SOC_MAX_SENSORS]: the thermal sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @clk: the controller clock is divided by the external 24MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @pclk: the advanced peripherals bus clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @regs: the base address of tsadc controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @tshut_temp: the hardware-controlled shutdown temperature value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * @cpu_temp_adjust: efuse value used to ajust the temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * @gpu_temp_adjust: efuse value used to ajust the temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * @cpu_temp: the current cpu's temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @logout: switch to control log output or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @rk3368_thermal_kobj: node in sys fs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct rk3368_thermal_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) const struct rk3368_tsadc_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct reset_control *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct rk3368_thermal_sensor sensors[NUM_SENSORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) long hw_shut_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) enum tshut_mode tshut_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) enum tshut_polarity tshut_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int cpu_temp_adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int gpu_temp_adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int cpu_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) bool logout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct kobject *rk3368_thermal_kobj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct regulator *ref_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int regulator_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int latency_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int latency_bound;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct notifier_block tsadc_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static struct rk3368_thermal_data *thermal_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static DEFINE_MUTEX(thermal_reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static DEFINE_MUTEX(thermal_lat_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const struct tsadc_table code_table_3368[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0, MIN_TEMP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {106, MIN_TEMP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {108, -35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {110, -30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {112, -25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {114, -20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {116, -15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {118, -10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {120, -5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {122, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {124, 5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {126, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {128, 15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {130, 20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {132, 25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {134, 30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {136, 35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {138, 40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {140, 45000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {142, 50000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {144, 55000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {146, 60000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {148, 65000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {150, 70000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {152, 75000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {154, 80000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {156, 85000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {158, 90000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {160, 95000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {162, 100000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {163, 105000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {165, 110000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {167, 115000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {169, 120000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {171, MAX_TEMP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {TSADCV3_DATA_MASK, MAX_TEMP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const struct chip_tsadc_table tsadc_table_3368 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .id = code_table_3368,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .length = ARRAY_SIZE(code_table_3368),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .data_mask = TSADCV3_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .mode = ADC_INCREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int rk3368_get_ajust_code(struct device_node *np, int *ajust_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct nvmem_cell *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned char *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) cell = of_nvmem_cell_get(np, "temp_adjust");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (IS_ERR(cell)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pr_err("avs failed to get temp_adjust cell\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return PTR_ERR(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) buf = (unsigned char *)nvmem_cell_read(cell, &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) nvmem_cell_put(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (IS_ERR(buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return PTR_ERR(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (buf[0] == INVALID_EFUSE_VALUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (buf[0] & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) *ajust_code = -(buf[0] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) *ajust_code = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static struct rk3368_thermal_data *rk3368_thermal_get_data(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) WARN_ON(!thermal_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return thermal_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int rk3368_temp_to_code(const struct chip_tsadc_table *tmp_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) long temp, u32 *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int low = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int high = tmp_table->length - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned int mid = (low + high) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned long denom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) *code = tmp_table->data_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) WARN_ON(tmp_table->length < 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (temp < tmp_table->id[low].temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return -EAGAIN; /* Incorrect reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) while (low <= high) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (temp == tmp_table->id[mid].temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) *code = tmp_table->id[mid].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) } else if (temp > tmp_table->id[mid].temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) low = mid + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) high = mid - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) mid = (low + high) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * The 5C granularity provided by the table is too much. Let's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * assume that the relationship between sensor readings and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * temperature between 2 table entries is linear and interpolate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * to produce less granular result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (*code == tmp_table->data_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) num = abs(tmp_table->id[low].code - tmp_table->id[high].code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) num *= abs(tmp_table->id[high].temp - temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) denom = abs(tmp_table->id[high].temp - tmp_table->id[low].temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) *code = tmp_table->id[high].code + (num / denom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int rk3368_code_to_temp(const struct chip_tsadc_table *tmp_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 code, int *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned int low = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned int high = tmp_table->length - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned int mid = (low + high) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned long denom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) *temp = INVALID_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) WARN_ON(tmp_table->length < 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) switch (tmp_table->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case ADC_DECREMENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) code &= tmp_table->data_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (code < tmp_table->id[high].code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return -EAGAIN; /* Incorrect reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) while (low <= high) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (code == tmp_table->id[mid].code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) *temp = tmp_table->id[mid].temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) } else if (code < tmp_table->id[mid].code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) low = mid + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) high = mid - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) mid = (low + high) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case ADC_INCREMENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) code &= tmp_table->data_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (code < tmp_table->id[low].code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return -EAGAIN; /* Incorrect reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) while (low <= high) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (code == tmp_table->id[mid].code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) *temp = tmp_table->id[mid].temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) } else if (code > tmp_table->id[mid].code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) low = mid + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) high = mid - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) mid = (low + high) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) pr_err("Invalid the conversion table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * The 5C granularity provided by the table is too much. Let's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * assume that the relationship between sensor readings and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * temperature between 2 table entries is linear and interpolate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * to produce less granular result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (*temp == INVALID_TEMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) num = abs(tmp_table->id[low].temp - tmp_table->id[high].temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) num *= abs(tmp_table->id[high].code - code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) denom = abs(tmp_table->id[high].code - tmp_table->id[low].code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) *temp = tmp_table->id[high].temp + (num / denom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const struct rk3368_tsadc_chip rk3368_tsadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .latency_bound = 50000, /* default 50000 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .hw_shut_temp = 125000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .mode = TSHUT_USER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .chn_num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .chn_id[0] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .chn_id[1] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .temp_table = &tsadc_table_3368,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int rk3368_configure_from_dt(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct rk3368_thermal_data *thermal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 shut_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int lat_bound;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (of_property_read_u32(np, "clock-frequency", &rate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dev_err(dev, "Missing clock-frequency property in the DT.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = clk_set_rate(thermal->clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) cycle = DIV_ROUND_UP(1000000000, rate) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (scpi_thermal_set_clk_cycle(cycle)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_err(dev, "scpi_thermal_set_clk_cycle error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (of_property_read_u32(np, "hw-shut-temp", &shut_temp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) "Missing tshut temp property, using default %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) thermal->chip->hw_shut_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) thermal->hw_shut_temp = thermal->chip->hw_shut_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) thermal->hw_shut_temp = shut_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (of_property_read_u32(np, "latency-bound", &lat_bound)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) "Missing latency-bound property, using default %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) thermal->chip->latency_bound);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) thermal->latency_bound = thermal->chip->latency_bound;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) thermal->latency_bound = lat_bound;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (thermal->hw_shut_temp > INT_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_err(dev, "Invalid tshut temperature specified: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) thermal->hw_shut_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int predict_temp(int temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) int cov_q = 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int cov_r = 542;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int temp_mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int temp_now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int prob_mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int prob_now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int temp_last = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int prob_last = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int bounding_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct rk3368_thermal_data *ctx = rk3368_thermal_get_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return INVALID_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (bounding_cnt++ > START_BOUNDING_COUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) bounding_cnt = START_BOUNDING_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (temp - temp_last > HIGHER_BOUNDING_TEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) temp = temp_last + HIGHER_BOUNDING_TEMP / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (temp_last - temp > LOWER_BOUNDING_TEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) temp = temp_last - LOWER_BOUNDING_TEMP / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) temp_mid = temp_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) prob_mid = prob_last + cov_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) gain = (prob_mid * BASE) / (prob_mid + cov_r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) temp_now = temp_mid + (gain * (temp - temp_mid) >> BASE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) prob_now = ((BASE - gain) * prob_mid) >> BASE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) prob_last = prob_now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) temp_last = temp_now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (ctx->logout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pr_info("prob_now %d, temp_last %d, temp %d gain %d", prob_now,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) temp_now, temp, gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return temp_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int get_raw_code_internal(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 val_cpu_pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int val_cpu = INVALID_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct rk3368_thermal_data *ctx = rk3368_thermal_get_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return INVALID_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* power up, channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) writel_relaxed(0x18, ctx->regs + TSADCV2_USER_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) udelay(TSADC_CLK_CYCLE_TIME * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* start working */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) writel_relaxed(0x38, ctx->regs + TSADCV2_USER_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) udelay(TSADC_CLK_CYCLE_TIME * 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* try 50 times */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) for (i = 0; i < 50; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) udelay(TSADC_CLK_CYCLE_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) val_cpu_pd = readl_relaxed(ctx->regs + TSADCV2_INT_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if ((val_cpu_pd & 0x100) == 0x100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /*clear eoc inter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) writel_relaxed(0x100, ctx->regs + TSADCV2_INT_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /*read adc data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) val_cpu = readl_relaxed(ctx->regs + TSADCV2_DATA(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /*power down, channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) writel_relaxed(0x0, ctx->regs + TSADCV2_USER_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return val_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define RAW_CODE_MIN (50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define RAW_CODE_MAX (225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int rk3368_get_raw_code(struct rk3368_thermal_data *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int old_data = 130;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int tsadc_data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (ctx->latency_req > ctx->latency_bound)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) tsadc_data = scpi_thermal_get_temperature();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) tsadc_data = get_raw_code_internal();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if ((tsadc_data < RAW_CODE_MIN) || (tsadc_data > RAW_CODE_MAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) tsadc_data = old_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) old_data = tsadc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return tsadc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int rk3368_convert_code_2_temp(int tsadc_data, int voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct rk3368_thermal_data *ctx = rk3368_thermal_get_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) const struct rk3368_tsadc_chip *tsadc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) int out_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int old_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) int data_adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u32 code_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u32 tmp_code1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u32 tmp_code2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return INVALID_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) tsadc = ctx->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) rk3368_temp_to_code(tsadc->temp_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ctx->cpu_temp_adjust * 1000, &tmp_code1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) rk3368_temp_to_code(tsadc->temp_table, 0, &tmp_code2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) data_adjust = tmp_code1 - tmp_code2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) code_temp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ((tsadc_data * voltage - data_adjust * 1000000) + 500000) / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) rk3368_code_to_temp(tsadc->temp_table, code_temp, &out_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (ctx->logout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) pr_info("cpu code temp:[%d, %d], voltage: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) tsadc_data, out_temp / 1000, voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if ((out_temp < MIN_TEMP) || (out_temp > MAX_TEMP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) out_temp = old_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) old_temp = out_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ctx->cpu_temp = out_temp / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return out_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static int rk3368_thermal_set_trips(void *_sensor, int low, int high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static int rk3368_thermal_get_temp(void *_sensor, int *out_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int raw_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct rk3368_thermal_data *ctx = rk3368_thermal_get_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return INVALID_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) pdev = ctx->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) mutex_lock(&thermal_reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) raw_code = rk3368_get_raw_code(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) temp = rk3368_convert_code_2_temp(raw_code, ctx->regulator_uv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) *out_temp = predict_temp(temp / 1000) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) mutex_unlock(&thermal_reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static const struct thermal_zone_of_device_ops rk3368_of_thermal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .get_temp = rk3368_thermal_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .set_trips = rk3368_thermal_set_trips,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) rk3368_thermal_register_sensor(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct rk3368_thermal_data *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct rk3368_thermal_sensor *sensor, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) sensor->ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) sensor->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) &rk3368_of_thermal_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (IS_ERR(sensor->tzd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) error = PTR_ERR(sensor->tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dev_err(&pdev->dev, "failed to register sensor %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) id, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * Reset TSADC Controller, reset all tsadc registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static void rk3368_thermal_reset_controller(struct reset_control *reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) reset_control_assert(reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) reset_control_deassert(reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static ssize_t rk3368_thermal_temp_adjust_test_store(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct kobj_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) *attr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) size_t n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct rk3368_thermal_data *ctx = rk3368_thermal_get_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int getdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) char cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) const char *buftmp = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ret = sscanf(buftmp, "%c ", &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) case 'c':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ret = sscanf(buftmp, "%c %d", &cmd, &getdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (ret != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ctx->cpu_temp_adjust = getdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) pr_info("get cpu_temp_adjust value = %d\n", getdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) case 'g':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ret = sscanf(buftmp, "%c %d", &cmd, &getdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (ret != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ctx->gpu_temp_adjust = getdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) pr_info("get gpu_temp_adjust value = %d\n", getdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) pr_info("Unknown command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static ssize_t rk3368_thermal_temp_adjust_test_show(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct kobj_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct rk3368_thermal_data *ctx = rk3368_thermal_get_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) char *str = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) str +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) sprintf(str, "rk3368_thermal: cpu:%d, gpu:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ctx->cpu_temp_adjust, ctx->gpu_temp_adjust);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return (str - buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static ssize_t rk3368_thermal_temp_test_store(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct kobj_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) const char *buf, size_t n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct rk3368_thermal_data *ctx = rk3368_thermal_get_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) char cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) const char *buftmp = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ret = sscanf(buftmp, "%c", &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) case 't':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ctx->logout = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) case 'f':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ctx->logout = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) pr_info("Unknown command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static ssize_t rk3368_thermal_temp_test_show(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct kobj_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct rk3368_thermal_data *ctx = rk3368_thermal_get_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) char *str = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) str += sprintf(str, "current cpu_temp:%d\n", ctx->cpu_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return (str - buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct rk3368_thermal_attribute {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct attribute attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ssize_t (*show) (struct kobject *kobj, struct kobj_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ssize_t (*store) (struct kobject *kobj, struct kobj_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) const char *buf, size_t n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static struct rk3368_thermal_attribute rk3368_thermal_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /*node_name permission show_func store_func */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) __ATTR(temp_adjust, 0644,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) rk3368_thermal_temp_adjust_test_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) rk3368_thermal_temp_adjust_test_store),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) __ATTR(temp, 0644, rk3368_thermal_temp_test_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) rk3368_thermal_temp_test_store),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static void rk3368_dump_temperature(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct rk3368_thermal_data *ctx = rk3368_thermal_get_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) pdev = ctx->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (ctx->cpu_temp != INVALID_TEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dev_warn(&pdev->dev, "cpu channal temperature(%d C)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ctx->cpu_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (ctx->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) pr_warn("THERMAL REGS:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) 32, 4, ctx->regs, 0x88, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) EXPORT_SYMBOL_GPL(rk3368_dump_temperature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static int rk3368_thermal_panic(struct notifier_block *this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) unsigned long ev, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) rk3368_dump_temperature();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static struct notifier_block rk3368_thermal_panic_block = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .notifier_call = rk3368_thermal_panic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static int rk3368_thermal_notify(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct rk3368_thermal_data *ctx = rk3368_thermal_get_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) pdev = ctx->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (event & REGULATOR_EVENT_PRE_VOLTAGE_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) mutex_lock(&thermal_reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) } else if (event & (REGULATOR_EVENT_VOLTAGE_CHANGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) REGULATOR_EVENT_ABORT_VOLTAGE_CHANGE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ctx->regulator_uv = (unsigned long)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (mutex_is_locked(&thermal_reg_mutex))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) mutex_unlock(&thermal_reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * This function gets called when a part of the kernel has a new latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * requirement. We record this requirement to instruct us to get temperature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static int tsadc_latency_notify(struct notifier_block *b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) unsigned long l, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct rk3368_thermal_data *ctx = rk3368_thermal_get_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) mutex_lock(&thermal_lat_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ctx->latency_req = (int)l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) mutex_unlock(&thermal_lat_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static struct notifier_block tsadc_latency_notifier = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .notifier_call = tsadc_latency_notify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static inline int tsadc_add_latency_notifier(struct notifier_block *n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return pm_qos_add_notifier(PM_QOS_CPU_DMA_LATENCY, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static inline int tsadc_remove_latency_notifier(struct notifier_block *n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return pm_qos_remove_notifier(PM_QOS_CPU_DMA_LATENCY, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static const struct of_device_id of_rk3368_thermal_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .compatible = "rockchip,rk3368-tsadc-legacy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .data = (void *)&rk3368_tsadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) { /* end */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) MODULE_DEVICE_TABLE(of, of_rk3368_thermal_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static int rk3368_thermal_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct rk3368_thermal_data *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) int ajust_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) int latency_req = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) match = of_match_node(of_rk3368_thermal_match, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dev_err(&pdev->dev, "no irq resource?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ctx = devm_kzalloc(&pdev->dev, sizeof(struct rk3368_thermal_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ctx->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ctx->chip = (const struct rk3368_tsadc_chip *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (!ctx->chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ctx->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (IS_ERR(ctx->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return PTR_ERR(ctx->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ctx->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (IS_ERR(ctx->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) error = PTR_ERR(ctx->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ctx->clk = devm_clk_get(&pdev->dev, "tsadc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (IS_ERR(ctx->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) error = PTR_ERR(ctx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ctx->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (IS_ERR(ctx->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) error = PTR_ERR(ctx->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) error = clk_prepare_enable(ctx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) dev_err(&pdev->dev, "failed to enable converter clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) error = clk_prepare_enable(ctx->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) dev_err(&pdev->dev, "failed to enable pclk: %d\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) rk3368_thermal_reset_controller(ctx->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) error = rk3368_configure_from_dt(&pdev->dev, np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) goto err_disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) thermal_ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ctx->ref_regulator = devm_regulator_get_optional(&pdev->dev, "tsadc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (IS_ERR(ctx->ref_regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) error = PTR_ERR(ctx->ref_regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (error != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) "couldn't get regulator tsadc-supply\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) goto err_disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) ctx->tsadc_nb.notifier_call = rk3368_thermal_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* register regulator notifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) error =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) regulator_register_notifier(ctx->ref_regulator, &ctx->tsadc_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) dev_err(&pdev->dev, "regulator notifier request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) goto err_disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) uv = regulator_get_voltage(ctx->ref_regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (uv <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) dev_WARN(&pdev->dev, "regulator get failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) uv = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) mutex_lock(&thermal_reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (!ctx->regulator_uv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ctx->regulator_uv = uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) mutex_unlock(&thermal_reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) error = tsadc_add_latency_notifier(&tsadc_latency_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dev_err(&pdev->dev, "latency notifier request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) goto err_unreg_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) latency_req = pm_qos_request(PM_QOS_CPU_DMA_LATENCY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) mutex_lock(&thermal_lat_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (!ctx->latency_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) ctx->latency_req = latency_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) mutex_unlock(&thermal_lat_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) rk3368_get_ajust_code(np, &ajust_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ctx->cpu_temp_adjust = (int)ajust_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) for (i = 0; i < ctx->chip->chn_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) error = rk3368_thermal_register_sensor(pdev, ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) &ctx->sensors[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ctx->chip->chn_id[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) "failed to register thermal sensor %d : error= %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) i, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) for (j = 0; j < i; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) thermal_zone_of_sensor_unregister(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) ctx->sensors[j].tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) goto err_remove_latancy_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ctx->rk3368_thermal_kobj =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) kobject_create_and_add("rk3368_thermal", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (!ctx->rk3368_thermal_kobj) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) "failed to creat debug node : error= %d\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) goto err_remove_latancy_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) for (i = 0; i < ARRAY_SIZE(rk3368_thermal_attrs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) error =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) sysfs_create_file(ctx->rk3368_thermal_kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) &rk3368_thermal_attrs[i].attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) "failed to register thermal sensor %d : error= %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) i, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) for (j = 0; j < i; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) sysfs_remove_file(ctx->rk3368_thermal_kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) &rk3368_thermal_attrs[j].attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) goto err_remove_latancy_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) platform_set_drvdata(pdev, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) atomic_notifier_chain_register(&panic_notifier_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) &rk3368_thermal_panic_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ctx->cpu_temp = INVALID_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) pr_info("rk3368 tsadc probed successfully\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) err_remove_latancy_notifier:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) tsadc_remove_latency_notifier(&tsadc_latency_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) err_unreg_notifier:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) regulator_unregister_notifier(ctx->ref_regulator, &ctx->tsadc_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) err_disable_pclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) clk_disable_unprepare(ctx->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) clk_disable_unprepare(ctx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static int rk3368_thermal_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct rk3368_thermal_data *ctx = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) atomic_notifier_chain_unregister(&panic_notifier_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) &rk3368_thermal_panic_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) for (i = 0; i < ctx->chip->chn_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct rk3368_thermal_sensor *sensor = &ctx->sensors[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) thermal_zone_of_sensor_unregister(&pdev->dev, sensor->tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) tsadc_remove_latency_notifier(&tsadc_latency_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) regulator_unregister_notifier(ctx->ref_regulator, &ctx->tsadc_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) clk_disable_unprepare(ctx->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) clk_disable_unprepare(ctx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static int __maybe_unused rk3368_thermal_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct rk3368_thermal_data *ctx = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) clk_disable(ctx->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) clk_disable(ctx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static int __maybe_unused rk3368_thermal_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct rk3368_thermal_data *ctx = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) error = clk_enable(ctx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) error = clk_enable(ctx->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) clk_disable(ctx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) rk3368_thermal_reset_controller(ctx->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) static SIMPLE_DEV_PM_OPS(rk3368_thermal_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) rk3368_thermal_suspend, rk3368_thermal_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static struct platform_driver rk3368_thermal_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .name = "rk3368-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .pm = &rk3368_thermal_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .of_match_table = of_rk3368_thermal_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .probe = rk3368_thermal_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .remove = rk3368_thermal_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /* rk3368 thermal needs a clock source of 32k from rk818, so this init process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * is postponed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static int __init rk3368_thermal_init_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return platform_driver_register(&rk3368_thermal_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) late_initcall(rk3368_thermal_init_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) MODULE_AUTHOR("Rockchip, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) MODULE_ALIAS("platform:rk3368-thermal");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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