Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright 2016 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/units.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "thermal_core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "thermal_hwmon.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SITES_MAX		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define TMR_DISABLE		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define TMR_ME			0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define TMR_ALPF		0x0c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define TMR_ALPF_V2		0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define TMTMIR_DEFAULT	0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define TIER_DISABLE	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TEUMR0_V2		0x51009c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TMSARA_V2		0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define TMU_VER1		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TMU_VER2		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define REGS_TMR	0x000	/* Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TMR_DISABLE	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TMR_ME		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TMR_ALPF	0x0c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TMR_MSITE_ALL	GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define REGS_TMTMIR	0x008	/* Temperature measurement interval Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TMTMIR_DEFAULT	0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define REGS_V2_TMSR	0x008	/* monitor site register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define REGS_V2_TMTMIR	0x00c	/* Temperature measurement interval Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define REGS_TIER	0x020	/* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define TIER_DISABLE	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define REGS_TTCFGR	0x080	/* Temperature Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define REGS_TSCFGR	0x084	/* Sensor Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define REGS_TRITSR(n)	(0x100 + 16 * (n)) /* Immediate Temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 					    * Site Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 					    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define TRITSR_V	BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define REGS_V2_TMSAR(n)	(0x304 + 16 * (n))	/* TMU monitoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 						* site adjustment register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 						*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define REGS_TTRnCR(n)	(0xf10 + 4 * (n)) /* Temperature Range n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 					   * Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 					   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define REGS_IPBRR(n)		(0xbf8 + 4 * (n)) /* IP Block Revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 						   * Register n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 						   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define REGS_V2_TEUMR(n)	(0xf00 + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * Thermal zone data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) struct qoriq_sensor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	int				id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) struct qoriq_tmu_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	int ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct qoriq_sensor	sensor[SITES_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static struct qoriq_tmu_data *qoriq_sensor_to_data(struct qoriq_sensor *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	return container_of(s, struct qoriq_tmu_data, sensor[s->id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static int tmu_get_temp(void *p, int *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct qoriq_sensor *qsensor = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct qoriq_tmu_data *qdata = qoriq_sensor_to_data(qsensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 * REGS_TRITSR(id) has the following layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 * For TMU Rev1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 * 31  ... 7 6 5 4 3 2 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 *  V          TEMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 * Where V bit signifies if the measurement is ready and is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	 * within sensor range. TEMP is an 8 bit value representing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 * temperature in Celsius.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	 * For TMU Rev2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	 * 31  ... 8 7 6 5 4 3 2 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 *  V          TEMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 * Where V bit signifies if the measurement is ready and is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 * within sensor range. TEMP is an 9 bit value representing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 * temperature in KelVin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if (regmap_read_poll_timeout(qdata->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 				     REGS_TRITSR(qsensor->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 				     val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 				     val & TRITSR_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 				     USEC_PER_MSEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 				     10 * USEC_PER_MSEC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (qdata->ver == TMU_VER1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		*temp = (val & GENMASK(7, 0)) * MILLIDEGREE_PER_DEGREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		*temp = kelvin_to_millicelsius(val & GENMASK(8, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct thermal_zone_of_device_ops tmu_tz_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.get_temp = tmu_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int qoriq_tmu_register_tmu_zone(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 				       struct qoriq_tmu_data *qdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (qdata->ver == TMU_VER1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		regmap_write(qdata->regmap, REGS_TMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			     TMR_MSITE_ALL | TMR_ME | TMR_ALPF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		regmap_write(qdata->regmap, REGS_V2_TMSR, TMR_MSITE_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		regmap_write(qdata->regmap, REGS_TMR, TMR_ME | TMR_ALPF_V2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	for (id = 0; id < SITES_MAX; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		struct thermal_zone_device *tzd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		struct qoriq_sensor *sensor = &qdata->sensor[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		sensor->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		tzd = devm_thermal_zone_of_sensor_register(dev, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 							   sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 							   &tmu_tz_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		ret = PTR_ERR_OR_ZERO(tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			if (ret == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			regmap_write(qdata->regmap, REGS_TMR, TMR_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		if (devm_thermal_add_hwmon_sysfs(tzd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				 "Failed to add hwmon sysfs attributes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int qoriq_tmu_calibration(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 				 struct qoriq_tmu_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	int i, val, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	u32 range[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	const u32 *calibration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	len = of_property_count_u32_elems(np, "fsl,tmu-range");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (len < 0 || len > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		dev_err(dev, "invalid range data.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	val = of_property_read_u32_array(np, "fsl,tmu-range", range, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (val != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		dev_err(dev, "failed to read range data.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* Init temperature range registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		regmap_write(data->regmap, REGS_TTRnCR(i), range[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	calibration = of_get_property(np, "fsl,tmu-calibration", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (calibration == NULL || len % 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		dev_err(dev, "invalid calibration data.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	for (i = 0; i < len; i += 8, calibration += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		val = of_read_number(calibration, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		regmap_write(data->regmap, REGS_TTCFGR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		val = of_read_number(calibration + 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		regmap_write(data->regmap, REGS_TSCFGR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	/* Disable interrupt, using polling instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	regmap_write(data->regmap, REGS_TIER, TIER_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	/* Set update_interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (data->ver == TMU_VER1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		regmap_write(data->regmap, REGS_TMTMIR, TMTMIR_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		regmap_write(data->regmap, REGS_V2_TMTMIR, TMTMIR_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		regmap_write(data->regmap, REGS_V2_TEUMR(0), TEUMR0_V2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		for (i = 0; i < SITES_MAX; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			regmap_write(data->regmap, REGS_V2_TMSAR(i), TMSARA_V2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/* Disable monitoring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const struct regmap_range qoriq_yes_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	regmap_reg_range(REGS_TMR, REGS_TSCFGR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	regmap_reg_range(REGS_V2_TEUMR(0), REGS_V2_TEUMR(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	regmap_reg_range(REGS_V2_TMSAR(0), REGS_V2_TMSAR(15)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	regmap_reg_range(REGS_IPBRR(0), REGS_IPBRR(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	/* Read only registers below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const struct regmap_access_table qoriq_wr_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.yes_ranges	= qoriq_yes_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.n_yes_ranges	= ARRAY_SIZE(qoriq_yes_ranges) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct regmap_access_table qoriq_rd_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.yes_ranges	= qoriq_yes_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.n_yes_ranges	= ARRAY_SIZE(qoriq_yes_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void qoriq_tmu_action(void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	struct qoriq_tmu_data *data = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	clk_disable_unprepare(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int qoriq_tmu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	u32 ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct qoriq_tmu_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	const bool little_endian = of_property_read_bool(np, "little-endian");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	const enum regmap_endian format_endian =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		little_endian ? REGMAP_ENDIAN_LITTLE : REGMAP_ENDIAN_BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	const struct regmap_config regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.reg_bits		= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		.val_bits		= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		.reg_stride		= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		.rd_table		= &qoriq_rd_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.wr_table		= &qoriq_wr_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		.val_format_endian	= format_endian,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		.max_register		= SZ_4K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	data = devm_kzalloc(dev, sizeof(struct qoriq_tmu_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			    GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	ret = PTR_ERR_OR_ZERO(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		dev_err(dev, "Failed to get memory region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	data->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	ret = PTR_ERR_OR_ZERO(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		dev_err(dev, "Failed to init regmap (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	data->clk = devm_clk_get_optional(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (IS_ERR(data->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		return PTR_ERR(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	ret = clk_prepare_enable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		dev_err(dev, "Failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	ret = devm_add_action_or_reset(dev, qoriq_tmu_action, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	/* version register offset at: 0xbf8 on both v1 and v2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	ret = regmap_read(data->regmap, REGS_IPBRR(0), &ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		dev_err(&pdev->dev, "Failed to read IP block version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	data->ver = (ver >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	qoriq_tmu_init_device(data);	/* TMU initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	ret = qoriq_tmu_calibration(dev, data);	/* TMU calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	ret = qoriq_tmu_register_tmu_zone(dev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		dev_err(dev, "Failed to register sensors\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	platform_set_drvdata(pdev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int __maybe_unused qoriq_tmu_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	struct qoriq_tmu_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	ret = regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	clk_disable_unprepare(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static int __maybe_unused qoriq_tmu_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	struct qoriq_tmu_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	ret = clk_prepare_enable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	/* Enable monitoring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	return regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, TMR_ME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static SIMPLE_DEV_PM_OPS(qoriq_tmu_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			 qoriq_tmu_suspend, qoriq_tmu_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const struct of_device_id qoriq_tmu_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	{ .compatible = "fsl,qoriq-tmu", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	{ .compatible = "fsl,imx8mq-tmu", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MODULE_DEVICE_TABLE(of, qoriq_tmu_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static struct platform_driver qoriq_tmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		.name		= "qoriq_thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		.pm		= &qoriq_tmu_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		.of_match_table	= qoriq_tmu_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	.probe	= qoriq_tmu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) module_platform_driver(qoriq_tmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MODULE_AUTHOR("Jia Hongtao <hongtao.jia@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MODULE_DESCRIPTION("QorIQ Thermal Monitoring Unit driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) MODULE_LICENSE("GPL v2");