^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __QCOM_TSENS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __QCOM_TSENS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define ONE_PT_CALIB 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define ONE_PT_CALIB2 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define TWO_PT_CALIB 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CAL_DEGC_PT1 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CAL_DEGC_PT2 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SLOPE_FACTOR 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SLOPE_DEFAULT 3200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define THRESHOLD_MAX_ADC_CODE 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define THRESHOLD_MIN_ADC_CODE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct tsens_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* IP version numbers in ascending order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) enum tsens_ver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) VER_0_1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) VER_1_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) VER_2_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) enum tsens_irq_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) LOWER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) UPPER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * struct tsens_sensor - data for each sensor connected to the tsens device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @priv: tsens device instance that this sensor is connected to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @tzd: pointer to the thermal zone that this sensor is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @offset: offset of temperature adjustment curve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @hw_id: HW ID can be used in case of platform-specific IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @slope: slope of temperature adjustment curve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @status: 8960-specific variable to track 8960 and 8660 status register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct tsens_sensor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct tsens_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct thermal_zone_device *tzd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int hw_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int slope;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * struct tsens_ops - operations as supported by the tsens device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @init: Function to initialize the tsens device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @calibrate: Function to calibrate the tsens device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @get_temp: Function which returns the temp in millidegC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @enable: Function to enable (clocks/power) tsens device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @disable: Function to disable the tsens device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @suspend: Function to suspend the tsens device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @resume: Function to resume the tsens device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @get_trend: Function to get the thermal/temp trend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct tsens_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* mandatory callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int (*init)(struct tsens_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int (*calibrate)(struct tsens_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int (*get_temp)(const struct tsens_sensor *s, int *temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* optional callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int (*enable)(struct tsens_priv *priv, int i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void (*disable)(struct tsens_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int (*suspend)(struct tsens_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int (*resume)(struct tsens_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int (*get_trend)(struct tsens_sensor *s, enum thermal_trend *trend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) [_name##_##9] = REG_FIELD(_offset + 36, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) [_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define REG_FIELD_FOR_EACH_SENSOR16(_name, _offset, _startbit, _stopbit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [_name##_##9] = REG_FIELD(_offset + 36, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [_name##_##11] = REG_FIELD(_offset + 44, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [_name##_##12] = REG_FIELD(_offset + 48, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [_name##_##13] = REG_FIELD(_offset + 52, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [_name##_##14] = REG_FIELD(_offset + 56, _startbit, _stopbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [_name##_##15] = REG_FIELD(_offset + 60, _startbit, _stopbit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define REG_FIELD_SPLIT_BITS_0_15(_name, _offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) [_name##_##0] = REG_FIELD(_offset, 0, 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [_name##_##1] = REG_FIELD(_offset, 1, 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) [_name##_##2] = REG_FIELD(_offset, 2, 2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) [_name##_##3] = REG_FIELD(_offset, 3, 3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [_name##_##4] = REG_FIELD(_offset, 4, 4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) [_name##_##5] = REG_FIELD(_offset, 5, 5), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) [_name##_##6] = REG_FIELD(_offset, 6, 6), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [_name##_##7] = REG_FIELD(_offset, 7, 7), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) [_name##_##8] = REG_FIELD(_offset, 8, 8), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [_name##_##9] = REG_FIELD(_offset, 9, 9), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) [_name##_##10] = REG_FIELD(_offset, 10, 10), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [_name##_##11] = REG_FIELD(_offset, 11, 11), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) [_name##_##12] = REG_FIELD(_offset, 12, 12), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [_name##_##13] = REG_FIELD(_offset, 13, 13), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [_name##_##14] = REG_FIELD(_offset, 14, 14), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [_name##_##15] = REG_FIELD(_offset, 15, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define REG_FIELD_SPLIT_BITS_16_31(_name, _offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [_name##_##0] = REG_FIELD(_offset, 16, 16), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [_name##_##1] = REG_FIELD(_offset, 17, 17), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [_name##_##2] = REG_FIELD(_offset, 18, 18), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [_name##_##3] = REG_FIELD(_offset, 19, 19), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [_name##_##4] = REG_FIELD(_offset, 20, 20), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [_name##_##5] = REG_FIELD(_offset, 21, 21), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [_name##_##6] = REG_FIELD(_offset, 22, 22), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [_name##_##7] = REG_FIELD(_offset, 23, 23), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [_name##_##8] = REG_FIELD(_offset, 24, 24), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [_name##_##9] = REG_FIELD(_offset, 25, 25), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [_name##_##10] = REG_FIELD(_offset, 26, 26), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [_name##_##11] = REG_FIELD(_offset, 27, 27), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) [_name##_##12] = REG_FIELD(_offset, 28, 28), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [_name##_##13] = REG_FIELD(_offset, 29, 29), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [_name##_##14] = REG_FIELD(_offset, 30, 30), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) [_name##_##15] = REG_FIELD(_offset, 31, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * reg_field IDs to use as an index into an array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * If you change the order of the entries, check the devm_regmap_field_alloc()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * calls in init_common()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) enum regfield_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* ----- SROT ------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* HW_VER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) VER_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) VER_MINOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) VER_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* CTRL_OFFSET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) TSENS_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) TSENS_SW_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) SENSOR_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) CODE_OR_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* ----- TM ------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* TRDY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) TRDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* INTERRUPT ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) INT_EN, /* v2+ has separate enables for crit, upper and lower irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) LAST_TEMP_0, /* Last temperature reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) LAST_TEMP_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) LAST_TEMP_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) LAST_TEMP_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) LAST_TEMP_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) LAST_TEMP_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) LAST_TEMP_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) LAST_TEMP_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) LAST_TEMP_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) LAST_TEMP_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) LAST_TEMP_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) LAST_TEMP_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) LAST_TEMP_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) LAST_TEMP_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) LAST_TEMP_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) LAST_TEMP_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) VALID_0, /* VALID reading or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) VALID_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) VALID_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) VALID_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) VALID_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) VALID_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) VALID_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) VALID_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) VALID_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) VALID_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) VALID_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) VALID_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) VALID_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) VALID_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) VALID_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) VALID_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) LOWER_STATUS_0, /* LOWER threshold violated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) LOWER_STATUS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) LOWER_STATUS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) LOWER_STATUS_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) LOWER_STATUS_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) LOWER_STATUS_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) LOWER_STATUS_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) LOWER_STATUS_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) LOWER_STATUS_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) LOWER_STATUS_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) LOWER_STATUS_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) LOWER_STATUS_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) LOWER_STATUS_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) LOWER_STATUS_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) LOWER_STATUS_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) LOWER_STATUS_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) LOW_INT_STATUS_0, /* LOWER interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) LOW_INT_STATUS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) LOW_INT_STATUS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) LOW_INT_STATUS_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) LOW_INT_STATUS_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) LOW_INT_STATUS_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) LOW_INT_STATUS_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) LOW_INT_STATUS_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) LOW_INT_STATUS_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) LOW_INT_STATUS_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) LOW_INT_STATUS_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) LOW_INT_STATUS_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) LOW_INT_STATUS_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) LOW_INT_STATUS_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) LOW_INT_STATUS_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) LOW_INT_STATUS_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) LOW_INT_CLEAR_0, /* LOWER interrupt clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) LOW_INT_CLEAR_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) LOW_INT_CLEAR_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) LOW_INT_CLEAR_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) LOW_INT_CLEAR_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) LOW_INT_CLEAR_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) LOW_INT_CLEAR_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) LOW_INT_CLEAR_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) LOW_INT_CLEAR_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) LOW_INT_CLEAR_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) LOW_INT_CLEAR_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) LOW_INT_CLEAR_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) LOW_INT_CLEAR_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) LOW_INT_CLEAR_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) LOW_INT_CLEAR_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) LOW_INT_CLEAR_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) LOW_INT_MASK_0, /* LOWER interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) LOW_INT_MASK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) LOW_INT_MASK_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) LOW_INT_MASK_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) LOW_INT_MASK_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) LOW_INT_MASK_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) LOW_INT_MASK_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) LOW_INT_MASK_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) LOW_INT_MASK_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) LOW_INT_MASK_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) LOW_INT_MASK_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) LOW_INT_MASK_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) LOW_INT_MASK_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) LOW_INT_MASK_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) LOW_INT_MASK_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) LOW_INT_MASK_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) LOW_THRESH_0, /* LOWER threshold values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) LOW_THRESH_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) LOW_THRESH_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) LOW_THRESH_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) LOW_THRESH_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) LOW_THRESH_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) LOW_THRESH_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) LOW_THRESH_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) LOW_THRESH_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) LOW_THRESH_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) LOW_THRESH_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) LOW_THRESH_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) LOW_THRESH_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) LOW_THRESH_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) LOW_THRESH_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) LOW_THRESH_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) UPPER_STATUS_0, /* UPPER threshold violated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) UPPER_STATUS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) UPPER_STATUS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) UPPER_STATUS_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) UPPER_STATUS_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) UPPER_STATUS_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) UPPER_STATUS_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) UPPER_STATUS_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) UPPER_STATUS_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) UPPER_STATUS_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) UPPER_STATUS_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) UPPER_STATUS_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) UPPER_STATUS_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) UPPER_STATUS_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) UPPER_STATUS_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) UPPER_STATUS_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) UP_INT_STATUS_0, /* UPPER interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) UP_INT_STATUS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) UP_INT_STATUS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) UP_INT_STATUS_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) UP_INT_STATUS_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) UP_INT_STATUS_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) UP_INT_STATUS_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) UP_INT_STATUS_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) UP_INT_STATUS_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) UP_INT_STATUS_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) UP_INT_STATUS_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) UP_INT_STATUS_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) UP_INT_STATUS_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) UP_INT_STATUS_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) UP_INT_STATUS_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) UP_INT_STATUS_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) UP_INT_CLEAR_0, /* UPPER interrupt clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) UP_INT_CLEAR_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) UP_INT_CLEAR_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) UP_INT_CLEAR_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) UP_INT_CLEAR_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) UP_INT_CLEAR_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) UP_INT_CLEAR_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) UP_INT_CLEAR_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) UP_INT_CLEAR_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) UP_INT_CLEAR_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) UP_INT_CLEAR_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) UP_INT_CLEAR_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) UP_INT_CLEAR_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) UP_INT_CLEAR_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) UP_INT_CLEAR_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) UP_INT_CLEAR_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) UP_INT_MASK_0, /* UPPER interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) UP_INT_MASK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) UP_INT_MASK_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) UP_INT_MASK_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) UP_INT_MASK_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) UP_INT_MASK_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) UP_INT_MASK_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) UP_INT_MASK_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) UP_INT_MASK_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) UP_INT_MASK_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) UP_INT_MASK_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) UP_INT_MASK_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) UP_INT_MASK_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) UP_INT_MASK_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) UP_INT_MASK_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) UP_INT_MASK_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) UP_THRESH_0, /* UPPER threshold values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) UP_THRESH_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) UP_THRESH_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) UP_THRESH_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) UP_THRESH_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) UP_THRESH_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) UP_THRESH_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) UP_THRESH_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) UP_THRESH_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) UP_THRESH_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) UP_THRESH_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) UP_THRESH_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) UP_THRESH_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) UP_THRESH_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) UP_THRESH_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) UP_THRESH_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) CRITICAL_STATUS_0, /* CRITICAL threshold violated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) CRITICAL_STATUS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) CRITICAL_STATUS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) CRITICAL_STATUS_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) CRITICAL_STATUS_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) CRITICAL_STATUS_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) CRITICAL_STATUS_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) CRITICAL_STATUS_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) CRITICAL_STATUS_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) CRITICAL_STATUS_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) CRITICAL_STATUS_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) CRITICAL_STATUS_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) CRITICAL_STATUS_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) CRITICAL_STATUS_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) CRITICAL_STATUS_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) CRITICAL_STATUS_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) CRIT_INT_STATUS_0, /* CRITICAL interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) CRIT_INT_STATUS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) CRIT_INT_STATUS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) CRIT_INT_STATUS_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) CRIT_INT_STATUS_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) CRIT_INT_STATUS_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) CRIT_INT_STATUS_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) CRIT_INT_STATUS_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) CRIT_INT_STATUS_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) CRIT_INT_STATUS_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) CRIT_INT_STATUS_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) CRIT_INT_STATUS_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) CRIT_INT_STATUS_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) CRIT_INT_STATUS_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) CRIT_INT_STATUS_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) CRIT_INT_STATUS_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) CRIT_INT_CLEAR_0, /* CRITICAL interrupt clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) CRIT_INT_CLEAR_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) CRIT_INT_CLEAR_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) CRIT_INT_CLEAR_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) CRIT_INT_CLEAR_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) CRIT_INT_CLEAR_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) CRIT_INT_CLEAR_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) CRIT_INT_CLEAR_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) CRIT_INT_CLEAR_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) CRIT_INT_CLEAR_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) CRIT_INT_CLEAR_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) CRIT_INT_CLEAR_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) CRIT_INT_CLEAR_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) CRIT_INT_CLEAR_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) CRIT_INT_CLEAR_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) CRIT_INT_CLEAR_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) CRIT_INT_MASK_0, /* CRITICAL interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) CRIT_INT_MASK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) CRIT_INT_MASK_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) CRIT_INT_MASK_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) CRIT_INT_MASK_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) CRIT_INT_MASK_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) CRIT_INT_MASK_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) CRIT_INT_MASK_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) CRIT_INT_MASK_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) CRIT_INT_MASK_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) CRIT_INT_MASK_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) CRIT_INT_MASK_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) CRIT_INT_MASK_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) CRIT_INT_MASK_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) CRIT_INT_MASK_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) CRIT_INT_MASK_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) CRIT_THRESH_0, /* CRITICAL threshold values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) CRIT_THRESH_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) CRIT_THRESH_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) CRIT_THRESH_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) CRIT_THRESH_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) CRIT_THRESH_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) CRIT_THRESH_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) CRIT_THRESH_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) CRIT_THRESH_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) CRIT_THRESH_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) CRIT_THRESH_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) CRIT_THRESH_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) CRIT_THRESH_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) CRIT_THRESH_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) CRIT_THRESH_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) CRIT_THRESH_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* WATCHDOG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) WDOG_BARK_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) WDOG_BARK_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) WDOG_BARK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) WDOG_BARK_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* CYCLE COMPLETION MONITOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) CC_MON_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) CC_MON_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) CC_MON_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MIN_STATUS_0, /* MIN threshold violated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MIN_STATUS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MIN_STATUS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MIN_STATUS_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MIN_STATUS_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MIN_STATUS_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MIN_STATUS_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MIN_STATUS_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) MIN_STATUS_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MIN_STATUS_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MIN_STATUS_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MIN_STATUS_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MIN_STATUS_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MIN_STATUS_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MIN_STATUS_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) MIN_STATUS_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) MAX_STATUS_0, /* MAX threshold violated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MAX_STATUS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MAX_STATUS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MAX_STATUS_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MAX_STATUS_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MAX_STATUS_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MAX_STATUS_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MAX_STATUS_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) MAX_STATUS_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MAX_STATUS_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MAX_STATUS_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MAX_STATUS_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MAX_STATUS_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MAX_STATUS_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MAX_STATUS_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) MAX_STATUS_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Keep last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) MAX_REGFIELDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * struct tsens_features - Features supported by the IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * @ver_major: Major number of IP version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * @crit_int: does the IP support critical interrupts?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * @adc: do the sensors only output adc code (instead of temperature)?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * @srot_split: does the IP neatly splits the register space into SROT and TM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * with SROT only being available to secure boot firmware?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * @has_watchdog: does this IP support watchdog functionality?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * @max_sensors: maximum sensors supported by this version of the IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct tsens_features {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned int ver_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) unsigned int crit_int:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) unsigned int adc:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) unsigned int srot_split:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) unsigned int has_watchdog:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned int max_sensors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * struct tsens_plat_data - tsens compile-time platform data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * @num_sensors: Number of sensors supported by platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * @ops: operations the tsens instance supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * @hw_ids: Subset of sensors ids supported by platform, if not the first n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * @feat: features of the IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * @fields: bitfield locations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct tsens_plat_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) const u32 num_sensors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) const struct tsens_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) unsigned int *hw_ids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct tsens_features *feat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) const struct reg_field *fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * struct tsens_context - Registers to be saved/restored across a context loss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * @threshold: Threshold register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * @control: Control register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct tsens_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * struct tsens_priv - private data for each instance of the tsens IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * @dev: pointer to struct device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * @num_sensors: number of sensors enabled on this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * @tm_map: pointer to TM register address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * @srot_map: pointer to SROT register address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * @tm_offset: deal with old device trees that don't address TM and SROT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * address space separately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * @ul_lock: lock while processing upper/lower threshold interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * @crit_lock: lock while processing critical threshold interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * @rf: array of regmap_fields used to store value of the field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * @ctx: registers to be saved and restored during suspend/resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * @feat: features of the IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * @fields: bitfield locations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * @ops: pointer to list of callbacks supported by this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * @debug_root: pointer to debugfs dentry for all tsens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * @debug: pointer to debugfs dentry for tsens controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * @sensor: list of sensors attached to this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct tsens_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u32 num_sensors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct regmap *tm_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct regmap *srot_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 tm_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* lock for upper/lower threshold interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) spinlock_t ul_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct regmap_field *rf[MAX_REGFIELDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct tsens_context ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct tsens_features *feat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) const struct reg_field *fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) const struct tsens_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct dentry *debug_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct dentry *debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct tsens_sensor sensor[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) char *qfprom_read(struct device *dev, const char *cname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int init_common(struct tsens_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int get_temp_common(const struct tsens_sensor *s, int *temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* TSENS target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) extern struct tsens_plat_data data_8960;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* TSENS v0.1 targets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) extern struct tsens_plat_data data_8916, data_8939, data_8974;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* TSENS v1 targets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) extern struct tsens_plat_data data_tsens_v1, data_8976;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* TSENS v2 targets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) extern struct tsens_plat_data data_8996, data_tsens_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #endif /* __QCOM_TSENS_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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