^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2018, Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "tsens.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* ----- SROT ------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SROT_HW_VER_OFF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SROT_CTRL_OFF 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* ----- TM ------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TM_INT_EN_OFF 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TM_UPPER_LOWER_INT_STATUS_OFF 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TM_UPPER_LOWER_INT_CLEAR_OFF 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TM_UPPER_LOWER_INT_MASK_OFF 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TM_CRITICAL_INT_STATUS_OFF 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TM_CRITICAL_INT_CLEAR_OFF 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TM_CRITICAL_INT_MASK_OFF 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TM_Sn_UPPER_LOWER_THRESHOLD_OFF 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TM_Sn_CRITICAL_THRESHOLD_OFF 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TM_Sn_STATUS_OFF 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TM_TRDY_OFF 0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TM_WDOG_LOG_OFF 0x013c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* v2.x: 8996, 8998, sdm845 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static struct tsens_features tsens_v2_feat = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .ver_major = VER_2_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .crit_int = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .adc = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .srot_split = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .max_sensors = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* ----- SROT ------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) [VER_MAJOR] = REG_FIELD(SROT_HW_VER_OFF, 28, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) [VER_MINOR] = REG_FIELD(SROT_HW_VER_OFF, 16, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) [VER_STEP] = REG_FIELD(SROT_HW_VER_OFF, 0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* CTRL_OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) [TSENS_EN] = REG_FIELD(SROT_CTRL_OFF, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) [TSENS_SW_RST] = REG_FIELD(SROT_CTRL_OFF, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* ----- TM ------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* INTERRUPT ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* v2 has separate enables for UPPER/LOWER/CRITICAL interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* TEMPERATURE THRESHOLDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) REG_FIELD_FOR_EACH_SENSOR16(LOW_THRESH, TM_Sn_UPPER_LOWER_THRESHOLD_OFF, 0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) REG_FIELD_FOR_EACH_SENSOR16(UP_THRESH, TM_Sn_UPPER_LOWER_THRESHOLD_OFF, 12, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) REG_FIELD_FOR_EACH_SENSOR16(CRIT_THRESH, TM_Sn_CRITICAL_THRESHOLD_OFF, 0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* INTERRUPTS [CLEAR/STATUS/MASK] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) REG_FIELD_SPLIT_BITS_0_15(LOW_INT_STATUS, TM_UPPER_LOWER_INT_STATUS_OFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) REG_FIELD_SPLIT_BITS_0_15(LOW_INT_CLEAR, TM_UPPER_LOWER_INT_CLEAR_OFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) REG_FIELD_SPLIT_BITS_0_15(LOW_INT_MASK, TM_UPPER_LOWER_INT_MASK_OFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) REG_FIELD_SPLIT_BITS_16_31(UP_INT_STATUS, TM_UPPER_LOWER_INT_STATUS_OFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) REG_FIELD_SPLIT_BITS_16_31(UP_INT_CLEAR, TM_UPPER_LOWER_INT_CLEAR_OFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) REG_FIELD_SPLIT_BITS_16_31(UP_INT_MASK, TM_UPPER_LOWER_INT_MASK_OFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) REG_FIELD_SPLIT_BITS_0_15(CRIT_INT_STATUS, TM_CRITICAL_INT_STATUS_OFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) REG_FIELD_SPLIT_BITS_0_15(CRIT_INT_CLEAR, TM_CRITICAL_INT_CLEAR_OFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) REG_FIELD_SPLIT_BITS_0_15(CRIT_INT_MASK, TM_CRITICAL_INT_MASK_OFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* WATCHDOG on v2.3 or later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) [WDOG_BARK_STATUS] = REG_FIELD(TM_CRITICAL_INT_STATUS_OFF, 31, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [WDOG_BARK_CLEAR] = REG_FIELD(TM_CRITICAL_INT_CLEAR_OFF, 31, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) [WDOG_BARK_MASK] = REG_FIELD(TM_CRITICAL_INT_MASK_OFF, 31, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) [CC_MON_STATUS] = REG_FIELD(TM_CRITICAL_INT_STATUS_OFF, 30, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [CC_MON_CLEAR] = REG_FIELD(TM_CRITICAL_INT_CLEAR_OFF, 30, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) [CC_MON_MASK] = REG_FIELD(TM_CRITICAL_INT_MASK_OFF, 30, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) [WDOG_BARK_COUNT] = REG_FIELD(TM_WDOG_LOG_OFF, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Sn_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) REG_FIELD_FOR_EACH_SENSOR16(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) REG_FIELD_FOR_EACH_SENSOR16(VALID, TM_Sn_STATUS_OFF, 21, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* xxx_STATUS bits: 1 == threshold violated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) REG_FIELD_FOR_EACH_SENSOR16(MIN_STATUS, TM_Sn_STATUS_OFF, 16, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) REG_FIELD_FOR_EACH_SENSOR16(LOWER_STATUS, TM_Sn_STATUS_OFF, 17, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) REG_FIELD_FOR_EACH_SENSOR16(UPPER_STATUS, TM_Sn_STATUS_OFF, 18, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) REG_FIELD_FOR_EACH_SENSOR16(CRITICAL_STATUS, TM_Sn_STATUS_OFF, 19, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) REG_FIELD_FOR_EACH_SENSOR16(MAX_STATUS, TM_Sn_STATUS_OFF, 20, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* TRDY: 1=ready, 0=in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static const struct tsens_ops ops_generic_v2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .init = init_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .get_temp = get_temp_tsens_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct tsens_plat_data data_tsens_v2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .ops = &ops_generic_v2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .feat = &tsens_v2_feat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .fields = tsens_v2_regfields,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Kept around for backward compatibility with old msm8996.dtsi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct tsens_plat_data data_8996 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .num_sensors = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .ops = &ops_generic_v2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .feat = &tsens_v2_feat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .fields = tsens_v2_regfields,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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