^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019, Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "tsens.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* ----- SROT ------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SROT_HW_VER_OFF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SROT_CTRL_OFF 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* ----- TM ------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TM_INT_EN_OFF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TM_Sn_STATUS_OFF 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TM_TRDY_OFF 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TM_HIGH_LOW_INT_STATUS_OFF 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TM_HIGH_LOW_Sn_INT_THRESHOLD_OFF 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* eeprom layout data for msm8956/76 (v1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MSM8976_BASE0_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MSM8976_BASE1_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MSM8976_BASE1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MSM8976_S0_P1_MASK 0x3f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MSM8976_S1_P1_MASK 0x3f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MSM8976_S2_P1_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MSM8976_S3_P1_MASK 0x3f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MSM8976_S4_P1_MASK 0x3f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MSM8976_S5_P1_MASK 0x3f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MSM8976_S6_P1_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MSM8976_S7_P1_MASK 0x3f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MSM8976_S8_P1_MASK 0x1f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MSM8976_S9_P1_MASK 0x1f8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MSM8976_S10_P1_MASK 0xf8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MSM8976_S10_P1_MASK_1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MSM8976_S0_P2_MASK 0xfc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MSM8976_S1_P2_MASK 0xfc000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MSM8976_S2_P2_MASK 0xfc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MSM8976_S3_P2_MASK 0xfc0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MSM8976_S4_P2_MASK 0xfc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MSM8976_S5_P2_MASK 0xfc000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MSM8976_S6_P2_MASK 0xfc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MSM8976_S7_P2_MASK 0xfc0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MSM8976_S8_P2_MASK 0x7e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MSM8976_S9_P2_MASK 0x7e00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MSM8976_S10_P2_MASK 0x7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MSM8976_S0_P1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MSM8976_S1_P1_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MSM8976_S2_P1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MSM8976_S3_P1_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MSM8976_S4_P1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MSM8976_S5_P1_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MSM8976_S6_P1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MSM8976_S7_P1_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MSM8976_S8_P1_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MSM8976_S9_P1_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MSM8976_S10_P1_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MSM8976_S10_P1_SHIFT_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MSM8976_S0_P2_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MSM8976_S1_P2_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MSM8976_S2_P2_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MSM8976_S3_P2_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MSM8976_S4_P2_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MSM8976_S5_P2_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MSM8976_S6_P2_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MSM8976_S7_P2_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MSM8976_S8_P2_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MSM8976_S9_P2_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MSM8976_S10_P2_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MSM8976_CAL_SEL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MSM8976_CAL_DEGC_PT1 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MSM8976_CAL_DEGC_PT2 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MSM8976_SLOPE_FACTOR 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MSM8976_SLOPE_DEFAULT 3200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* eeprom layout data for qcs404/405 (v1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BASE0_MASK 0x000007f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define BASE1_MASK 0x0007f800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define BASE0_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define BASE1_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define S0_P1_MASK 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define S1_P1_MASK 0x0003f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define S2_P1_MASK 0x3f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define S3_P1_MASK 0x000003f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define S4_P1_MASK 0x003f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define S5_P1_MASK 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define S6_P1_MASK 0x0003f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define S7_P1_MASK 0x3f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define S8_P1_MASK 0x000003f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define S9_P1_MASK 0x003f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define S0_P2_MASK 0x00000fc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define S1_P2_MASK 0x00fc0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define S2_P2_MASK_1_0 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define S2_P2_MASK_5_2 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define S3_P2_MASK 0x0000fc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define S4_P2_MASK 0x0fc00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define S5_P2_MASK 0x00000fc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define S6_P2_MASK 0x00fc0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define S7_P2_MASK_1_0 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define S7_P2_MASK_5_2 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define S8_P2_MASK 0x0000fc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define S9_P2_MASK 0x0fc00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define S0_P1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define S0_P2_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define S1_P1_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define S1_P2_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define S2_P1_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define S2_P2_SHIFT_1_0 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define S2_P2_SHIFT_5_2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define S3_P1_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define S3_P2_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define S4_P1_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define S4_P2_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define S5_P1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define S5_P2_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define S6_P1_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define S6_P2_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define S7_P1_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define S7_P2_SHIFT_1_0 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define S7_P2_SHIFT_5_2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define S8_P1_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define S8_P2_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define S9_P1_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define S9_P2_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CAL_SEL_MASK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CAL_SEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void compute_intercept_slope_8976(struct tsens_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 *p1, u32 *p2, u32 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) priv->sensor[0].slope = 3313;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) priv->sensor[1].slope = 3275;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) priv->sensor[2].slope = 3320;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) priv->sensor[3].slope = 3246;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) priv->sensor[4].slope = 3279;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) priv->sensor[5].slope = 3257;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) priv->sensor[6].slope = 3234;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) priv->sensor[7].slope = 3269;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) priv->sensor[8].slope = 3255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) priv->sensor[9].slope = 3239;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) priv->sensor[10].slope = 3286;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) for (i = 0; i < priv->num_sensors; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) priv->sensor[i].offset = (p1[i] * MSM8976_SLOPE_FACTOR) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) (MSM8976_CAL_DEGC_PT1 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) priv->sensor[i].slope);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int calibrate_v1(struct tsens_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 base0 = 0, base1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 p1[10], p2[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 mode = 0, lsb = 0, msb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 *qfprom_cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (IS_ERR(qfprom_cdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return PTR_ERR(qfprom_cdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mode = (qfprom_cdata[4] & CAL_SEL_MASK) >> CAL_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dev_dbg(priv->dev, "calibration mode is %d\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) case TWO_PT_CALIB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) base1 = (qfprom_cdata[4] & BASE1_MASK) >> BASE1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) p2[0] = (qfprom_cdata[0] & S0_P2_MASK) >> S0_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) p2[1] = (qfprom_cdata[0] & S1_P2_MASK) >> S1_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* This value is split over two registers, 2 bits and 4 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) lsb = (qfprom_cdata[0] & S2_P2_MASK_1_0) >> S2_P2_SHIFT_1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) msb = (qfprom_cdata[1] & S2_P2_MASK_5_2) >> S2_P2_SHIFT_5_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) p2[2] = msb << 2 | lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) p2[3] = (qfprom_cdata[1] & S3_P2_MASK) >> S3_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) p2[4] = (qfprom_cdata[1] & S4_P2_MASK) >> S4_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) p2[5] = (qfprom_cdata[2] & S5_P2_MASK) >> S5_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) p2[6] = (qfprom_cdata[2] & S6_P2_MASK) >> S6_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* This value is split over two registers, 2 bits and 4 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) lsb = (qfprom_cdata[2] & S7_P2_MASK_1_0) >> S7_P2_SHIFT_1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) msb = (qfprom_cdata[3] & S7_P2_MASK_5_2) >> S7_P2_SHIFT_5_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) p2[7] = msb << 2 | lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) p2[8] = (qfprom_cdata[3] & S8_P2_MASK) >> S8_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) p2[9] = (qfprom_cdata[3] & S9_P2_MASK) >> S9_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) for (i = 0; i < priv->num_sensors; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) p2[i] = ((base1 + p2[i]) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case ONE_PT_CALIB2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) base0 = (qfprom_cdata[4] & BASE0_MASK) >> BASE0_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) p1[0] = (qfprom_cdata[0] & S0_P1_MASK) >> S0_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) p1[1] = (qfprom_cdata[0] & S1_P1_MASK) >> S1_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) p1[2] = (qfprom_cdata[0] & S2_P1_MASK) >> S2_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) p1[3] = (qfprom_cdata[1] & S3_P1_MASK) >> S3_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) p1[4] = (qfprom_cdata[1] & S4_P1_MASK) >> S4_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) p1[5] = (qfprom_cdata[2] & S5_P1_MASK) >> S5_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) p1[6] = (qfprom_cdata[2] & S6_P1_MASK) >> S6_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) p1[7] = (qfprom_cdata[2] & S7_P1_MASK) >> S7_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) p1[8] = (qfprom_cdata[3] & S8_P1_MASK) >> S8_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) p1[9] = (qfprom_cdata[3] & S9_P1_MASK) >> S9_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) for (i = 0; i < priv->num_sensors; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) p1[i] = (((base0) + p1[i]) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) for (i = 0; i < priv->num_sensors; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) p1[i] = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) p2[i] = 780;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) compute_intercept_slope(priv, p1, p2, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) kfree(qfprom_cdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int calibrate_8976(struct tsens_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int base0 = 0, base1 = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 p1[11], p2[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int mode = 0, tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 *qfprom_cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (IS_ERR(qfprom_cdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return PTR_ERR(qfprom_cdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) mode = (qfprom_cdata[4] & MSM8976_CAL_SEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_dbg(priv->dev, "calibration mode is %d\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case TWO_PT_CALIB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) base1 = (qfprom_cdata[2] & MSM8976_BASE1_MASK) >> MSM8976_BASE1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) p2[0] = (qfprom_cdata[0] & MSM8976_S0_P2_MASK) >> MSM8976_S0_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) p2[1] = (qfprom_cdata[0] & MSM8976_S1_P2_MASK) >> MSM8976_S1_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) p2[2] = (qfprom_cdata[1] & MSM8976_S2_P2_MASK) >> MSM8976_S2_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) p2[3] = (qfprom_cdata[1] & MSM8976_S3_P2_MASK) >> MSM8976_S3_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) p2[4] = (qfprom_cdata[2] & MSM8976_S4_P2_MASK) >> MSM8976_S4_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) p2[5] = (qfprom_cdata[2] & MSM8976_S5_P2_MASK) >> MSM8976_S5_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) p2[6] = (qfprom_cdata[3] & MSM8976_S6_P2_MASK) >> MSM8976_S6_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) p2[7] = (qfprom_cdata[3] & MSM8976_S7_P2_MASK) >> MSM8976_S7_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) p2[8] = (qfprom_cdata[4] & MSM8976_S8_P2_MASK) >> MSM8976_S8_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) p2[9] = (qfprom_cdata[4] & MSM8976_S9_P2_MASK) >> MSM8976_S9_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) p2[10] = (qfprom_cdata[5] & MSM8976_S10_P2_MASK) >> MSM8976_S10_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) for (i = 0; i < priv->num_sensors; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) p2[i] = ((base1 + p2[i]) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case ONE_PT_CALIB2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) base0 = qfprom_cdata[0] & MSM8976_BASE0_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) p1[0] = (qfprom_cdata[0] & MSM8976_S0_P1_MASK) >> MSM8976_S0_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) p1[1] = (qfprom_cdata[0] & MSM8976_S1_P1_MASK) >> MSM8976_S1_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) p1[2] = (qfprom_cdata[1] & MSM8976_S2_P1_MASK) >> MSM8976_S2_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) p1[3] = (qfprom_cdata[1] & MSM8976_S3_P1_MASK) >> MSM8976_S3_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) p1[4] = (qfprom_cdata[2] & MSM8976_S4_P1_MASK) >> MSM8976_S4_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) p1[5] = (qfprom_cdata[2] & MSM8976_S5_P1_MASK) >> MSM8976_S5_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) p1[6] = (qfprom_cdata[3] & MSM8976_S6_P1_MASK) >> MSM8976_S6_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) p1[7] = (qfprom_cdata[3] & MSM8976_S7_P1_MASK) >> MSM8976_S7_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) p1[8] = (qfprom_cdata[4] & MSM8976_S8_P1_MASK) >> MSM8976_S8_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) p1[9] = (qfprom_cdata[4] & MSM8976_S9_P1_MASK) >> MSM8976_S9_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) p1[10] = (qfprom_cdata[4] & MSM8976_S10_P1_MASK) >> MSM8976_S10_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) tmp = (qfprom_cdata[5] & MSM8976_S10_P1_MASK_1) << MSM8976_S10_P1_SHIFT_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) p1[10] |= tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) for (i = 0; i < priv->num_sensors; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) p1[i] = (((base0) + p1[i]) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) for (i = 0; i < priv->num_sensors; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) p1[i] = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) p2[i] = 780;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) compute_intercept_slope_8976(priv, p1, p2, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) kfree(qfprom_cdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* v1.x: msm8956,8976,qcs404,405 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static struct tsens_features tsens_v1_feat = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .ver_major = VER_1_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .crit_int = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .adc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .srot_split = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .max_sensors = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* ----- SROT ------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) [VER_MAJOR] = REG_FIELD(SROT_HW_VER_OFF, 28, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) [VER_MINOR] = REG_FIELD(SROT_HW_VER_OFF, 16, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) [VER_STEP] = REG_FIELD(SROT_HW_VER_OFF, 0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* CTRL_OFFSET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) [TSENS_EN] = REG_FIELD(SROT_CTRL_OFF, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) [TSENS_SW_RST] = REG_FIELD(SROT_CTRL_OFF, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) [SENSOR_EN] = REG_FIELD(SROT_CTRL_OFF, 3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* ----- TM ------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* INTERRUPT ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* UPPER/LOWER TEMPERATURE THRESHOLDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) REG_FIELD_FOR_EACH_SENSOR11(LOW_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) REG_FIELD_FOR_EACH_SENSOR11(UP_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 10, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* UPPER/LOWER INTERRUPTS [CLEAR/STATUS] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) REG_FIELD_FOR_EACH_SENSOR11(LOW_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 20, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) REG_FIELD_FOR_EACH_SENSOR11(UP_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 21, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) [LOW_INT_STATUS_0] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) [LOW_INT_STATUS_1] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) [LOW_INT_STATUS_2] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) [LOW_INT_STATUS_3] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) [LOW_INT_STATUS_4] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) [LOW_INT_STATUS_5] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) [LOW_INT_STATUS_6] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) [LOW_INT_STATUS_7] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 7, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) [UP_INT_STATUS_0] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) [UP_INT_STATUS_1] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 9, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) [UP_INT_STATUS_2] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 10, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) [UP_INT_STATUS_3] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 11, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) [UP_INT_STATUS_4] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 12, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) [UP_INT_STATUS_5] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 13, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) [UP_INT_STATUS_6] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 14, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) [UP_INT_STATUS_7] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 15, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* NO CRITICAL INTERRUPT SUPPORT on v1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Sn_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) REG_FIELD_FOR_EACH_SENSOR11(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) REG_FIELD_FOR_EACH_SENSOR11(VALID, TM_Sn_STATUS_OFF, 14, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* xxx_STATUS bits: 1 == threshold violated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) REG_FIELD_FOR_EACH_SENSOR11(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) REG_FIELD_FOR_EACH_SENSOR11(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) REG_FIELD_FOR_EACH_SENSOR11(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* No CRITICAL field on v1.x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) REG_FIELD_FOR_EACH_SENSOR11(MAX_STATUS, TM_Sn_STATUS_OFF, 13, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* TRDY: 1=ready, 0=in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct tsens_ops ops_generic_v1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .init = init_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .calibrate = calibrate_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .get_temp = get_temp_tsens_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct tsens_plat_data data_tsens_v1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .ops = &ops_generic_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .feat = &tsens_v1_feat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .fields = tsens_v1_regfields,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const struct tsens_ops ops_8976 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .init = init_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .calibrate = calibrate_8976,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .get_temp = get_temp_tsens_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Valid for both MSM8956 and MSM8976. Sensor ID 3 is unused. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct tsens_plat_data data_8976 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .num_sensors = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .ops = &ops_8976,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .hw_ids = (unsigned int[]){0, 1, 2, 4, 5, 6, 7, 8, 9, 10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .feat = &tsens_v1_feat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .fields = tsens_v1_regfields,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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