^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/iio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "../thermal_core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define QPNP_TM_REG_TYPE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define QPNP_TM_REG_SUBTYPE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define QPNP_TM_REG_STATUS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define QPNP_TM_REG_ALARM_CTRL 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define QPNP_TM_TYPE 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define QPNP_TM_SUBTYPE_GEN1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define QPNP_TM_SUBTYPE_GEN2 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define STATUS_GEN1_STAGE_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define STATUS_GEN2_STATE_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define STATUS_GEN2_STATE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SHUTDOWN_CTRL1_RATE_25HZ BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ALARM_CTRL_FORCE_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Trip point values based on threshold control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * 0 = {105 C, 125 C, 145 C}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * 1 = {110 C, 130 C, 150 C}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * 2 = {115 C, 135 C, 155 C}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * 3 = {120 C, 140 C, 160 C}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEMP_STAGE_STEP 20000 /* Stage step: 20.000 C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TEMP_STAGE_HYSTERESIS 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TEMP_THRESH_MIN 105000 /* Threshold Min: 105 C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEMP_THRESH_STEP 5000 /* Threshold step: 5 C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define THRESH_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define THRESH_MAX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Stage 2 Threshold Min: 125 C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define STAGE2_THRESHOLD_MIN 125000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Stage 2 Threshold Max: 140 C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define STAGE2_THRESHOLD_MAX 140000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DEFAULT_TEMP 37000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct qpnp_tm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct thermal_zone_device *tz_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int subtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) long temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int stage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int prev_stage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* protects .thresh, .stage and chip registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bool initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct iio_channel *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* This array maps from GEN2 alarm state to GEN1 alarm stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const unsigned int alarm_state_map[8] = {0, 1, 1, 2, 2, 3, 3, 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int qpnp_tm_read(struct qpnp_tm_chip *chip, u16 addr, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ret = regmap_read(chip->map, chip->base + addr, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int qpnp_tm_write(struct qpnp_tm_chip *chip, u16 addr, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return regmap_write(chip->map, chip->base + addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * qpnp_tm_get_temp_stage() - return over-temperature stage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @chip: Pointer to the qpnp_tm chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Return: stage (GEN1) or state (GEN2) on success, or errno on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (chip->subtype == QPNP_TM_SUBTYPE_GEN1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ret = reg & STATUS_GEN1_STAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ret = (reg & STATUS_GEN2_STATE_MASK) >> STATUS_GEN2_STATE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * This function updates the internal temp value based on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * current thermal stage and threshold as well as the previous stage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int stage, stage_new, stage_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) WARN_ON(!mutex_is_locked(&chip->lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ret = qpnp_tm_get_temp_stage(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) stage = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (chip->subtype == QPNP_TM_SUBTYPE_GEN1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) stage_new = stage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) stage_old = chip->stage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) stage_new = alarm_state_map[stage];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) stage_old = alarm_state_map[chip->stage];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (stage_new > stage_old) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* increasing stage, use lower bound */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) chip->temp = (stage_new - 1) * TEMP_STAGE_STEP +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) chip->thresh * TEMP_THRESH_STEP +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) TEMP_STAGE_HYSTERESIS + TEMP_THRESH_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) } else if (stage_new < stage_old) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* decreasing stage, use upper bound */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) chip->temp = stage_new * TEMP_STAGE_STEP +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) chip->thresh * TEMP_THRESH_STEP -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) TEMP_STAGE_HYSTERESIS + TEMP_THRESH_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) chip->stage = stage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int qpnp_tm_get_temp(void *data, int *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct qpnp_tm_chip *chip = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int ret, mili_celsius;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (!chip->initialized) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *temp = DEFAULT_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (!chip->adc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = qpnp_tm_update_temp_no_adc(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret = iio_read_channel_processed(chip->adc, &mili_celsius);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) chip->temp = mili_celsius;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *temp = chip->temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) bool disable_s2_shutdown = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) WARN_ON(!mutex_is_locked(&chip->lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Default: S2 and S3 shutdown enabled, thresholds at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * 105C/125C/145C, monitoring at 25Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) reg = SHUTDOWN_CTRL1_RATE_25HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (temp == THERMAL_TEMP_INVALID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) temp < STAGE2_THRESHOLD_MIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) chip->thresh = THRESH_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) goto skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (temp <= STAGE2_THRESHOLD_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) chip->thresh = THRESH_MAX -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ((STAGE2_THRESHOLD_MAX - temp) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) TEMP_THRESH_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) disable_s2_shutdown = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) chip->thresh = THRESH_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (chip->adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) disable_s2_shutdown = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_warn(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "No ADC is configured and critical temperature is above the maximum stage 2 threshold of 140 C! Configuring stage 2 shutdown at 140 C.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) skip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) reg |= chip->thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (disable_s2_shutdown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) reg |= SHUTDOWN_CTRL1_OVERRIDE_S2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int qpnp_tm_set_trip_temp(void *data, int trip, int temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct qpnp_tm_chip *chip = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) const struct thermal_trip *trip_points;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) trip_points = of_thermal_get_trip_points(chip->tz_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (!trip_points)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (trip_points[trip].type != THERMAL_TRIP_CRITICAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ret = qpnp_tm_update_critical_trip_temp(chip, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const struct thermal_zone_of_device_ops qpnp_tm_sensor_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .get_temp = qpnp_tm_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .set_trip_temp = qpnp_tm_set_trip_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static irqreturn_t qpnp_tm_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct qpnp_tm_chip *chip = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) thermal_zone_device_update(chip->tz_dev, THERMAL_EVENT_UNSPECIFIED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int qpnp_tm_get_critical_trip_temp(struct qpnp_tm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int ntrips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) const struct thermal_trip *trips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ntrips = of_thermal_get_ntrips(chip->tz_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (ntrips <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return THERMAL_TEMP_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) trips = of_thermal_get_trip_points(chip->tz_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (!trips)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return THERMAL_TEMP_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) for (i = 0; i < ntrips; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (of_thermal_is_trip_valid(chip->tz_dev, i) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) trips[i].type == THERMAL_TRIP_CRITICAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return trips[i].temperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return THERMAL_TEMP_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * This function initializes the internal temp value based on only the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * current thermal stage and threshold. Setup threshold control and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * disable shutdown override.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int qpnp_tm_init(struct qpnp_tm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned int stage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u8 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int crit_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = qpnp_tm_read(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) chip->thresh = reg & SHUTDOWN_CTRL1_THRESHOLD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) chip->temp = DEFAULT_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = qpnp_tm_get_temp_stage(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) chip->stage = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) stage = chip->subtype == QPNP_TM_SUBTYPE_GEN1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ? chip->stage : alarm_state_map[chip->stage];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (stage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) chip->temp = chip->thresh * TEMP_THRESH_STEP +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) (stage - 1) * TEMP_STAGE_STEP +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) TEMP_THRESH_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) crit_temp = qpnp_tm_get_critical_trip_temp(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = qpnp_tm_update_critical_trip_temp(chip, crit_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Enable the thermal alarm PMIC module in always-on mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) reg = ALARM_CTRL_FORCE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ret = qpnp_tm_write(chip, QPNP_TM_REG_ALARM_CTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) chip->initialized = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int qpnp_tm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct qpnp_tm_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 type, subtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_set_drvdata(&pdev->dev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) chip->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mutex_init(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) chip->map = dev_get_regmap(pdev->dev.parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (!chip->map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ret = of_property_read_u32(node, "reg", &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* ADC based measurements are optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) chip->adc = devm_iio_channel_get(&pdev->dev, "thermal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (IS_ERR(chip->adc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ret = PTR_ERR(chip->adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) chip->adc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) chip->base = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = qpnp_tm_read(chip, QPNP_TM_REG_TYPE, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_err(&pdev->dev, "could not read type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ret = qpnp_tm_read(chip, QPNP_TM_REG_SUBTYPE, &subtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_err(&pdev->dev, "could not read subtype\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) && subtype != QPNP_TM_SUBTYPE_GEN2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) type, subtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) chip->subtype = subtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * Register the sensor before initializing the hardware to be able to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * read the trip points. get_temp() returns the default temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * before the hardware initialization is completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) chip->tz_dev = devm_thermal_zone_of_sensor_register(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) &pdev->dev, 0, chip, &qpnp_tm_sensor_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (IS_ERR(chip->tz_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_err(&pdev->dev, "failed to register sensor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return PTR_ERR(chip->tz_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ret = qpnp_tm_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dev_err(&pdev->dev, "init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, qpnp_tm_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) IRQF_ONESHOT, node->name, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) thermal_zone_device_update(chip->tz_dev, THERMAL_EVENT_UNSPECIFIED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const struct of_device_id qpnp_tm_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) { .compatible = "qcom,spmi-temp-alarm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MODULE_DEVICE_TABLE(of, qpnp_tm_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static struct platform_driver qpnp_tm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .name = "spmi-temp-alarm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .of_match_table = qpnp_tm_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .probe = qpnp_tm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) module_platform_driver(qpnp_tm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MODULE_ALIAS("platform:spmi-temp-alarm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MODULE_DESCRIPTION("QPNP PMIC Temperature Alarm driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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