^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Hanyi Wu <hanyi.wu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Sascha Hauer <s.hauer@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Dawei Chien <dawei.chien@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Louis Yu <louis.yu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* AUXADC Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AUXADC_CON1_SET_V 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AUXADC_CON1_CLR_V 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AUXADC_CON2_V 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AUXADC_DATA(channel) (0x14 + (channel) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define APMIXED_SYS_TS_CON1 0x604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Thermal Controller Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEMP_MONCTL0 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEMP_MONCTL1 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEMP_MONCTL2 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEMP_MONIDET0 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEMP_MONIDET1 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEMP_MSRCTL0 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEMP_MSRCTL1 0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEMP_AHBPOLL 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEMP_AHBTO 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEMP_ADCPNP0 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TEMP_ADCPNP1 0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEMP_ADCPNP2 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TEMP_ADCPNP3 0x0b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TEMP_ADCMUX 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TEMP_ADCEN 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TEMP_PNPMUXADDR 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEMP_ADCMUXADDR 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TEMP_ADCENADDR 0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TEMP_ADCVALIDADDR 0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TEMP_ADCVOLTADDR 0x07c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TEMP_RDCTRL 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TEMP_ADCVALIDMASK 0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TEMP_ADCVOLTAGESHIFT 0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TEMP_ADCWRITECTRL 0x08c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TEMP_MSR0 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TEMP_MSR1 0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TEMP_MSR2 0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TEMP_MSR3 0x0B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TEMP_SPARE0 0x0f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TEMP_ADCPNP0_1 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TEMP_ADCPNP1_1 0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TEMP_ADCPNP2_1 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TEMP_MSR0_1 0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TEMP_MSR1_1 0x194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TEMP_MSR2_1 0x198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TEMP_ADCPNP3_1 0x1b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TEMP_MSR3_1 0x1B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PTPCORESEL 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* MT8173 thermal sensors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MT8173_TS1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MT8173_TS2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MT8173_TS3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MT8173_TS4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MT8173_TSABB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* AUXADC channel 11 is used for the temperature sensors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MT8173_TEMP_AUXADC_CHANNEL 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* The total number of temperature sensors in the MT8173 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MT8173_NUM_SENSORS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* The number of banks in the MT8173 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MT8173_NUM_ZONES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* The number of sensing points per bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MT8173_NUM_SENSORS_PER_ZONE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* The number of controller in the MT8173 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MT8173_NUM_CONTROLLER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* The calibration coefficient of sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MT8173_CALIBRATION 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Layout of the fuses providing the calibration data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * MT8183 has 6 sensors and needs 6 VTS calibration data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * MT8173 has 5 sensors and needs 5 VTS calibration data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * MT2701 has 3 sensors and needs 3 VTS calibration data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * MT2712 has 4 sensors and needs 4 VTS calibration data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CALIB_BUF0_VALID_V1 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Layout of the fuses providing the calibration data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * These macros could be used for MT7622.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) VTS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) VTS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) VTS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) VTS4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) VTS5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) VTSABB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MAX_NUM_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) enum mtk_thermal_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MTK_THERMAL_V1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MTK_THERMAL_V2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* MT2701 thermal sensors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MT2701_TS1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MT2701_TS2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MT2701_TSABB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* AUXADC channel 11 is used for the temperature sensors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MT2701_TEMP_AUXADC_CHANNEL 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* The total number of temperature sensors in the MT2701 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MT2701_NUM_SENSORS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* The number of sensing points per bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MT2701_NUM_SENSORS_PER_ZONE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* The number of controller in the MT2701 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MT2701_NUM_CONTROLLER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* The calibration coefficient of sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MT2701_CALIBRATION 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* MT2712 thermal sensors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MT2712_TS1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MT2712_TS2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MT2712_TS3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MT2712_TS4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* AUXADC channel 11 is used for the temperature sensors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MT2712_TEMP_AUXADC_CHANNEL 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* The total number of temperature sensors in the MT2712 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MT2712_NUM_SENSORS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* The number of sensing points per bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MT2712_NUM_SENSORS_PER_ZONE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* The number of controller in the MT2712 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MT2712_NUM_CONTROLLER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* The calibration coefficient of sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MT2712_CALIBRATION 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MT7622_TEMP_AUXADC_CHANNEL 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MT7622_NUM_SENSORS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MT7622_NUM_ZONES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MT7622_NUM_SENSORS_PER_ZONE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MT7622_TS1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MT7622_NUM_CONTROLLER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* The maximum number of banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MAX_NUM_ZONES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* The calibration coefficient of sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MT7622_CALIBRATION 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* MT8183 thermal sensors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MT8183_TS1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MT8183_TS2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MT8183_TS3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MT8183_TS4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MT8183_TS5 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MT8183_TSABB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* AUXADC channel is used for the temperature sensors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MT8183_TEMP_AUXADC_CHANNEL 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* The total number of temperature sensors in the MT8183 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MT8183_NUM_SENSORS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* The number of banks in the MT8183 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MT8183_NUM_ZONES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* The number of sensing points per bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MT8183_NUM_SENSORS_PER_ZONE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* The number of controller in the MT8183 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MT8183_NUM_CONTROLLER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* The calibration coefficient of sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MT8183_CALIBRATION 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct mtk_thermal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct thermal_bank_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int num_sensors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) const int *sensors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct mtk_thermal_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct mtk_thermal *mt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct mtk_thermal_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) s32 num_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) s32 num_sensors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) s32 auxadc_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) const int *vts_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) const int *sensor_mux_values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) const int *msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) const int *adcpnp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) const int cali_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) const int num_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) const int *controller_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) bool need_switch_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) enum mtk_thermal_version version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct mtk_thermal {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) void __iomem *thermal_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct clk *clk_peri_therm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct clk *clk_auxadc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* lock: for getting and putting banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Calibration values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) s32 adc_ge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) s32 adc_oe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) s32 degc_cali;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) s32 o_slope;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) s32 o_slope_sign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) s32 vts[MAX_NUM_VTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) const struct mtk_thermal_data *conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct mtk_thermal_bank banks[MAX_NUM_ZONES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* MT8183 thermal sensor data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* MT8173 thermal sensor data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { MT8173_TS2, MT8173_TS3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { MT8173_TS2, MT8173_TS4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { MT8173_TS2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) VTS1, VTS2, VTS3, VTS4, VTSABB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* MT2701 thermal sensor data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MT2701_TS1, MT2701_TS2, MT2701_TSABB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) VTS1, VTS2, VTS3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* MT2712 thermal sensor data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) VTS1, VTS2, VTS3, VTS4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* MT7622 thermal sensor data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * The MT8173 thermal controller has four banks. Each bank can read up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * four temperature sensors simultaneously. The MT8173 has a total of 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * temperature sensors. We use each bank to measure a certain area of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * areas, hence is used in different banks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * The thermal core only gets the maximum temperature of all banks, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * the bank concept wouldn't be necessary here. However, the SVS (Smart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * Voltage Scaling) unit makes its decisions based on the same bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * data, and this indeed needs the temperatures of the individual banks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * for making better decisions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const struct mtk_thermal_data mt8173_thermal_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .num_banks = MT8173_NUM_ZONES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .num_sensors = MT8173_NUM_SENSORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .vts_index = mt8173_vts_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .cali_val = MT8173_CALIBRATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .num_controller = MT8173_NUM_CONTROLLER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .controller_offset = mt8173_tc_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .need_switch_bank = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .bank_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .num_sensors = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .sensors = mt8173_bank_data[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .num_sensors = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .sensors = mt8173_bank_data[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .num_sensors = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .sensors = mt8173_bank_data[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .num_sensors = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .sensors = mt8173_bank_data[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .msr = mt8173_msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .adcpnp = mt8173_adcpnp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .sensor_mux_values = mt8173_mux_values,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .version = MTK_THERMAL_V1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * The MT2701 thermal controller has one bank, which can read up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * three temperature sensors simultaneously. The MT2701 has a total of 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * temperature sensors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * The thermal core only gets the maximum temperature of this one bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * so the bank concept wouldn't be necessary here. However, the SVS (Smart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * Voltage Scaling) unit makes its decisions based on the same bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const struct mtk_thermal_data mt2701_thermal_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .num_banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .num_sensors = MT2701_NUM_SENSORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .vts_index = mt2701_vts_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .cali_val = MT2701_CALIBRATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .num_controller = MT2701_NUM_CONTROLLER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .controller_offset = mt2701_tc_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .need_switch_bank = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .bank_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .num_sensors = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .sensors = mt2701_bank_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .msr = mt2701_msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .adcpnp = mt2701_adcpnp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .sensor_mux_values = mt2701_mux_values,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .version = MTK_THERMAL_V1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * The MT2712 thermal controller has one bank, which can read up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * four temperature sensors simultaneously. The MT2712 has a total of 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * temperature sensors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * The thermal core only gets the maximum temperature of this one bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * so the bank concept wouldn't be necessary here. However, the SVS (Smart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * Voltage Scaling) unit makes its decisions based on the same bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static const struct mtk_thermal_data mt2712_thermal_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .num_banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .num_sensors = MT2712_NUM_SENSORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .vts_index = mt2712_vts_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .cali_val = MT2712_CALIBRATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .num_controller = MT2712_NUM_CONTROLLER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .controller_offset = mt2712_tc_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .need_switch_bank = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .bank_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .num_sensors = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .sensors = mt2712_bank_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .msr = mt2712_msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .adcpnp = mt2712_adcpnp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .sensor_mux_values = mt2712_mux_values,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .version = MTK_THERMAL_V1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static const struct mtk_thermal_data mt7622_thermal_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .num_banks = MT7622_NUM_ZONES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .num_sensors = MT7622_NUM_SENSORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .vts_index = mt7622_vts_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .cali_val = MT7622_CALIBRATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .num_controller = MT7622_NUM_CONTROLLER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .controller_offset = mt7622_tc_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .need_switch_bank = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .bank_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .num_sensors = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .sensors = mt7622_bank_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .msr = mt7622_msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .adcpnp = mt7622_adcpnp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .sensor_mux_values = mt7622_mux_values,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .version = MTK_THERMAL_V2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * The MT8183 thermal controller has one bank for the current SW framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * The MT8183 has a total of 6 temperature sensors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * There are two thermal controller to control the six sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * The first one bind 2 sensor, and the other bind 4 sensors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * The thermal core only gets the maximum temperature of all sensor, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * the bank concept wouldn't be necessary here. However, the SVS (Smart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * Voltage Scaling) unit makes its decisions based on the same bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * data, and this indeed needs the temperatures of the individual banks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * for making better decisions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const struct mtk_thermal_data mt8183_thermal_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .num_banks = MT8183_NUM_ZONES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .num_sensors = MT8183_NUM_SENSORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .vts_index = mt8183_vts_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .cali_val = MT8183_CALIBRATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .num_controller = MT8183_NUM_CONTROLLER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .controller_offset = mt8183_tc_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .need_switch_bank = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .bank_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .num_sensors = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .sensors = mt8183_bank_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .msr = mt8183_msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .adcpnp = mt8183_adcpnp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .sensor_mux_values = mt8183_mux_values,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .version = MTK_THERMAL_V1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * raw_to_mcelsius - convert a raw ADC value to mcelsius
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * @mt: The thermal controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * @sensno: sensor number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * @raw: raw ADC value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * This converts the raw ADC value to mcelsius using the SoC specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * calibration constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) s32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) raw &= 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) tmp = 203450520 << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) tmp /= mt->conf->cali_val + mt->o_slope;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) tmp /= 10000 + mt->adc_ge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) tmp *= raw - mt->vts[sensno] - 3350;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) tmp >>= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return mt->degc_cali * 500 - tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) s32 format_1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) s32 format_2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) s32 g_oe = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) s32 g_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) s32 g_x_roomt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) s32 tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (raw == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) raw &= 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) g_oe = mt->adc_oe - 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) format_1 = mt->vts[VTS2] + 3105 - g_oe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) format_2 = (mt->degc_cali * 10) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) tmp = tmp * 10 * 100 / 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (mt->o_slope_sign == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) tmp = tmp / (165 - mt->o_slope);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) tmp = tmp / (165 + mt->o_slope);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return (format_2 - tmp) * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * mtk_thermal_get_bank - get bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * @bank: The bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * The bank registers are banked, we have to select a bank in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * PTPCORESEL register to access it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct mtk_thermal *mt = bank->mt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (mt->conf->need_switch_bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) mutex_lock(&mt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) val = readl(mt->thermal_base + PTPCORESEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) val &= ~0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) val |= bank->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) writel(val, mt->thermal_base + PTPCORESEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * mtk_thermal_put_bank - release bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * @bank: The bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * release a bank previously taken with mtk_thermal_get_bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct mtk_thermal *mt = bank->mt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (mt->conf->need_switch_bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) mutex_unlock(&mt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * mtk_thermal_bank_temperature - get the temperature of a bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * @bank: The bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * The temperature of a bank is considered the maximum temperature of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * the sensors associated to the bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct mtk_thermal *mt = bank->mt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) const struct mtk_thermal_data *conf = mt->conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int i, temp = INT_MIN, max = INT_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) u32 raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) raw = readl(mt->thermal_base + conf->msr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (mt->conf->version == MTK_THERMAL_V1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) temp = raw_to_mcelsius_v1(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) mt, conf->bank_data[bank->id].sensors[i], raw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) temp = raw_to_mcelsius_v2(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) mt, conf->bank_data[bank->id].sensors[i], raw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * The first read of a sensor often contains very high bogus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * temperature value. Filter these out so that the system does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * not immediately shut down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (temp > 200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (temp > max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) max = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static int mtk_read_temp(void *data, int *temperature)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct mtk_thermal *mt = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) int tempmax = INT_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) for (i = 0; i < mt->conf->num_banks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct mtk_thermal_bank *bank = &mt->banks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) mtk_thermal_get_bank(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) mtk_thermal_put_bank(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) *temperature = tempmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .get_temp = mtk_read_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) u32 apmixed_phys_base, u32 auxadc_phys_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int ctrl_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct mtk_thermal_bank *bank = &mt->banks[num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) const struct mtk_thermal_data *conf = mt->conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) int offset = mt->conf->controller_offset[ctrl_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) void __iomem *controller_base = mt->thermal_base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) bank->id = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) bank->mt = mt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) mtk_thermal_get_bank(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * filt interval is 1 * 46.540us = 46.54us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * sen interval is 429 * 46.540us = 19.96ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) TEMP_MONCTL2_SENSOR_INTERVAL(429),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) controller_base + TEMP_MONCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* poll is set to 10u */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) controller_base + TEMP_AHBPOLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* temperature sampling control, 1 sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) writel(0x0, controller_base + TEMP_MSRCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* exceed this polling time, IRQ would be inserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) writel(0xffffffff, controller_base + TEMP_AHBTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* number of interrupts per event, 1 is enough */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) writel(0x0, controller_base + TEMP_MONIDET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) writel(0x0, controller_base + TEMP_MONIDET1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * The MT8173 thermal controller does not have its own ADC. Instead it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * uses AHB bus accesses to control the AUXADC. To do this the thermal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * controller has to be programmed with the physical addresses of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * AUXADC registers and with the various bit positions in the AUXADC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * Also the thermal controller controls a mux in the APMIXEDSYS register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * automatically by hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* AHB address for auxadc mux selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) controller_base + TEMP_ADCMUXADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (mt->conf->version == MTK_THERMAL_V1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* AHB address for pnp sensor mux selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) controller_base + TEMP_PNPMUXADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* AHB value for auxadc enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* AHB address for auxadc enable (channel 0 immediate mode selected) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) writel(auxadc_phys_base + AUXADC_CON1_SET_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) controller_base + TEMP_ADCENADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* AHB address for auxadc valid bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) controller_base + TEMP_ADCVALIDADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* AHB address for auxadc voltage output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) controller_base + TEMP_ADCVOLTADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* read valid & voltage are at the same register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) writel(0x0, controller_base + TEMP_RDCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* indicate where the valid bit is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) controller_base + TEMP_ADCVALIDMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* no shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* enable auxadc mux write transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) controller_base + TEMP_ADCWRITECTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) for (i = 0; i < conf->bank_data[num].num_sensors; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) mt->thermal_base + conf->adcpnp[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) writel((1 << conf->bank_data[num].num_sensors) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) controller_base + TEMP_MONCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) controller_base + TEMP_ADCWRITECTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mtk_thermal_put_bank(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static u64 of_get_phys_base(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) u64 size64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) const __be32 *regaddr_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) regaddr_p = of_get_address(np, 0, &size64, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (!regaddr_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return OF_BAD_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return of_translate_address(np, regaddr_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!(buf[0] & CALIB_BUF0_VALID_V1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) for (i = 0; i < mt->conf->num_sensors; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) switch (mt->conf->vts_index[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) case VTS1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) case VTS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) case VTS3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) case VTS4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) case VTS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) case VTSABB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) mt->vts[VTSABB] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) CALIB_BUF2_VTS_TSABB_V1(buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (CALIB_BUF1_ID_V1(buf[1]) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (!CALIB_BUF1_VALID_V2(buf[1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static int mtk_thermal_get_calibration_data(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct mtk_thermal *mt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct nvmem_cell *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) u32 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* Start with default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) mt->adc_ge = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) for (i = 0; i < mt->conf->num_sensors; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) mt->vts[i] = 260;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) mt->degc_cali = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) mt->o_slope = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) cell = nvmem_cell_get(dev, "calibration-data");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (IS_ERR(cell)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (PTR_ERR(cell) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return PTR_ERR(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) buf = (u32 *)nvmem_cell_read(cell, &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) nvmem_cell_put(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (IS_ERR(buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return PTR_ERR(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (len < 3 * sizeof(u32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) dev_warn(dev, "invalid calibration data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (mt->conf->version == MTK_THERMAL_V1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ret = mtk_thermal_extract_efuse_v1(mt, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) ret = mtk_thermal_extract_efuse_v2(mt, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) dev_info(dev, "Device not calibrated, using default calibration values\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static const struct of_device_id mtk_thermal_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .compatible = "mediatek,mt8173-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .data = (void *)&mt8173_thermal_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .compatible = "mediatek,mt2701-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .data = (void *)&mt2701_thermal_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .compatible = "mediatek,mt2712-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .data = (void *)&mt2712_thermal_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .compatible = "mediatek,mt7622-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .data = (void *)&mt7622_thermal_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .compatible = "mediatek,mt8183-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .data = (void *)&mt8183_thermal_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) tmp &= ~(0x37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) tmp |= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) void __iomem *auxadc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) writel(0x1, mt->thermal_base + TEMP_MONCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static int mtk_thermal_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) int ret, i, ctrl_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct mtk_thermal *mt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) u64 auxadc_phys_base, apmixed_phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct thermal_zone_device *tzdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) void __iomem *apmixed_base, *auxadc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (!mt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) mt->conf = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (IS_ERR(mt->clk_peri_therm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return PTR_ERR(mt->clk_peri_therm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (IS_ERR(mt->clk_auxadc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return PTR_ERR(mt->clk_auxadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (IS_ERR(mt->thermal_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return PTR_ERR(mt->thermal_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) mutex_init(&mt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) mt->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (!auxadc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dev_err(&pdev->dev, "missing auxadc node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) auxadc_base = of_iomap(auxadc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) auxadc_phys_base = of_get_phys_base(auxadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) of_node_put(auxadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (auxadc_phys_base == OF_BAD_ADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) dev_err(&pdev->dev, "Can't get auxadc phys address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (!apmixedsys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) dev_err(&pdev->dev, "missing apmixedsys node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) apmixed_base = of_iomap(apmixedsys, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) apmixed_phys_base = of_get_phys_base(apmixedsys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) of_node_put(apmixedsys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (apmixed_phys_base == OF_BAD_ADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) dev_err(&pdev->dev, "Can't get auxadc phys address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ret = device_reset(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ret = clk_prepare_enable(mt->clk_auxadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ret = clk_prepare_enable(mt->clk_peri_therm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) goto err_disable_clk_auxadc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (mt->conf->version == MTK_THERMAL_V2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) mtk_thermal_turn_on_buffer(apmixed_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) mtk_thermal_release_periodic_ts(mt, auxadc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) for (i = 0; i < mt->conf->num_banks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) mtk_thermal_init_bank(mt, i, apmixed_phys_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) auxadc_phys_base, ctrl_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) platform_set_drvdata(pdev, mt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) &mtk_thermal_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (IS_ERR(tzdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) ret = PTR_ERR(tzdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) goto err_disable_clk_peri_therm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) err_disable_clk_peri_therm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) clk_disable_unprepare(mt->clk_peri_therm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) err_disable_clk_auxadc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) clk_disable_unprepare(mt->clk_auxadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static int mtk_thermal_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) struct mtk_thermal *mt = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) clk_disable_unprepare(mt->clk_peri_therm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) clk_disable_unprepare(mt->clk_auxadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static struct platform_driver mtk_thermal_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .probe = mtk_thermal_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .remove = mtk_thermal_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .name = "mtk-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .of_match_table = mtk_thermal_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) module_platform_driver(mtk_thermal_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) MODULE_DESCRIPTION("Mediatek thermal driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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