^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Broadcom STB AVS TMON thermal sensor driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015-2017 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define DRV_NAME "brcmstb_thermal"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define pr_fmt(fmt) DRV_NAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irqreturn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AVS_TMON_STATUS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AVS_TMON_STATUS_valid_msk BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AVS_TMON_STATUS_data_msk GENMASK(10, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AVS_TMON_STATUS_data_shift 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AVS_TMON_EN_OVERTEMP_RESET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AVS_TMON_EN_OVERTEMP_RESET_msk BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AVS_TMON_RESET_THRESH 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AVS_TMON_RESET_THRESH_msk GENMASK(10, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AVS_TMON_RESET_THRESH_shift 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AVS_TMON_INT_IDLE_TIME 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AVS_TMON_EN_TEMP_INT_SRCS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AVS_TMON_EN_TEMP_INT_SRCS_high BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AVS_TMON_EN_TEMP_INT_SRCS_low BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AVS_TMON_INT_THRESH 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AVS_TMON_INT_THRESH_high_msk GENMASK(26, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AVS_TMON_INT_THRESH_high_shift 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AVS_TMON_INT_THRESH_low_msk GENMASK(10, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AVS_TMON_INT_THRESH_low_shift 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AVS_TMON_TEMP_INT_CODE 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AVS_TMON_TP_TEST_ENABLE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Default coefficients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AVS_TMON_TEMP_SLOPE 487
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AVS_TMON_TEMP_OFFSET 410040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* HW related temperature constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AVS_TMON_TEMP_MAX 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AVS_TMON_TEMP_MIN -88161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AVS_TMON_TEMP_MASK AVS_TMON_TEMP_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) enum avs_tmon_trip_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) TMON_TRIP_TYPE_LOW = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) TMON_TRIP_TYPE_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) TMON_TRIP_TYPE_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) TMON_TRIP_TYPE_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct avs_tmon_trip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* HW bit to enable the trip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 enable_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* HW field to read the trip temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 reg_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 reg_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct avs_tmon_trip avs_tmon_trips[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Trips when temperature is below threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [TMON_TRIP_TYPE_LOW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .enable_offs = AVS_TMON_EN_TEMP_INT_SRCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .enable_mask = AVS_TMON_EN_TEMP_INT_SRCS_low,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .reg_offs = AVS_TMON_INT_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .reg_msk = AVS_TMON_INT_THRESH_low_msk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .reg_shift = AVS_TMON_INT_THRESH_low_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Trips when temperature is above threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [TMON_TRIP_TYPE_HIGH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .enable_offs = AVS_TMON_EN_TEMP_INT_SRCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .enable_mask = AVS_TMON_EN_TEMP_INT_SRCS_high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .reg_offs = AVS_TMON_INT_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .reg_msk = AVS_TMON_INT_THRESH_high_msk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .reg_shift = AVS_TMON_INT_THRESH_high_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Automatically resets chip when above threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) [TMON_TRIP_TYPE_RESET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .enable_offs = AVS_TMON_EN_OVERTEMP_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .enable_mask = AVS_TMON_EN_OVERTEMP_RESET_msk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .reg_offs = AVS_TMON_RESET_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .reg_msk = AVS_TMON_RESET_THRESH_msk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .reg_shift = AVS_TMON_RESET_THRESH_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct brcmstb_thermal_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) const struct thermal_zone_of_device_ops *of_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct brcmstb_thermal_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void __iomem *tmon_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct thermal_zone_device *thermal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Process specific thermal parameters used for calculations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) const struct brcmstb_thermal_params *temp_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Convert a HW code to a temperature reading (millidegree celsius) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline int avs_tmon_code_to_temp(struct brcmstb_thermal_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int offset = priv->temp_params->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int mult = priv->temp_params->mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return (offset - (int)((code & AVS_TMON_TEMP_MASK) * mult));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Convert a temperature value (millidegree celsius) to a HW code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @temp: temperature to convert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @low: if true, round toward the low side
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static inline u32 avs_tmon_temp_to_code(struct brcmstb_thermal_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int temp, bool low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int offset = priv->temp_params->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int mult = priv->temp_params->mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (temp < AVS_TMON_TEMP_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return AVS_TMON_TEMP_MAX; /* Maximum code value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (temp >= offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return 0; /* Minimum code value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return (u32)(DIV_ROUND_UP(offset - temp, mult));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return (u32)((offset - temp) / mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int brcmstb_get_temp(void *data, int *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct brcmstb_thermal_priv *priv = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) long t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val = __raw_readl(priv->tmon_base + AVS_TMON_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (!(val & AVS_TMON_STATUS_valid_msk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_err(priv->dev, "reading not valid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) val = (val & AVS_TMON_STATUS_data_msk) >> AVS_TMON_STATUS_data_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) t = avs_tmon_code_to_temp(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (t < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) *temp = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void avs_tmon_trip_enable(struct brcmstb_thermal_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) enum avs_tmon_trip_type type, int en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct avs_tmon_trip *trip = &avs_tmon_trips[type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 val = __raw_readl(priv->tmon_base + trip->enable_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_dbg(priv->dev, "%sable trip, type %d\n", en ? "en" : "dis", type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) val |= trip->enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) val &= ~trip->enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) __raw_writel(val, priv->tmon_base + trip->enable_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int avs_tmon_get_trip_temp(struct brcmstb_thermal_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) enum avs_tmon_trip_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct avs_tmon_trip *trip = &avs_tmon_trips[type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 val = __raw_readl(priv->tmon_base + trip->reg_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) val &= trip->reg_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) val >>= trip->reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return avs_tmon_code_to_temp(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void avs_tmon_set_trip_temp(struct brcmstb_thermal_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) enum avs_tmon_trip_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct avs_tmon_trip *trip = &avs_tmon_trips[type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 val, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_dbg(priv->dev, "set temp %d to %d\n", type, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* round toward low temp for the low interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) val = avs_tmon_temp_to_code(priv, temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) type == TMON_TRIP_TYPE_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) val <<= trip->reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) val &= trip->reg_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) orig = __raw_readl(priv->tmon_base + trip->reg_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) orig &= ~trip->reg_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) orig |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) __raw_writel(orig, priv->tmon_base + trip->reg_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int avs_tmon_get_intr_temp(struct brcmstb_thermal_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) val = __raw_readl(priv->tmon_base + AVS_TMON_TEMP_INT_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return avs_tmon_code_to_temp(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static irqreturn_t brcmstb_tmon_irq_thread(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct brcmstb_thermal_priv *priv = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int low, high, intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) low = avs_tmon_get_trip_temp(priv, TMON_TRIP_TYPE_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) high = avs_tmon_get_trip_temp(priv, TMON_TRIP_TYPE_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) intr = avs_tmon_get_intr_temp(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_dbg(priv->dev, "low/intr/high: %d/%d/%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) low, intr, high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Disable high-temp until next threshold shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (intr >= high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) avs_tmon_trip_enable(priv, TMON_TRIP_TYPE_HIGH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Disable low-temp until next threshold shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (intr <= low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) avs_tmon_trip_enable(priv, TMON_TRIP_TYPE_LOW, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Notify using the interrupt temperature, in case the temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * changes before it can next be read out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) thermal_zone_device_update(priv->thermal, intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int brcmstb_set_trips(void *data, int low, int high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct brcmstb_thermal_priv *priv = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_dbg(priv->dev, "set trips %d <--> %d\n", low, high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * Disable low-temp if "low" is too small. As per thermal framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * API, we use -INT_MAX rather than INT_MIN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (low <= -INT_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) avs_tmon_trip_enable(priv, TMON_TRIP_TYPE_LOW, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) avs_tmon_set_trip_temp(priv, TMON_TRIP_TYPE_LOW, low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) avs_tmon_trip_enable(priv, TMON_TRIP_TYPE_LOW, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Disable high-temp if "high" is too big. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (high == INT_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) avs_tmon_trip_enable(priv, TMON_TRIP_TYPE_HIGH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) avs_tmon_set_trip_temp(priv, TMON_TRIP_TYPE_HIGH, high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) avs_tmon_trip_enable(priv, TMON_TRIP_TYPE_HIGH, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct thermal_zone_of_device_ops brcmstb_16nm_of_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .get_temp = brcmstb_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const struct brcmstb_thermal_params brcmstb_16nm_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .offset = 457829,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .mult = 557,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .of_ops = &brcmstb_16nm_of_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const struct thermal_zone_of_device_ops brcmstb_28nm_of_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .get_temp = brcmstb_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .set_trips = brcmstb_set_trips,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct brcmstb_thermal_params brcmstb_28nm_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .offset = 410040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .mult = 487,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .of_ops = &brcmstb_28nm_of_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const struct of_device_id brcmstb_thermal_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { .compatible = "brcm,avs-tmon-bcm7216", .data = &brcmstb_16nm_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { .compatible = "brcm,avs-tmon", .data = &brcmstb_28nm_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_DEVICE_TABLE(of, brcmstb_thermal_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int brcmstb_thermal_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) const struct thermal_zone_of_device_ops *of_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct thermal_zone_device *thermal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct brcmstb_thermal_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) priv->temp_params = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (!priv->temp_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) priv->tmon_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (IS_ERR(priv->tmon_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return PTR_ERR(priv->tmon_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) priv->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) of_ops = priv->temp_params->of_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) thermal = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) of_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (IS_ERR(thermal)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ret = PTR_ERR(thermal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dev_err(&pdev->dev, "could not register sensor: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) priv->thermal = thermal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) brcmstb_tmon_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) DRV_NAME, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev_err(&pdev->dev, "could not request IRQ: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev_info(&pdev->dev, "registered AVS TMON of-sensor driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static struct platform_driver brcmstb_thermal_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .probe = brcmstb_thermal_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .of_match_table = brcmstb_thermal_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) module_platform_driver(brcmstb_thermal_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MODULE_AUTHOR("Brian Norris");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MODULE_DESCRIPTION("Broadcom STB AVS TMON thermal driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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