^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell EBU Armada SoCs thermal sensor driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "thermal_core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Thermal Manager Control and Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PMU_TDC0_SW_RST_MASK (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PMU_TM_DISABLE_OFFS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PMU_TM_DISABLE_MASK (0x1 << PMU_TM_DISABLE_OFFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PMU_TDC0_REF_CAL_CNT_OFFS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PMU_TDC0_REF_CAL_CNT_MASK (0x1ff << PMU_TDC0_REF_CAL_CNT_OFFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PMU_TDC0_OTF_CAL_MASK (0x1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PMU_TDC0_START_CAL_MASK (0x1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define A375_UNIT_CONTROL_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define A375_UNIT_CONTROL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define A375_READOUT_INVERT BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define A375_HW_RESETn BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Errata fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CONTROL0_TSEN_TC_TRIM_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CONTROL0_TSEN_TC_TRIM_VAL 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CONTROL0_TSEN_START BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CONTROL0_TSEN_RESET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CONTROL0_TSEN_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CONTROL0_TSEN_AVG_BYPASS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CONTROL0_TSEN_CHAN_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CONTROL0_TSEN_CHAN_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CONTROL0_TSEN_OSR_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CONTROL0_TSEN_OSR_MAX 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CONTROL0_TSEN_MODE_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CONTROL0_TSEN_MODE_EXTERNAL 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CONTROL0_TSEN_MODE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CONTROL1_TSEN_AVG_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CONTROL1_EXT_TSEN_SW_RESET BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CONTROL1_EXT_TSEN_HW_RESETn BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CONTROL1_TSEN_INT_EN BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CONTROL1_TSEN_SELECT_OFF 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CONTROL1_TSEN_SELECT_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define STATUS_POLL_PERIOD_US 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define STATUS_POLL_TIMEOUT_US 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OVERHEAT_INT_POLL_DELAY_MS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct armada_thermal_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Marvell EBU Thermal Sensor Dev Structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct armada_thermal_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct regmap *syscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) char zone_name[THERMAL_NAME_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* serialize temperature reads/updates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct mutex update_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct armada_thermal_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct thermal_zone_device *overheat_sensor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int interrupt_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int current_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) long current_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) long current_hysteresis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct armada_thermal_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Initialize the thermal IC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) void (*init)(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct armada_thermal_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Formula coeficients: temp = (b - m * reg) / div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) s64 coef_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) s64 coef_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 coef_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bool inverted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) bool signed_sample;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Register shift and mask to access the sensor temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int temp_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int temp_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int thresh_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int hyst_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int hyst_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 is_valid_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Syscon access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int syscon_control0_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int syscon_control1_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int syscon_status_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int dfx_irq_cause_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int dfx_irq_mask_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int dfx_overheat_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int dfx_server_irq_mask_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int dfx_server_irq_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* One sensor is in the thermal IC, the others are in the CPUs if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int cpu_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct armada_drvdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) enum drvtype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) } type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct armada_thermal_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct thermal_zone_device *tz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) } data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * struct armada_thermal_sensor - hold the information of one thermal sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @thermal: pointer to the local private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @tzd: pointer to the thermal zone device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @id: identifier of the thermal sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct armada_thermal_sensor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct armada_thermal_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void armadaxp_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct armada_thermal_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct armada_thermal_data *data = priv->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) regmap_read(priv->syscon, data->syscon_control1_off, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) reg |= PMU_TDC0_OTF_CAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Reference calibration value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) reg &= ~PMU_TDC0_REF_CAL_CNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Reset the sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) reg |= PMU_TDC0_SW_RST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) regmap_write(priv->syscon, data->syscon_control1_off, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) reg &= ~PMU_TDC0_SW_RST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) regmap_write(priv->syscon, data->syscon_control1_off, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Enable the sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) regmap_read(priv->syscon, data->syscon_status_off, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) reg &= ~PMU_TM_DISABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) regmap_write(priv->syscon, data->syscon_status_off, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void armada370_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct armada_thermal_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct armada_thermal_data *data = priv->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) regmap_read(priv->syscon, data->syscon_control1_off, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) reg |= PMU_TDC0_OTF_CAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Reference calibration value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) reg &= ~PMU_TDC0_REF_CAL_CNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Reset the sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) reg &= ~PMU_TDC0_START_CAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) regmap_write(priv->syscon, data->syscon_control1_off, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void armada375_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct armada_thermal_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct armada_thermal_data *data = priv->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) regmap_read(priv->syscon, data->syscon_control1_off, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) reg &= ~(A375_UNIT_CONTROL_MASK << A375_UNIT_CONTROL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) reg &= ~A375_READOUT_INVERT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) reg &= ~A375_HW_RESETn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) regmap_write(priv->syscon, data->syscon_control1_off, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) reg |= A375_HW_RESETn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) regmap_write(priv->syscon, data->syscon_control1_off, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int armada_wait_sensor_validity(struct armada_thermal_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return regmap_read_poll_timeout(priv->syscon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) priv->data->syscon_status_off, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) reg & priv->data->is_valid_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) STATUS_POLL_PERIOD_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) STATUS_POLL_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void armada380_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct armada_thermal_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct armada_thermal_data *data = priv->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Disable the HW/SW reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) regmap_read(priv->syscon, data->syscon_control1_off, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) reg |= CONTROL1_EXT_TSEN_HW_RESETn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) reg &= ~CONTROL1_EXT_TSEN_SW_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) regmap_write(priv->syscon, data->syscon_control1_off, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Set Tsen Tc Trim to correct default value (errata #132698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) regmap_read(priv->syscon, data->syscon_control0_off, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) reg &= ~CONTROL0_TSEN_TC_TRIM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) reg |= CONTROL0_TSEN_TC_TRIM_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) regmap_write(priv->syscon, data->syscon_control0_off, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void armada_ap806_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct armada_thermal_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct armada_thermal_data *data = priv->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) regmap_read(priv->syscon, data->syscon_control0_off, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) reg &= ~CONTROL0_TSEN_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) reg |= CONTROL0_TSEN_START | CONTROL0_TSEN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Sample every ~2ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) reg |= CONTROL0_TSEN_OSR_MAX << CONTROL0_TSEN_OSR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Enable average (2 samples by default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) reg &= ~CONTROL0_TSEN_AVG_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) regmap_write(priv->syscon, data->syscon_control0_off, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static void armada_cp110_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct armada_thermal_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct armada_thermal_data *data = priv->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) armada380_init(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Sample every ~2ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) regmap_read(priv->syscon, data->syscon_control0_off, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) reg |= CONTROL0_TSEN_OSR_MAX << CONTROL0_TSEN_OSR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) regmap_write(priv->syscon, data->syscon_control0_off, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Average the output value over 2^1 = 2 samples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) regmap_read(priv->syscon, data->syscon_control1_off, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) reg &= ~CONTROL1_TSEN_AVG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) reg |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) regmap_write(priv->syscon, data->syscon_control1_off, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static bool armada_is_valid(struct armada_thermal_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (!priv->data->is_valid_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) regmap_read(priv->syscon, priv->data->syscon_status_off, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return reg & priv->data->is_valid_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static void armada_enable_overheat_interrupt(struct armada_thermal_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct armada_thermal_data *data = priv->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Clear DFX temperature IRQ cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) regmap_read(priv->syscon, data->dfx_irq_cause_off, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Enable DFX Temperature IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) regmap_read(priv->syscon, data->dfx_irq_mask_off, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) reg |= data->dfx_overheat_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) regmap_write(priv->syscon, data->dfx_irq_mask_off, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Enable DFX server IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) regmap_read(priv->syscon, data->dfx_server_irq_mask_off, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) reg |= data->dfx_server_irq_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) regmap_write(priv->syscon, data->dfx_server_irq_mask_off, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Enable overheat interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) regmap_read(priv->syscon, data->syscon_control1_off, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) reg |= CONTROL1_TSEN_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) regmap_write(priv->syscon, data->syscon_control1_off, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void __maybe_unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) armada_disable_overheat_interrupt(struct armada_thermal_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct armada_thermal_data *data = priv->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) regmap_read(priv->syscon, data->syscon_control1_off, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) reg &= ~CONTROL1_TSEN_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) regmap_write(priv->syscon, data->syscon_control1_off, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* There is currently no board with more than one sensor per channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int armada_select_channel(struct armada_thermal_priv *priv, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct armada_thermal_data *data = priv->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 ctrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (channel < 0 || channel > priv->data->cpu_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (priv->current_channel == channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Stop the measurements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) regmap_read(priv->syscon, data->syscon_control0_off, &ctrl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ctrl0 &= ~CONTROL0_TSEN_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) regmap_write(priv->syscon, data->syscon_control0_off, ctrl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Reset the mode, internal sensor will be automatically selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ctrl0 &= ~(CONTROL0_TSEN_MODE_MASK << CONTROL0_TSEN_MODE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Other channels are external and should be selected accordingly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Change the mode to external */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ctrl0 |= CONTROL0_TSEN_MODE_EXTERNAL <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) CONTROL0_TSEN_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Select the sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ctrl0 &= ~(CONTROL0_TSEN_CHAN_MASK << CONTROL0_TSEN_CHAN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ctrl0 |= (channel - 1) << CONTROL0_TSEN_CHAN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Actually set the mode/channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) regmap_write(priv->syscon, data->syscon_control0_off, ctrl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) priv->current_channel = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Re-start the measurements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ctrl0 |= CONTROL0_TSEN_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) regmap_write(priv->syscon, data->syscon_control0_off, ctrl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * The IP has a latency of ~15ms, so after updating the selected source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * we must absolutely wait for the sensor validity bit to ensure we read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * actual data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (armada_wait_sensor_validity(priv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev_err(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "Temperature sensor reading not valid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int armada_read_sensor(struct armada_thermal_priv *priv, int *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u32 reg, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) s64 sample, b, m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) regmap_read(priv->syscon, priv->data->syscon_status_off, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) reg = (reg >> priv->data->temp_shift) & priv->data->temp_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (priv->data->signed_sample)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* The most significant bit is the sign bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) sample = sign_extend32(reg, fls(priv->data->temp_mask) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) sample = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Get formula coeficients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) b = priv->data->coef_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) m = priv->data->coef_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) div = priv->data->coef_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (priv->data->inverted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) *temp = div_s64((m * sample) - b, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) *temp = div_s64(b - (m * sample), div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int armada_get_temp_legacy(struct thermal_zone_device *thermal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct armada_thermal_priv *priv = thermal->devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Valid check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!armada_is_valid(priv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev_err(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "Temperature sensor reading not valid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Do the actual reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret = armada_read_sensor(priv, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static struct thermal_zone_device_ops legacy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .get_temp = armada_get_temp_legacy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static int armada_get_temp(void *_sensor, int *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct armada_thermal_sensor *sensor = _sensor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct armada_thermal_priv *priv = sensor->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) mutex_lock(&priv->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Select the desired channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = armada_select_channel(priv, sensor->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) goto unlock_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* Do the actual reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ret = armada_read_sensor(priv, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) goto unlock_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * Select back the interrupt source channel from which a potential
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * critical trip point has been set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ret = armada_select_channel(priv, priv->interrupt_source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unlock_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) mutex_unlock(&priv->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static const struct thermal_zone_of_device_ops of_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .get_temp = armada_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static unsigned int armada_mc_to_reg_temp(struct armada_thermal_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned int temp_mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) s64 b = data->coef_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) s64 m = data->coef_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) s64 div = data->coef_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned int sample;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (data->inverted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) sample = div_s64(((temp_mc * div) + b), m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) sample = div_s64((b - (temp_mc * div)), m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return sample & data->temp_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * The documentation states:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * high/low watermark = threshold +/- 0.4761 * 2^(hysteresis + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * which is the mathematical derivation for:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * 0x0 <=> 1.9°C, 0x1 <=> 3.8°C, 0x2 <=> 7.6°C, 0x3 <=> 15.2°C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static unsigned int hyst_levels_mc[] = {1900, 3800, 7600, 15200};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static unsigned int armada_mc_to_reg_hyst(struct armada_thermal_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unsigned int hyst_mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * We will always take the smallest possible hysteresis to avoid risking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * the hardware integrity by enlarging the threshold by +8°C in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * worst case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) for (i = ARRAY_SIZE(hyst_levels_mc) - 1; i > 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (hyst_mc >= hyst_levels_mc[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return i & data->hyst_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static void armada_set_overheat_thresholds(struct armada_thermal_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int thresh_mc, int hyst_mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct armada_thermal_data *data = priv->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned int threshold = armada_mc_to_reg_temp(data, thresh_mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned int hysteresis = armada_mc_to_reg_hyst(data, hyst_mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u32 ctrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) regmap_read(priv->syscon, data->syscon_control1_off, &ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Set Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (thresh_mc >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ctrl1 &= ~(data->temp_mask << data->thresh_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ctrl1 |= threshold << data->thresh_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) priv->current_threshold = thresh_mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Set Hysteresis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (hyst_mc >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ctrl1 &= ~(data->hyst_mask << data->hyst_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ctrl1 |= hysteresis << data->hyst_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) priv->current_hysteresis = hyst_mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) regmap_write(priv->syscon, data->syscon_control1_off, ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static irqreturn_t armada_overheat_isr(int irq, void *blob)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * Disable the IRQ and continue in thread context (thermal core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * notification and temperature monitoring).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) disable_irq_nosync(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static irqreturn_t armada_overheat_isr_thread(int irq, void *blob)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct armada_thermal_priv *priv = blob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int low_threshold = priv->current_threshold - priv->current_hysteresis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) int temperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* Notify the core in thread context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) thermal_zone_device_update(priv->overheat_sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) THERMAL_EVENT_UNSPECIFIED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * The overheat interrupt must be cleared by reading the DFX interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * cause _after_ the temperature has fallen down to the low threshold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * Otherwise future interrupts might not be served.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) msleep(OVERHEAT_INT_POLL_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) mutex_lock(&priv->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = armada_read_sensor(priv, &temperature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mutex_unlock(&priv->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) goto enable_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) } while (temperature >= low_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) regmap_read(priv->syscon, priv->data->dfx_irq_cause_off, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Notify the thermal core that the temperature is acceptable again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) thermal_zone_device_update(priv->overheat_sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) THERMAL_EVENT_UNSPECIFIED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) enable_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) enable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static const struct armada_thermal_data armadaxp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .init = armadaxp_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .temp_shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .temp_mask = 0x1ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .coef_b = 3153000000ULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .coef_m = 10000000ULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .coef_div = 13825,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .syscon_status_off = 0xb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .syscon_control1_off = 0x2d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static const struct armada_thermal_data armada370_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .init = armada370_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .is_valid_bit = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .temp_shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .temp_mask = 0x1ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .coef_b = 3153000000ULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .coef_m = 10000000ULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .coef_div = 13825,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .syscon_status_off = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .syscon_control1_off = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static const struct armada_thermal_data armada375_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .init = armada375_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .is_valid_bit = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .temp_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .temp_mask = 0x1ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .coef_b = 3171900000ULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .coef_m = 10000000ULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .coef_div = 13616,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .syscon_status_off = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .syscon_control0_off = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .syscon_control1_off = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const struct armada_thermal_data armada380_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .init = armada380_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .is_valid_bit = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .temp_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .temp_mask = 0x3ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .coef_b = 1172499100ULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .coef_m = 2000096ULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .coef_div = 4201,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .inverted = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .syscon_control0_off = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .syscon_control1_off = 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .syscon_status_off = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static const struct armada_thermal_data armada_ap806_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .init = armada_ap806_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .is_valid_bit = BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .temp_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .temp_mask = 0x3ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .thresh_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .hyst_shift = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .hyst_mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .coef_b = -150000LL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .coef_m = 423ULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .coef_div = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .inverted = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .signed_sample = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .syscon_control0_off = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .syscon_control1_off = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .syscon_status_off = 0x8C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .dfx_irq_cause_off = 0x108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .dfx_irq_mask_off = 0x10C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .dfx_overheat_irq = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .dfx_server_irq_mask_off = 0x104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .dfx_server_irq_en = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .cpu_nr = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static const struct armada_thermal_data armada_cp110_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .init = armada_cp110_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .is_valid_bit = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .temp_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .temp_mask = 0x3ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .thresh_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .hyst_shift = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .hyst_mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .coef_b = 1172499100ULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .coef_m = 2000096ULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .coef_div = 4201,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .inverted = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .syscon_control0_off = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .syscon_control1_off = 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .syscon_status_off = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .dfx_irq_cause_off = 0x108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .dfx_irq_mask_off = 0x10C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .dfx_overheat_irq = BIT(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .dfx_server_irq_mask_off = 0x104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .dfx_server_irq_en = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static const struct of_device_id armada_thermal_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .compatible = "marvell,armadaxp-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .data = &armadaxp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .compatible = "marvell,armada370-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .data = &armada370_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .compatible = "marvell,armada375-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .data = &armada375_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .compatible = "marvell,armada380-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .data = &armada380_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .compatible = "marvell,armada-ap806-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .data = &armada_ap806_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .compatible = "marvell,armada-cp110-thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .data = &armada_cp110_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) MODULE_DEVICE_TABLE(of, armada_thermal_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static const struct regmap_config armada_thermal_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static int armada_thermal_probe_legacy(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct armada_thermal_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct armada_thermal_data *data = priv->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* First memory region points towards the status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * Fix up from the old individual DT register specification to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * cover all the registers. We do this by adjusting the ioremap()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * result, which should be fine as ioremap() deals with pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * However, validate that we do not cross a page boundary while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * making this adjustment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (((unsigned long)base & ~PAGE_MASK) < data->syscon_status_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) base -= data->syscon_status_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) priv->syscon = devm_regmap_init_mmio(&pdev->dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) &armada_thermal_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return PTR_ERR_OR_ZERO(priv->syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static int armada_thermal_probe_syscon(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct armada_thermal_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) priv->syscon = syscon_node_to_regmap(pdev->dev.parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return PTR_ERR_OR_ZERO(priv->syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static void armada_set_sane_name(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct armada_thermal_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) const char *name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) char *insane_char;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (strlen(name) > THERMAL_NAME_LENGTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * When inside a system controller, the device name has the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * form: f06f8000.system-controller:ap-thermal so stripping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * after the ':' should give us a shorter but meaningful name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) name = strrchr(name, ':');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (!name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) name = "armada_thermal";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) name++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* Save the name locally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) strncpy(priv->zone_name, name, THERMAL_NAME_LENGTH - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) priv->zone_name[THERMAL_NAME_LENGTH - 1] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* Then check there are no '-' or hwmon core will complain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) insane_char = strpbrk(priv->zone_name, "-");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (insane_char)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) *insane_char = '_';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) } while (insane_char);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * The IP can manage to trigger interrupts on overheat situation from all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * sensors. However, the interrupt source changes along with the last selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * source (ie. the last read sensor), which is an inconsistent behavior. Avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * possible glitches by always selecting back only one channel (arbitrarily: the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * first in the DT which has a critical trip point). We also disable sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * switch during overheat situations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static int armada_configure_overheat_int(struct armada_thermal_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct thermal_zone_device *tz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) int sensor_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* Retrieve the critical trip point to enable the overheat interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) const struct thermal_trip *trips = of_thermal_get_trip_points(tz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (!trips)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) for (i = 0; i < of_thermal_get_ntrips(tz); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (trips[i].type == THERMAL_TRIP_CRITICAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (i == of_thermal_get_ntrips(tz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ret = armada_select_channel(priv, sensor_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) armada_set_overheat_thresholds(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) trips[i].temperature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) trips[i].hysteresis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) priv->overheat_sensor = tz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) priv->interrupt_source = sensor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) armada_enable_overheat_interrupt(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static int armada_thermal_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct thermal_zone_device *tz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct armada_thermal_sensor *sensor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct armada_drvdata *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct armada_thermal_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) int sensor_id, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) match = of_match_device(armada_thermal_id_table, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (!drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) priv->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) priv->data = (struct armada_thermal_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) mutex_init(&priv->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * Legacy DT bindings only described "control1" register (also referred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * as "control MSB" on old documentation). Then, bindings moved to cover
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * "control0/control LSB" and "control1/control MSB" registers within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * the same resource, which was then of size 8 instead of 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * The logic of defining sporadic registers is broken. For instance, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * blocked the addition of the overheat interrupt feature that needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * another resource somewhere else in the same memory area. One solution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * is to define an overall system controller and put the thermal node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * into it, which requires the use of regmaps across all the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (IS_ERR(syscon_node_to_regmap(pdev->dev.parent->of_node))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* Ensure device name is correct for the thermal core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) armada_set_sane_name(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ret = armada_thermal_probe_legacy(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) priv->data->init(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* Wait the sensors to be valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) armada_wait_sensor_validity(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) tz = thermal_zone_device_register(priv->zone_name, 0, 0, priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) &legacy_ops, NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (IS_ERR(tz)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) "Failed to register thermal zone device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return PTR_ERR(tz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ret = thermal_zone_device_enable(tz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) thermal_zone_device_unregister(tz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) drvdata->type = LEGACY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) drvdata->data.tz = tz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) platform_set_drvdata(pdev, drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ret = armada_thermal_probe_syscon(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) priv->current_channel = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) priv->data->init(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) drvdata->type = SYSCON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) drvdata->data.priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) platform_set_drvdata(pdev, drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (irq == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* The overheat interrupt feature is not mandatory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ret = devm_request_threaded_irq(&pdev->dev, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) armada_overheat_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) armada_overheat_isr_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) 0, NULL, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dev_err(&pdev->dev, "Cannot request threaded IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * There is one channel for the IC and one per CPU (if any), each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * channel has one sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) for (sensor_id = 0; sensor_id <= priv->data->cpu_nr; sensor_id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) sensor = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) sizeof(struct armada_thermal_sensor),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /* Register the sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) sensor->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) sensor->id = sensor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) tz = devm_thermal_zone_of_sensor_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) sensor->id, sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) &of_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (IS_ERR(tz)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) dev_info(&pdev->dev, "Thermal sensor %d unavailable\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) sensor_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) devm_kfree(&pdev->dev, sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * The first channel that has a critical trip point registered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * in the DT will serve as interrupt source. Others possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * critical trip points will simply be ignored by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (irq > 0 && !priv->overheat_sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) armada_configure_overheat_int(priv, tz, sensor->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* Just complain if no overheat interrupt was set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (!priv->overheat_sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) dev_warn(&pdev->dev, "Overheat interrupt not available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static int armada_thermal_exit(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct armada_drvdata *drvdata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (drvdata->type == LEGACY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) thermal_zone_device_unregister(drvdata->data.tz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static struct platform_driver armada_thermal_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .probe = armada_thermal_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .remove = armada_thermal_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .name = "armada_thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .of_match_table = armada_thermal_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) module_platform_driver(armada_thermal_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) MODULE_DESCRIPTION("Marvell EBU Armada SoCs thermal driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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