Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Sonics Silicon Backplane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Bus scanning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 2006 Broadcom Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Licensed under the GNU/GPL. See COPYING for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "ssb_private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/ssb/ssb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/ssb/ssb_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <pcmcia/cistpl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <pcmcia/ds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) const char *ssb_core_name(u16 coreid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	switch (coreid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	case SSB_DEV_CHIPCOMMON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		return "ChipCommon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	case SSB_DEV_ILINE20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		return "ILine 20";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	case SSB_DEV_SDRAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		return "SDRAM";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	case SSB_DEV_PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		return "PCI";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	case SSB_DEV_MIPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		return "MIPS";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	case SSB_DEV_ETHERNET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		return "Fast Ethernet";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	case SSB_DEV_V90:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		return "V90";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	case SSB_DEV_USB11_HOSTDEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		return "USB 1.1 Hostdev";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	case SSB_DEV_ADSL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		return "ADSL";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	case SSB_DEV_ILINE100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		return "ILine 100";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	case SSB_DEV_IPSEC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		return "IPSEC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	case SSB_DEV_PCMCIA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		return "PCMCIA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	case SSB_DEV_INTERNAL_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		return "Internal Memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	case SSB_DEV_MEMC_SDRAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		return "MEMC SDRAM";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	case SSB_DEV_EXTIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		return "EXTIF";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	case SSB_DEV_80211:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		return "IEEE 802.11";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	case SSB_DEV_MIPS_3302:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		return "MIPS 3302";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	case SSB_DEV_USB11_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		return "USB 1.1 Host";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	case SSB_DEV_USB11_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		return "USB 1.1 Device";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	case SSB_DEV_USB20_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		return "USB 2.0 Host";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	case SSB_DEV_USB20_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		return "USB 2.0 Device";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	case SSB_DEV_SDIO_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		return "SDIO Host";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	case SSB_DEV_ROBOSWITCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		return "Roboswitch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	case SSB_DEV_PARA_ATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		return "PATA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	case SSB_DEV_SATA_XORDMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		return "SATA XOR-DMA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	case SSB_DEV_ETHERNET_GBIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		return "GBit Ethernet";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	case SSB_DEV_PCIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		return "PCI-E";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	case SSB_DEV_MIMO_PHY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		return "MIMO PHY";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	case SSB_DEV_SRAM_CTRLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		return "SRAM Controller";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	case SSB_DEV_MINI_MACPHY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		return "Mini MACPHY";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	case SSB_DEV_ARM_1176:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		return "ARM 1176";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	case SSB_DEV_ARM_7TDMI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		return "ARM 7TDMI";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	case SSB_DEV_ARM_CM3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		return "ARM Cortex M3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return "UNKNOWN";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static u16 pcidev_to_chipid(struct pci_dev *pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	u16 chipid_fallback = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	switch (pci_dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	case 0x4301:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		chipid_fallback = 0x4301;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	case 0x4305 ... 0x4307:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		chipid_fallback = 0x4307;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	case 0x4403:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		chipid_fallback = 0x4402;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	case 0x4610 ... 0x4615:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		chipid_fallback = 0x4610;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	case 0x4710 ... 0x4715:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		chipid_fallback = 0x4710;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	case 0x4320 ... 0x4325:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		chipid_fallback = 0x4309;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	case PCI_DEVICE_ID_BCM4401:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	case PCI_DEVICE_ID_BCM4401B0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	case PCI_DEVICE_ID_BCM4401B1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		chipid_fallback = 0x4401;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		dev_err(&pci_dev->dev, "PCI-ID not in fallback list\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	return chipid_fallback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static u8 chipid_to_nrcores(u16 chipid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	switch (chipid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	case 0x5365:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	case 0x4306:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		return 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	case 0x4310:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		return 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	case 0x4307:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	case 0x4301:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	case 0x4401:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	case 0x4402:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	case 0x4710:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	case 0x4610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	case 0x4704:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		pr_err("CHIPID not in nrcores fallback list\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		       u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	u32 lo, hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	switch (bus->bustype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	case SSB_BUSTYPE_SSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		offset += current_coreidx * SSB_CORE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	case SSB_BUSTYPE_PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	case SSB_BUSTYPE_PCMCIA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		if (offset >= 0x800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			ssb_pcmcia_switch_segment(bus, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			offset -= 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			ssb_pcmcia_switch_segment(bus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		lo = readw(bus->mmio + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		hi = readw(bus->mmio + offset + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		return lo | (hi << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	case SSB_BUSTYPE_SDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		offset += current_coreidx * SSB_CORE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return ssb_sdio_scan_read32(bus, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	return readl(bus->mmio + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int scan_switchcore(struct ssb_bus *bus, u8 coreidx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	switch (bus->bustype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	case SSB_BUSTYPE_SSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	case SSB_BUSTYPE_PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return ssb_pci_switch_coreidx(bus, coreidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	case SSB_BUSTYPE_PCMCIA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		return ssb_pcmcia_switch_coreidx(bus, coreidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	case SSB_BUSTYPE_SDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return ssb_sdio_scan_switch_coreidx(bus, coreidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) void ssb_iounmap(struct ssb_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	switch (bus->bustype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	case SSB_BUSTYPE_SSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	case SSB_BUSTYPE_PCMCIA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		iounmap(bus->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	case SSB_BUSTYPE_PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #ifdef CONFIG_SSB_PCIHOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		pci_iounmap(bus->host_pci, bus->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		WARN_ON(1); /* Can't reach this code. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	case SSB_BUSTYPE_SDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	bus->mmio = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	bus->mapped_device = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void __iomem *ssb_ioremap(struct ssb_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 				 unsigned long baseaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	void __iomem *mmio = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	switch (bus->bustype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	case SSB_BUSTYPE_SSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		/* Only map the first core for now. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	case SSB_BUSTYPE_PCMCIA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		mmio = ioremap(baseaddr, SSB_CORE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	case SSB_BUSTYPE_PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #ifdef CONFIG_SSB_PCIHOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		mmio = pci_iomap(bus->host_pci, 0, ~0UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		WARN_ON(1); /* Can't reach this code. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	case SSB_BUSTYPE_SDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		/* Nothing to ioremap in the SDIO case, just fake it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		mmio = (void __iomem *)baseaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int we_support_multiple_80211_cores(struct ssb_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	/* More than one 802.11 core is only supported by special chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	 * There are chips with two 802.11 cores, but with dangling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	 * pins on the second core. Be careful and reject them here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #ifdef CONFIG_SSB_PCIHOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (bus->bustype == SSB_BUSTYPE_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		    ((bus->host_pci->device == 0x4313) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		     (bus->host_pci->device == 0x431A) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		     (bus->host_pci->device == 0x4321) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		     (bus->host_pci->device == 0x4324)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #endif /* CONFIG_SSB_PCIHOST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int ssb_bus_scan(struct ssb_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		 unsigned long baseaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	int err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	u32 idhi, cc, rev, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	int dev_i, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct ssb_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	int nr_80211_cores = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	mmio = ssb_ioremap(bus, baseaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (!mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	bus->mmio = mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	err = scan_switchcore(bus, 0); /* Switch to first core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	idhi = scan_read32(bus, 0, SSB_IDHIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	cc = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	rev = (idhi & SSB_IDHIGH_RCLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	rev |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	bus->nr_devices = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (cc == SSB_DEV_CHIPCOMMON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		tmp = scan_read32(bus, 0, SSB_CHIPCO_CHIPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		bus->chip_id = (tmp & SSB_CHIPCO_IDMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		bus->chip_rev = (tmp & SSB_CHIPCO_REVMASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 				SSB_CHIPCO_REVSHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		bus->chip_package = (tmp & SSB_CHIPCO_PACKMASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 				    SSB_CHIPCO_PACKSHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		if (rev >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			bus->nr_devices = (tmp & SSB_CHIPCO_NRCORESMASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 					  SSB_CHIPCO_NRCORESSHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		tmp = scan_read32(bus, 0, SSB_CHIPCO_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		bus->chipco.capabilities = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		if (bus->bustype == SSB_BUSTYPE_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			bus->chip_id = pcidev_to_chipid(bus->host_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			bus->chip_rev = bus->host_pci->revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			bus->chip_package = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			bus->chip_id = 0x4710;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			bus->chip_rev = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 			bus->chip_package = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	pr_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		bus->chip_id, bus->chip_rev, bus->chip_package);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if (!bus->nr_devices)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		bus->nr_devices = chipid_to_nrcores(bus->chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		pr_err("More than %d ssb cores found (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		       SSB_MAX_NR_CORES, bus->nr_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (bus->bustype == SSB_BUSTYPE_SSB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		/* Now that we know the number of cores,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		 * remap the whole IO space for all cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		iounmap(mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		mmio = ioremap(baseaddr, SSB_CORE_SIZE * bus->nr_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		if (!mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		bus->mmio = mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	/* Fetch basic information about each core/device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	for (i = 0, dev_i = 0; i < bus->nr_devices; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		err = scan_switchcore(bus, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		dev = &(bus->devices[dev_i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		idhi = scan_read32(bus, i, SSB_IDHIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		dev->id.coreid = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		dev->id.revision = (idhi & SSB_IDHIGH_RCLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		dev->id.revision |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		dev->id.vendor = (idhi & SSB_IDHIGH_VC) >> SSB_IDHIGH_VC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		dev->core_index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		dev->bus = bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		dev->ops = bus->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		pr_debug("Core %d found: %s (cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 			 i, ssb_core_name(dev->id.coreid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			 dev->id.coreid, dev->id.revision, dev->id.vendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		switch (dev->id.coreid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		case SSB_DEV_80211:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 			nr_80211_cores++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			if (nr_80211_cores > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 				if (!we_support_multiple_80211_cores(bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 					pr_debug("Ignoring additional 802.11 core\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 					continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 				}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		case SSB_DEV_EXTIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #ifdef CONFIG_SSB_DRIVER_EXTIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			if (bus->extif.dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 				pr_warn("WARNING: Multiple EXTIFs found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 			bus->extif.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #endif /* CONFIG_SSB_DRIVER_EXTIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		case SSB_DEV_CHIPCOMMON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			if (bus->chipco.dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 				pr_warn("WARNING: Multiple ChipCommon found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 			bus->chipco.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		case SSB_DEV_MIPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		case SSB_DEV_MIPS_3302:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #ifdef CONFIG_SSB_DRIVER_MIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 			if (bus->mipscore.dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 				pr_warn("WARNING: Multiple MIPS cores found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 			bus->mipscore.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #endif /* CONFIG_SSB_DRIVER_MIPS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		case SSB_DEV_PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		case SSB_DEV_PCIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #ifdef CONFIG_SSB_DRIVER_PCICORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 			if (bus->bustype == SSB_BUSTYPE_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 				/* Ignore PCI cores on PCI-E cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 				 * Ignore PCI-E cores on PCI cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 				 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 				if (dev->id.coreid == SSB_DEV_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 					if (pci_is_pcie(bus->host_pci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 						continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 				} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 					if (!pci_is_pcie(bus->host_pci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 						continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 				}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 			if (bus->pcicore.dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 				pr_warn("WARNING: Multiple PCI(E) cores found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 			bus->pcicore.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #endif /* CONFIG_SSB_DRIVER_PCICORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		case SSB_DEV_ETHERNET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 			if (bus->bustype == SSB_BUSTYPE_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 				if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 				    (bus->host_pci->device & 0xFF00) == 0x4300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 					/* This is a dangling ethernet core on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 					 * wireless device. Ignore it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 					continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 				}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		dev_i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	bus->nr_devices = dev_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	ssb_iounmap(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }