^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Sonics Silicon Backplane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Subsystem core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2005, Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Licensed under the GNU/GPL. See COPYING for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "ssb_private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/ssb/ssb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/ssb/ssb_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/ssb/ssb_driver_gige.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mmc/sdio_func.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <pcmcia/cistpl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <pcmcia/ds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Temporary list of yet-to-be-attached buses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static LIST_HEAD(attach_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* List if running buses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static LIST_HEAD(buses);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Software ID counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static unsigned int next_busnumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* buses_mutes locks the two buslists and the next_busnumber.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Don't lock this directly, but use ssb_buses_[un]lock() below. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static DEFINE_MUTEX(buses_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* There are differences in the codeflow, if the bus is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * initialized from early boot, as various needed services
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * are not available early. This is a mechanism to delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * these initializations to after early boot has finished.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * It's also used to avoid mutex locking, as that's not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * available and needed early. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static bool ssb_is_early_boot = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void ssb_buses_lock(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void ssb_buses_unlock(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #ifdef CONFIG_SSB_PCIHOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct ssb_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ssb_buses_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) list_for_each_entry(bus, &buses, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (bus->bustype == SSB_BUSTYPE_PCI &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) bus->host_pci == pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) bus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ssb_buses_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif /* CONFIG_SSB_PCIHOST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #ifdef CONFIG_SSB_PCMCIAHOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct ssb_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ssb_buses_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) list_for_each_entry(bus, &buses, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) bus->host_pcmcia == pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) bus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ssb_buses_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #endif /* CONFIG_SSB_PCMCIAHOST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int ssb_for_each_bus_call(unsigned long data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int (*func)(struct ssb_bus *bus, unsigned long data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct ssb_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ssb_buses_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) list_for_each_entry(bus, &buses, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) res = func(bus, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (res >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ssb_buses_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ssb_buses_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct ssb_device *ssb_device_get(struct ssb_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) get_device(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void ssb_device_put(struct ssb_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) put_device(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int ssb_device_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct ssb_driver *ssb_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (dev->driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ssb_drv = drv_to_ssb_drv(dev->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (ssb_drv && ssb_drv->resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) err = ssb_drv->resume(ssb_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int ssb_device_suspend(struct device *dev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct ssb_driver *ssb_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (dev->driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ssb_drv = drv_to_ssb_drv(dev->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ssb_drv && ssb_drv->suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) err = ssb_drv->suspend(ssb_dev, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int ssb_bus_resume(struct ssb_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Reset HW state information in memory, so that HW is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * completely reinitialized. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) bus->mapped_device = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #ifdef CONFIG_SSB_DRIVER_PCICORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) bus->pcicore.setup_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) err = ssb_bus_powerup(bus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) err = ssb_pcmcia_hardware_setup(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ssb_bus_may_powerdown(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ssb_chipco_resume(&bus->chipco);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ssb_bus_may_powerdown(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) EXPORT_SYMBOL(ssb_bus_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int ssb_bus_suspend(struct ssb_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ssb_chipco_suspend(&bus->chipco);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) EXPORT_SYMBOL(ssb_bus_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #ifdef CONFIG_SSB_SPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /** ssb_devices_freeze - Freeze all devices on the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * After freezing no device driver will be handling a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * on this bus anymore. ssb_devices_thaw() must be called after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * a successful freeze to reactivate the devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * @bus: The bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * @ctx: Context structure. Pass this to ssb_devices_thaw().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct ssb_device *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct ssb_driver *sdrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) memset(ctx, 0, sizeof(*ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ctx->bus = bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) for (i = 0; i < bus->nr_devices; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) sdev = ssb_device_get(&bus->devices[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (!sdev->dev || !sdev->dev->driver ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) !device_is_registered(sdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ssb_device_put(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) sdrv = drv_to_ssb_drv(sdev->dev->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (WARN_ON(!sdrv->remove))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) sdrv->remove(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ctx->device_frozen[i] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /** ssb_devices_thaw - Unfreeze all devices on the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * This will re-attach the device drivers and re-init the devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @ctx: The context structure from ssb_devices_freeze()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int ssb_devices_thaw(struct ssb_freeze_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct ssb_bus *bus = ctx->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct ssb_device *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct ssb_driver *sdrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int err, result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) for (i = 0; i < bus->nr_devices; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!ctx->device_frozen[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) sdev = &bus->devices[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (WARN_ON(!sdev->dev || !sdev->dev->driver))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) sdrv = drv_to_ssb_drv(sdev->dev->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (WARN_ON(!sdrv || !sdrv->probe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) err = sdrv->probe(sdev, &sdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "Failed to thaw device %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_name(sdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) result = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ssb_device_put(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #endif /* CONFIG_SSB_SPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void ssb_device_shutdown(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct ssb_driver *ssb_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (!dev->driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ssb_drv = drv_to_ssb_drv(dev->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (ssb_drv && ssb_drv->shutdown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ssb_drv->shutdown(ssb_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int ssb_device_remove(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (ssb_drv && ssb_drv->remove)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ssb_drv->remove(ssb_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ssb_device_put(ssb_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int ssb_device_probe(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ssb_device_get(ssb_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ssb_drv && ssb_drv->probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ssb_device_put(ssb_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int ssb_match_devid(const struct ssb_device_id *tabid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) const struct ssb_device_id *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if ((tabid->vendor != devid->vendor) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) tabid->vendor != SSB_ANY_VENDOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if ((tabid->coreid != devid->coreid) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) tabid->coreid != SSB_ANY_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if ((tabid->revision != devid->revision) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) tabid->revision != SSB_ANY_REV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int ssb_bus_match(struct device *dev, struct device_driver *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) const struct ssb_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) for (id = ssb_drv->id_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) id->vendor || id->coreid || id->revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (ssb_match_devid(id, &ssb_dev->id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return 1; /* found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return add_uevent_var(env,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "MODALIAS=ssb:v%04Xid%04Xrev%02X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ssb_dev->id.vendor, ssb_dev->id.coreid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ssb_dev->id.revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define ssb_config_attr(attrib, field, format_string) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static ssize_t \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static DEVICE_ATTR_RO(attrib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ssb_config_attr(core_num, core_index, "%u\n")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ssb_config_attr(coreid, id.coreid, "0x%04x\n")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ssb_config_attr(vendor, id.vendor, "0x%04x\n")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ssb_config_attr(revision, id.revision, "%u\n")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ssb_config_attr(irq, irq, "%u\n")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) name_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return sprintf(buf, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static DEVICE_ATTR_RO(name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static struct attribute *ssb_device_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) &dev_attr_name.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) &dev_attr_core_num.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) &dev_attr_coreid.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) &dev_attr_vendor.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) &dev_attr_revision.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) &dev_attr_irq.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ATTRIBUTE_GROUPS(ssb_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static struct bus_type ssb_bustype = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .name = "ssb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .match = ssb_bus_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .probe = ssb_device_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .remove = ssb_device_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .shutdown = ssb_device_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .suspend = ssb_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .resume = ssb_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .uevent = ssb_device_uevent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .dev_groups = ssb_device_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static void ssb_buses_lock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* See the comment at the ssb_is_early_boot definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (!ssb_is_early_boot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mutex_lock(&buses_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static void ssb_buses_unlock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* See the comment at the ssb_is_early_boot definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (!ssb_is_early_boot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) mutex_unlock(&buses_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static void ssb_devices_unregister(struct ssb_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct ssb_device *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) for (i = bus->nr_devices - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) sdev = &(bus->devices[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (sdev->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) device_unregister(sdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #ifdef CONFIG_SSB_EMBEDDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (bus->bustype == SSB_BUSTYPE_SSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) platform_device_unregister(bus->watchdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) void ssb_bus_unregister(struct ssb_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) err = ssb_gpio_unregister(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (err == -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) pr_debug("Some GPIOs are still in use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) else if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pr_debug("Can not unregister GPIO driver: %i\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ssb_buses_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ssb_devices_unregister(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) list_del(&bus->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ssb_buses_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ssb_pcmcia_exit(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ssb_pci_exit(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ssb_iounmap(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) EXPORT_SYMBOL(ssb_bus_unregister);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static void ssb_release_dev(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct __ssb_dev_wrapper *devwrap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) kfree(devwrap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int ssb_devices_register(struct ssb_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct ssb_device *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct __ssb_dev_wrapper *devwrap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int i, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int dev_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) for (i = 0; i < bus->nr_devices; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) sdev = &(bus->devices[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* We don't register SSB-system devices to the kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * as the drivers for them are built into SSB. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) switch (sdev->id.coreid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case SSB_DEV_CHIPCOMMON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case SSB_DEV_PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) case SSB_DEV_PCIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) case SSB_DEV_PCMCIA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case SSB_DEV_MIPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) case SSB_DEV_MIPS_3302:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case SSB_DEV_EXTIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (!devwrap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) dev = &devwrap->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) devwrap->sdev = sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dev->release = ssb_release_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev->bus = &ssb_bustype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) switch (bus->bustype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) case SSB_BUSTYPE_PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #ifdef CONFIG_SSB_PCIHOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) sdev->irq = bus->host_pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dev->parent = &bus->host_pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) sdev->dma_dev = dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case SSB_BUSTYPE_PCMCIA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #ifdef CONFIG_SSB_PCMCIAHOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) sdev->irq = bus->host_pcmcia->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev->parent = &bus->host_pcmcia->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case SSB_BUSTYPE_SDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #ifdef CONFIG_SSB_SDIOHOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev->parent = &bus->host_sdio->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) case SSB_BUSTYPE_SSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dev->dma_mask = &dev->coherent_dma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) sdev->dma_dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) sdev->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) err = device_register(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) pr_err("Could not register %s\n", dev_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* Set dev to NULL to not unregister
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * dev on error unwinding. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) sdev->dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) put_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dev_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #ifdef CONFIG_SSB_DRIVER_MIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (bus->mipscore.pflash.present) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) err = platform_device_register(&ssb_pflash_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) pr_err("Error registering parallel flash\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #ifdef CONFIG_SSB_SFLASH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (bus->mipscore.sflash.present) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) err = platform_device_register(&ssb_sflash_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) pr_err("Error registering serial flash\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Unwind the already registered devices. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ssb_devices_unregister(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* Needs ssb_buses_lock() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static int ssb_attach_queued_buses(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct ssb_bus *bus, *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int drop_them_all = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) list_for_each_entry_safe(bus, n, &attach_queue, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (drop_them_all) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) list_del(&bus->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Can't init the PCIcore in ssb_bus_register(), as that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * is too early in boot for embedded systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * (no udelay() available). So do it here in attach stage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) err = ssb_bus_powerup(bus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ssb_pcicore_init(&bus->pcicore);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (bus->bustype == SSB_BUSTYPE_SSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ssb_watchdog_register(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) err = ssb_gpio_init(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (err == -ENOTSUPP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) pr_debug("GPIO driver not activated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) else if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) pr_debug("Error registering GPIO driver: %i\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ssb_bus_may_powerdown(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) err = ssb_devices_register(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) drop_them_all = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) list_del(&bus->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) list_move_tail(&bus->list, &buses);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static int ssb_fetch_invariants(struct ssb_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ssb_invariants_func_t get_invariants)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct ssb_init_invariants iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) memset(&iv, 0, sizeof(iv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) err = get_invariants(bus, &iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) bus->has_cardbus_slot = iv.has_cardbus_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static int __maybe_unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ssb_bus_register(struct ssb_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ssb_invariants_func_t get_invariants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) unsigned long baseaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) spin_lock_init(&bus->bar_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) INIT_LIST_HEAD(&bus->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #ifdef CONFIG_SSB_EMBEDDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) spin_lock_init(&bus->gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Powerup the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Init SDIO-host device (if any), before the scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) err = ssb_sdio_init(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) goto err_disable_xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ssb_buses_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) bus->busnumber = next_busnumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Scan for devices (cores) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) err = ssb_bus_scan(bus, baseaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) goto err_sdio_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Init PCI-host device (if any) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) err = ssb_pci_init(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Init PCMCIA-host device (if any) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) err = ssb_pcmcia_init(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) goto err_pci_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* Initialize basic system devices (if available) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) err = ssb_bus_powerup(bus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) goto err_pcmcia_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ssb_chipcommon_init(&bus->chipco);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ssb_extif_init(&bus->extif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ssb_mipscore_init(&bus->mipscore);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) err = ssb_fetch_invariants(bus, get_invariants);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ssb_bus_may_powerdown(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) goto err_pcmcia_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ssb_bus_may_powerdown(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* Queue it for attach.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * See the comment at the ssb_is_early_boot definition. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) list_add_tail(&bus->list, &attach_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (!ssb_is_early_boot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* This is not early boot, so we must attach the bus now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) err = ssb_attach_queued_buses();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) goto err_dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) next_busnumber++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ssb_buses_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) err_dequeue:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) list_del(&bus->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) err_pcmcia_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ssb_pcmcia_exit(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) err_pci_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ssb_pci_exit(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ssb_iounmap(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) err_sdio_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ssb_sdio_exit(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) err_disable_xtal:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ssb_buses_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #ifdef CONFIG_SSB_PCIHOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) int ssb_bus_pcibus_register(struct ssb_bus *bus, struct pci_dev *host_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) bus->bustype = SSB_BUSTYPE_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) bus->host_pci = host_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) bus->ops = &ssb_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dev_info(&host_pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) "Sonics Silicon Backplane found on PCI device %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) dev_name(&host_pci->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dev_err(&host_pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) "Failed to register PCI version of SSB with error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #endif /* CONFIG_SSB_PCIHOST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #ifdef CONFIG_SSB_PCMCIAHOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct pcmcia_device *pcmcia_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) unsigned long baseaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) bus->bustype = SSB_BUSTYPE_PCMCIA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) bus->host_pcmcia = pcmcia_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) bus->ops = &ssb_pcmcia_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dev_info(&pcmcia_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) "Sonics Silicon Backplane found on PCMCIA device %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) pcmcia_dev->devname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #endif /* CONFIG_SSB_PCMCIAHOST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #ifdef CONFIG_SSB_SDIOHOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) unsigned int quirks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) bus->bustype = SSB_BUSTYPE_SDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) bus->host_sdio = func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) bus->ops = &ssb_sdio_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) bus->quirks = quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dev_info(&func->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) "Sonics Silicon Backplane found on SDIO device %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) sdio_func_id(func));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) EXPORT_SYMBOL(ssb_bus_sdiobus_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #endif /* CONFIG_SSB_PCMCIAHOST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #ifdef CONFIG_SSB_HOST_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) int ssb_bus_host_soc_register(struct ssb_bus *bus, unsigned long baseaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) bus->bustype = SSB_BUSTYPE_SSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) bus->ops = &ssb_host_soc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) err = ssb_bus_register(bus, ssb_host_soc_get_invariants, baseaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) pr_info("Sonics Silicon Backplane found at address 0x%08lX\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) baseaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) drv->drv.name = drv->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) drv->drv.bus = &ssb_bustype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) drv->drv.owner = owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return driver_register(&drv->drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) EXPORT_SYMBOL(__ssb_driver_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) void ssb_driver_unregister(struct ssb_driver *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) driver_unregister(&drv->drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) EXPORT_SYMBOL(ssb_driver_unregister);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) void ssb_set_devtypedata(struct ssb_device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct ssb_bus *bus = dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct ssb_device *ent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) for (i = 0; i < bus->nr_devices; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ent = &(bus->devices[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (ent->id.vendor != dev->id.vendor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (ent->id.coreid != dev->id.coreid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ent->devtypedata = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) EXPORT_SYMBOL(ssb_set_devtypedata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static u32 clkfactor_f6_resolve(u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* map the magic values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) switch (v) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) case SSB_CHIPCO_CLK_F6_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) case SSB_CHIPCO_CLK_F6_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) case SSB_CHIPCO_CLK_F6_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) case SSB_CHIPCO_CLK_F6_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) case SSB_CHIPCO_CLK_F6_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) case SSB_CHIPCO_CLK_F6_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /* Calculate the speed the backplane would run at a given set of clockcontrol values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u32 n1, n2, clock, m1, m2, m3, mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) n1 = (n & SSB_CHIPCO_CLK_N1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) switch (plltype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (m & SSB_CHIPCO_CLK_T6_MMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return SSB_CHIPCO_CLK_T6_M1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return SSB_CHIPCO_CLK_T6_M0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) n1 = clkfactor_f6_resolve(n1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) n2 += SSB_CHIPCO_CLK_F5_BIAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) n1 += SSB_CHIPCO_CLK_T2_BIAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) n2 += SSB_CHIPCO_CLK_T2_BIAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) WARN_ON(!((n1 >= 2) && (n1 <= 7)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) WARN_ON(!((n2 >= 5) && (n2 <= 23)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return 100000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) switch (plltype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (!clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) m1 = (m & SSB_CHIPCO_CLK_M1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) switch (plltype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) m1 = clkfactor_f6_resolve(m1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if ((plltype == SSB_PLLTYPE_1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) (plltype == SSB_PLLTYPE_3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) m2 += SSB_CHIPCO_CLK_F5_BIAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) m2 = clkfactor_f6_resolve(m2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) m3 = clkfactor_f6_resolve(m3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) switch (mc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) case SSB_CHIPCO_CLK_MC_BYPASS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) case SSB_CHIPCO_CLK_MC_M1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return (clock / m1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) case SSB_CHIPCO_CLK_MC_M1M2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return (clock / (m1 * m2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) case SSB_CHIPCO_CLK_MC_M1M2M3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return (clock / (m1 * m2 * m3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) case SSB_CHIPCO_CLK_MC_M1M3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return (clock / (m1 * m3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) case SSB_PLLTYPE_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) m1 += SSB_CHIPCO_CLK_T2_BIAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) m3 += SSB_CHIPCO_CLK_T2_BIAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) WARN_ON(!((m1 >= 2) && (m1 <= 7)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) WARN_ON(!((m2 >= 3) && (m2 <= 10)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) WARN_ON(!((m3 >= 2) && (m3 <= 7)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) clock /= m1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) clock /= m2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) clock /= m3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* Get the current speed the backplane is running at */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) u32 ssb_clockspeed(struct ssb_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) u32 plltype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) u32 clkctl_n, clkctl_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return ssb_pmu_get_controlclock(&bus->chipco);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (ssb_extif_available(&bus->extif))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ssb_extif_get_clockcontrol(&bus->extif, &plltype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) &clkctl_n, &clkctl_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) else if (bus->chipco.dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) &clkctl_n, &clkctl_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (bus->chip_id == 0x5365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) rate = 100000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) rate /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) EXPORT_SYMBOL(ssb_clockspeed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* The REJECT bit seems to be different for Backplane rev 2.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) case SSB_IDLOW_SSBREV_22:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) case SSB_IDLOW_SSBREV_24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) case SSB_IDLOW_SSBREV_26:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return SSB_TMSLOW_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) case SSB_IDLOW_SSBREV_23:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return SSB_TMSLOW_REJECT_23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) case SSB_IDLOW_SSBREV_27: /* same here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return SSB_TMSLOW_REJECT; /* this is a guess */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) case SSB_IDLOW_SSBREV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) int ssb_device_is_enabled(struct ssb_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) u32 reject;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) reject = ssb_tmslow_reject_bitmask(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) val = ssb_read32(dev, SSB_TMSLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return (val == SSB_TMSLOW_CLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) EXPORT_SYMBOL(ssb_device_is_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static void ssb_flush_tmslow(struct ssb_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* Make _really_ sure the device has finished the TMSLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * register write transaction, as we risk running into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * a machine check exception otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * Do this by reading the register back to commit the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * PCI write and delay an additional usec for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * to react to the change. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ssb_read32(dev, SSB_TMSLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) ssb_device_disable(dev, core_specific_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ssb_write32(dev, SSB_TMSLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) SSB_TMSLOW_FGC | core_specific_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ssb_flush_tmslow(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /* Clear SERR if set. This is a hw bug workaround. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ssb_write32(dev, SSB_TMSHIGH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) val = ssb_read32(dev, SSB_IMSTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ssb_write32(dev, SSB_IMSTATE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) ssb_write32(dev, SSB_TMSLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) core_specific_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ssb_flush_tmslow(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) core_specific_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ssb_flush_tmslow(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) EXPORT_SYMBOL(ssb_device_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /* Wait for bitmask in a register to get set or cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * timeout is in units of ten-microseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) int timeout, int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) for (i = 0; i < timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) val = ssb_read32(dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if ((val & bitmask) == bitmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (!(val & bitmask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) dev_err(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) "Timeout waiting for bitmask %08X on register %04X to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) bitmask, reg, set ? "set" : "clear");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) u32 reject, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) reject = ssb_tmslow_reject_bitmask(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) val = ssb_read32(dev, SSB_IMSTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) val |= SSB_IMSTATE_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) ssb_write32(dev, SSB_IMSTATE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ssb_write32(dev, SSB_TMSLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) reject | SSB_TMSLOW_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) core_specific_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) ssb_flush_tmslow(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) val = ssb_read32(dev, SSB_IMSTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) val &= ~SSB_IMSTATE_REJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) ssb_write32(dev, SSB_IMSTATE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ssb_write32(dev, SSB_TMSLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) reject | SSB_TMSLOW_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) core_specific_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ssb_flush_tmslow(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) EXPORT_SYMBOL(ssb_device_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /* Some chipsets need routing known for PCIe and 64-bit DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) u16 chip_id = dev->bus->chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (dev->id.coreid == SSB_DEV_80211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return (chip_id == 0x4322 || chip_id == 43221 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) chip_id == 43231 || chip_id == 43222);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) u32 ssb_dma_translation(struct ssb_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) switch (dev->bus->bustype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) case SSB_BUSTYPE_SSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) case SSB_BUSTYPE_PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (pci_is_pcie(dev->bus->host_pci) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return SSB_PCIE_DMA_H32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (ssb_dma_translation_special_bit(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return SSB_PCIE_DMA_H32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return SSB_PCI_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) __ssb_dma_not_implemented(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) EXPORT_SYMBOL(ssb_dma_translation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) int ssb_bus_may_powerdown(struct ssb_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct ssb_chipcommon *cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /* On buses where more than one core may be working
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * at a time, we must not powerdown stuff if there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * still cores that may want to run. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (bus->bustype == SSB_BUSTYPE_SSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) cc = &bus->chipco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (!cc->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (cc->dev->id.revision < 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) bus->powered_up = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) pr_err("Bus powerdown failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) EXPORT_SYMBOL(ssb_bus_may_powerdown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) enum ssb_clkmode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) bus->powered_up = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) ssb_chipco_set_clockmode(&bus->chipco, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) pr_err("Bus powerup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) EXPORT_SYMBOL(ssb_bus_powerup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static void ssb_broadcast_value(struct ssb_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) u32 address, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #ifdef CONFIG_SSB_DRIVER_PCICORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* This is used for both, PCI and ChipCommon core, so be careful. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) void ssb_commit_settings(struct ssb_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) struct ssb_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #ifdef CONFIG_SSB_DRIVER_PCICORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) dev = bus->chipco.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (WARN_ON(!dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* This forces an update of the cached registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ssb_broadcast_value(dev, 0xFD8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) EXPORT_SYMBOL(ssb_commit_settings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) u32 ssb_admatch_base(u32 adm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) u32 base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) switch (adm & SSB_ADM_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) case SSB_ADM_TYPE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) base = (adm & SSB_ADM_BASE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) case SSB_ADM_TYPE1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) base = (adm & SSB_ADM_BASE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) case SSB_ADM_TYPE2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) base = (adm & SSB_ADM_BASE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) EXPORT_SYMBOL(ssb_admatch_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) u32 ssb_admatch_size(u32 adm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) u32 size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) switch (adm & SSB_ADM_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) case SSB_ADM_TYPE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) case SSB_ADM_TYPE1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) case SSB_ADM_TYPE2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) size = (1 << (size + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) EXPORT_SYMBOL(ssb_admatch_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static int __init ssb_modinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* See the comment at the ssb_is_early_boot definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ssb_is_early_boot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) err = bus_register(&ssb_bustype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /* Maybe we already registered some buses at early boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * Check for this and attach them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ssb_buses_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) err = ssb_attach_queued_buses();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) ssb_buses_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) bus_unregister(&ssb_bustype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) err = b43_pci_ssb_bridge_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) pr_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) /* don't fail SSB init because of this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) err = ssb_host_pcmcia_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) pr_err("PCMCIA host initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) /* don't fail SSB init because of this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) err = ssb_gige_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) pr_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /* don't fail SSB init because of this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* ssb must be initialized after PCI but before the ssb drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * That means we must use some initcall between subsys_initcall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) * and device_initcall. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) fs_initcall(ssb_modinit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) static void __exit ssb_modexit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) ssb_gige_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ssb_host_pcmcia_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) b43_pci_ssb_bridge_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) bus_unregister(&ssb_bustype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) module_exit(ssb_modexit)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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