Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Sonics Silicon Backplane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Embedded systems support code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2005-2008, Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2006-2008, Michael Buesch <m@bues.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Licensed under the GNU/GPL. See COPYING for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "ssb_private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/ssb/ssb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/ssb/ssb_embedded.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/ssb/ssb_driver_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/ssb/ssb_driver_gige.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) int ssb_watchdog_timer_set(struct ssb_bus *bus, u32 ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	if (ssb_chipco_available(&bus->chipco)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		ssb_chipco_watchdog_timer_set(&bus->chipco, ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	if (ssb_extif_available(&bus->extif)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		ssb_extif_watchdog_timer_set(&bus->extif, ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) EXPORT_SYMBOL(ssb_watchdog_timer_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) int ssb_watchdog_register(struct ssb_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct bcm47xx_wdt wdt = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	if (ssb_chipco_available(&bus->chipco)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		wdt.driver_data = &bus->chipco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		wdt.max_timer_ms = bus->chipco.max_timer_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	} else if (ssb_extif_available(&bus->extif)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		wdt.driver_data = &bus->extif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 					     bus->busnumber, &wdt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 					     sizeof(wdt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	if (IS_ERR(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		pr_debug("can not register watchdog device, err: %li\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 			 PTR_ERR(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		return PTR_ERR(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	bus->watchdog = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	spin_lock_irqsave(&bus->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (ssb_chipco_available(&bus->chipco))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		res = ssb_chipco_gpio_in(&bus->chipco, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	else if (ssb_extif_available(&bus->extif))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		res = ssb_extif_gpio_in(&bus->extif, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	spin_unlock_irqrestore(&bus->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) EXPORT_SYMBOL(ssb_gpio_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) u32 ssb_gpio_out(struct ssb_bus *bus, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	spin_lock_irqsave(&bus->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (ssb_chipco_available(&bus->chipco))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		res = ssb_chipco_gpio_out(&bus->chipco, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	else if (ssb_extif_available(&bus->extif))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		res = ssb_extif_gpio_out(&bus->extif, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	spin_unlock_irqrestore(&bus->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) EXPORT_SYMBOL(ssb_gpio_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 ssb_gpio_outen(struct ssb_bus *bus, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	spin_lock_irqsave(&bus->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (ssb_chipco_available(&bus->chipco))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		res = ssb_chipco_gpio_outen(&bus->chipco, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	else if (ssb_extif_available(&bus->extif))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		res = ssb_extif_gpio_outen(&bus->extif, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	spin_unlock_irqrestore(&bus->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) EXPORT_SYMBOL(ssb_gpio_outen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 ssb_gpio_control(struct ssb_bus *bus, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	spin_lock_irqsave(&bus->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (ssb_chipco_available(&bus->chipco))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		res = ssb_chipco_gpio_control(&bus->chipco, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	spin_unlock_irqrestore(&bus->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) EXPORT_SYMBOL(ssb_gpio_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 ssb_gpio_intmask(struct ssb_bus *bus, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	spin_lock_irqsave(&bus->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (ssb_chipco_available(&bus->chipco))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		res = ssb_chipco_gpio_intmask(&bus->chipco, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	else if (ssb_extif_available(&bus->extif))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		res = ssb_extif_gpio_intmask(&bus->extif, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	spin_unlock_irqrestore(&bus->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) EXPORT_SYMBOL(ssb_gpio_intmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 ssb_gpio_polarity(struct ssb_bus *bus, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	spin_lock_irqsave(&bus->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (ssb_chipco_available(&bus->chipco))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		res = ssb_chipco_gpio_polarity(&bus->chipco, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	else if (ssb_extif_available(&bus->extif))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		res = ssb_extif_gpio_polarity(&bus->extif, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	spin_unlock_irqrestore(&bus->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) EXPORT_SYMBOL(ssb_gpio_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #ifdef CONFIG_SSB_DRIVER_GIGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int gige_pci_init_callback(struct ssb_bus *bus, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct pci_dev *pdev = (struct pci_dev *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct ssb_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	for (i = 0; i < bus->nr_devices; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		dev = &(bus->devices[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		if (!dev->dev ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		    !dev->dev->driver ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		    !device_is_registered(dev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		res = ssb_gige_pcibios_plat_dev_init(dev, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		if (res >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif /* CONFIG_SSB_DRIVER_GIGE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int ssb_pcibios_plat_dev_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	err = ssb_pcicore_plat_dev_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #ifdef CONFIG_SSB_DRIVER_GIGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	err = ssb_for_each_bus_call((unsigned long)dev, gige_pci_init_callback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (err >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/* This is not a PCI device on any SSB device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #ifdef CONFIG_SSB_DRIVER_GIGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int gige_map_irq_callback(struct ssb_bus *bus, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	const struct pci_dev *pdev = (const struct pci_dev *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	struct ssb_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	for (i = 0; i < bus->nr_devices; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		dev = &(bus->devices[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		if (!dev->dev ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		    !dev->dev->driver ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		    !device_is_registered(dev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		res = ssb_gige_map_irq(dev, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		if (res >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #endif /* CONFIG_SSB_DRIVER_GIGE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/* Check if this PCI device is a device on a SSB bus or device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 * and return the IRQ number for it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	res = ssb_pcicore_pcibios_map_irq(dev, slot, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (res >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #ifdef CONFIG_SSB_DRIVER_GIGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	res = ssb_for_each_bus_call((unsigned long)dev, gige_map_irq_callback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (res >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/* This is not a PCI device on any SSB device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }