^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Sonics Silicon Backplane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Broadcom Gigabit Ethernet core driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2008, Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2008, Michael Buesch <m@bues.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Licensed under the GNU/GPL. See COPYING for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ssb/ssb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ssb/ssb_driver_gige.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MODULE_AUTHOR("Michael Buesch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const struct ssb_device_id ssb_gige_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return ssb_read8(dev->dev, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return ssb_read16(dev->dev, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return ssb_read32(dev->dev, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static inline void gige_write8(struct ssb_gige *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u16 offset, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ssb_write8(dev->dev, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static inline void gige_write16(struct ssb_gige *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u16 offset, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ssb_write16(dev->dev, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline void gige_write32(struct ssb_gige *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u16 offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ssb_write32(dev->dev, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) BUG_ON(offset >= 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return gige_read8(dev, SSB_GIGE_PCICFG + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) BUG_ON(offset >= 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return gige_read16(dev, SSB_GIGE_PCICFG + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) BUG_ON(offset >= 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return gige_read32(dev, SSB_GIGE_PCICFG + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void gige_pcicfg_write8(struct ssb_gige *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int offset, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) BUG_ON(offset >= 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) void gige_pcicfg_write16(struct ssb_gige *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int offset, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) BUG_ON(offset >= 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) void gige_pcicfg_write32(struct ssb_gige *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) BUG_ON(offset >= 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int reg, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (reg >= 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *val = gige_pcicfg_read8(dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *val = gige_pcicfg_read16(dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) *val = gige_pcicfg_read32(dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int reg, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (reg >= 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) gige_pcicfg_write8(dev, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) gige_pcicfg_write16(dev, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) gige_pcicfg_write32(dev, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int ssb_gige_probe(struct ssb_device *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) const struct ssb_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct ssb_gige *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 base, tmslow, tmshigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev = kzalloc(sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev->dev = sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) spin_lock_init(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dev->pci_controller.pci_ops = &dev->pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev->pci_controller.io_resource = &dev->io_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dev->pci_controller.mem_resource = &dev->mem_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev->pci_controller.io_map_base = 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dev->pci_ops.read = ssb_gige_pci_read_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dev->pci_ops.write = ssb_gige_pci_write_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev->io_resource.start = 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev->io_resource.end = 0x8FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (!ssb_device_is_enabled(sdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ssb_device_enable(sdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Setup BAR0. This is a 64k MMIO region. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev->mem_resource.start = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dev->mem_resource.end = base + 0x10000 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Enable the memory region. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) gige_pcicfg_write16(dev, PCI_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) gige_pcicfg_read16(dev, PCI_COMMAND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) | PCI_COMMAND_MEMORY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Write flushing is controlled by the Flush Status Control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * We want to flush every register write with a timeout and we want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * to disable the IRQ mask while flushing to avoid concurrency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * Note that automatic write flushing does _not_ work from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * an IRQ handler. The driver must flush manually by reading a register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Check if we have an RGMII or GMII PHY-bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * On RGMII do not bypass the DLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) tmslow = ssb_read32(sdev, SSB_TMSLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dev->has_rgmii = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev->has_rgmii = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) tmslow |= SSB_GIGE_TMSLOW_DLLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ssb_write32(sdev, SSB_TMSLOW, tmslow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ssb_set_drvdata(sdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) register_pci_controller(&dev->pci_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!pdev->resource[0].name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return (strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) EXPORT_SYMBOL(pdev_is_ssb_gige_core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct ssb_gige *dev = ssb_get_drvdata(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (pdev->bus->ops != &dev->pci_ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* The PCI device is not on this SSB GigE bridge device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Fixup the PCI resources. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) res = &(pdev->resource[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) res->name = dev->mem_resource.name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) res->start = dev->mem_resource.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) res->end = dev->mem_resource.end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Fixup interrupt lines. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) pdev->irq = ssb_mips_irq(sdev) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int ssb_gige_map_irq(struct ssb_device *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) const struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct ssb_gige *dev = ssb_get_drvdata(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (pdev->bus->ops != &dev->pci_ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* The PCI device is not on this SSB GigE bridge device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return ssb_mips_irq(sdev) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct ssb_driver ssb_gige_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .name = "BCM-GigE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .id_table = ssb_gige_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .probe = ssb_gige_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int ssb_gige_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return ssb_driver_register(&ssb_gige_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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