^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Sonics Silicon Backplane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Broadcom EXTIF core driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2005, Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Licensed under the GNU/GPL. See COPYING for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "ssb_private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static inline u32 extif_read32(struct ssb_extif *extif, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) return ssb_read32(extif->dev, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static inline void extif_write32(struct ssb_extif *extif, u16 offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ssb_write32(extif->dev, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static inline u32 extif_write32_masked(struct ssb_extif *extif, u16 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) value &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) value |= extif_read32(extif, offset) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) extif_write32(extif, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #ifdef CONFIG_SSB_SERIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static bool serial_exists(u8 *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 save_mcr, msr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) save_mcr = regs[UART_MCR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) regs[UART_MCR] = (UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_RTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) msr = regs[UART_MSR] & (UART_MSR_DCD | UART_MSR_RI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) | UART_MSR_CTS | UART_MSR_DSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) regs[UART_MCR] = save_mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return (msr == (UART_MSR_DCD | UART_MSR_CTS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int ssb_extif_serial_init(struct ssb_extif *extif, struct ssb_serial_port *ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 i, nr_ports = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Disable GPIO interrupt initially */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) extif_write32(extif, SSB_EXTIF_GPIO_INTPOL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) extif_write32(extif, SSB_EXTIF_GPIO_INTMASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void __iomem *uart_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) uart_regs = ioremap(SSB_EUART, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (uart_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) uart_regs += (i * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (serial_exists(uart_regs) && ports) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extif_write32(extif, SSB_EXTIF_GPIO_INTMASK, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) nr_ports++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ports[i].regs = uart_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ports[i].irq = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ports[i].baud_base = 13500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ports[i].reg_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) iounmap(uart_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return nr_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #endif /* CONFIG_SSB_SERIAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Initialize extif so we can get to the LEDs and external UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) extif_write32(extif, SSB_EXTIF_PROG_CFG, SSB_EXTCFG_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Set timing for the flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) tmp |= DIV_ROUND_UP(120, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Set programmable interface timing for external uart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) tmp |= DIV_ROUND_UP(120, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 *pll_type, u32 *n, u32 *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *pll_type = SSB_PLLTYPE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *n = extif_read32(extif, SSB_EXTIF_CLOCK_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return ssb_extif_watchdog_timer_set(extif, ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ticks = ssb_extif_watchdog_timer_set(extif, ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void ssb_extif_init(struct ssb_extif *extif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (!extif->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return; /* We don't have a Extif core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) spin_lock_init(&extif->gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return extif_read32(extif, SSB_EXTIF_GPIO_IN) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) spin_lock_irqsave(&extif->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) spin_unlock_irqrestore(&extif->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) spin_lock_irqsave(&extif->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) spin_unlock_irqrestore(&extif->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) spin_lock_irqsave(&extif->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) spin_unlock_irqrestore(&extif->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) spin_lock_irqsave(&extif->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) spin_unlock_irqrestore(&extif->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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