^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Sonics Silicon Backplane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ChipCommon serial flash interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Licensed under the GNU/GPL. See COPYING for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "ssb_private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/ssb/ssb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) static struct resource ssb_sflash_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) .name = "ssb_sflash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) .start = SSB_FLASH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) .end = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct platform_device ssb_sflash_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .name = "ssb_sflash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .resource = &ssb_sflash_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct ssb_sflash_tbl_e {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 blocksize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u16 numblocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { "M25P20", 0x11, 0x10000, 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { "M25P40", 0x12, 0x10000, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { "M25P16", 0x14, 0x10000, 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { "M25P32", 0x15, 0x10000, 64, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { "M25P64", 0x16, 0x10000, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { "M25FL128", 0x17, 0x10000, 256, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { "SST25WF512", 1, 0x1000, 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { "SST25VF512", 0x48, 0x1000, 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { "SST25WF010", 2, 0x1000, 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { "SST25VF010", 0x49, 0x1000, 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { "SST25WF020", 3, 0x1000, 64, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { "SST25VF020", 0x43, 0x1000, 64, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { "SST25WF040", 4, 0x1000, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { "SST25VF040", 0x44, 0x1000, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { "SST25VF040B", 0x8d, 0x1000, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { "SST25WF080", 5, 0x1000, 256, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { "SST25VF080B", 0x8e, 0x1000, 256, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { "SST25VF016", 0x41, 0x1000, 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { "SST25VF032", 0x4a, 0x1000, 1024, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { "SST25VF064", 0x4b, 0x1000, 2048, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { "AT45DB011", 0xc, 256, 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { "AT45DB021", 0x14, 256, 1024, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { "AT45DB041", 0x1c, 256, 2048, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { "AT45DB081", 0x24, 256, 4096, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { "AT45DB161", 0x2c, 512, 4096, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { "AT45DB321", 0x34, 512, 8192, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { "AT45DB642", 0x3c, 1024, 8192, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void ssb_sflash_cmd(struct ssb_chipcommon *cc, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) chipco_write32(cc, SSB_CHIPCO_FLASHCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SSB_CHIPCO_FLASHCTL_START | opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) for (i = 0; i < 1000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (!(chipco_read32(cc, SSB_CHIPCO_FLASHCTL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SSB_CHIPCO_FLASHCTL_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dev_err(cc->dev->dev, "SFLASH control command failed (timeout)!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Initialize serial flash access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int ssb_sflash_init(struct ssb_chipcommon *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct ssb_sflash *sflash = &cc->dev->bus->mipscore.sflash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) const struct ssb_sflash_tbl_e *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 id, id2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case SSB_CHIPCO_FLASHT_STSER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_DP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) id2 = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case 0xbf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) for (e = ssb_sflash_sst_tbl; e->name; e++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (e->id == id2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case 0x13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) for (e = ssb_sflash_st_tbl; e->name; e++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (e->id == id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (!e->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pr_err("Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) id, id2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case SSB_CHIPCO_FLASHT_ATSER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA) & 0x3c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) for (e = ssb_sflash_at_tbl; e->name; e++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (e->id == id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (!e->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pr_err("Unsupported Atmel serial flash (id: 0x%X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) pr_err("Unsupported flash type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) sflash->window = SSB_FLASH2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) sflash->blocksize = e->blocksize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) sflash->numblocks = e->numblocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) sflash->size = sflash->blocksize * sflash->numblocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) sflash->present = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pr_info("Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) e->name, sflash->size / 1024, e->blocksize, e->numblocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Prepare platform device, but don't register it yet. It's too early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * malloc (required by device_private_init) is not available yet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ssb_sflash_dev.resource[0].end = ssb_sflash_dev.resource[0].start +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) sflash->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ssb_sflash_dev.dev.platform_data = sflash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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