^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Sonics Silicon Backplane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Broadcom ChipCommon core driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2005, Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Licensed under the GNU/GPL. See COPYING for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "ssb_private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ssb/ssb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ssb/ssb_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/bcm47xx_wdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Clock sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) enum ssb_clksrc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* PCI clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) SSB_CHIPCO_CLKSRC_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Crystal slow clock oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) SSB_CHIPCO_CLKSRC_XTALOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Low power oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) SSB_CHIPCO_CLKSRC_LOPWROS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) value &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) value |= chipco_read32(cc, offset) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) chipco_write32(cc, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum ssb_clkmode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct ssb_device *ccdev = cc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct ssb_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (!ccdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) bus = ccdev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* We support SLOW only on 6..9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) mode = SSB_CLKMODE_DYNAMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return; /* PMU controls clockmode, separated function needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) WARN_ON(ccdev->id.revision >= 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* chipcommon cores prior to rev6 don't support dynamic clock control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (ccdev->id.revision < 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* ChipCommon cores rev10+ need testing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (ccdev->id.revision >= 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case SSB_CLKMODE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (ccdev->id.revision < 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) SSB_CHIPCO_SYSCLKCTL_FORCEHT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* udelay(150); TODO: not available in early init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case SSB_CLKMODE_DYNAMIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (ccdev->id.revision < 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* For dynamic control, we have to release our xtal_pu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * "force on" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Get the Slow Clock Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct ssb_bus *bus = cc->dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (cc->dev->id.revision < 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (bus->bustype == SSB_BUSTYPE_SSB ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) bus->bustype == SSB_BUSTYPE_PCMCIA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return SSB_CHIPCO_CLKSRC_XTALOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (bus->bustype == SSB_BUSTYPE_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (tmp & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return SSB_CHIPCO_CLKSRC_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return SSB_CHIPCO_CLKSRC_XTALOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (cc->dev->id.revision < 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) tmp &= 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (tmp == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return SSB_CHIPCO_CLKSRC_LOPWROS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (tmp == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return SSB_CHIPCO_CLKSRC_XTALOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (tmp == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return SSB_CHIPCO_CLKSRC_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return SSB_CHIPCO_CLKSRC_XTALOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) enum ssb_clksrc clocksrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int divisor = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) clocksrc = chipco_pctl_get_slowclksrc(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (cc->dev->id.revision < 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) switch (clocksrc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case SSB_CHIPCO_CLKSRC_PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) divisor = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) case SSB_CHIPCO_CLKSRC_XTALOS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) divisor = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) } else if (cc->dev->id.revision < 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) switch (clocksrc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case SSB_CHIPCO_CLKSRC_LOPWROS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) case SSB_CHIPCO_CLKSRC_XTALOS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case SSB_CHIPCO_CLKSRC_PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) divisor = (tmp >> 16) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) divisor *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) divisor = (tmp >> 16) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) divisor *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) switch (clocksrc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case SSB_CHIPCO_CLKSRC_LOPWROS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (get_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) limit = 43000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) limit = 25000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case SSB_CHIPCO_CLKSRC_XTALOS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (get_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) limit = 20200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) limit = 19800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) case SSB_CHIPCO_CLKSRC_PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (get_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) limit = 34000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) limit = 25000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) limit /= divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct ssb_bus *bus = cc->dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (bus->chip_id == 0x4321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (bus->chip_rev == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) else if (bus->chip_rev == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (cc->dev->id.revision >= 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Set Idle Power clock rate to 1Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 0x0000FFFF) | 0x00040000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int maxfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) (maxfreq * 150 + 999999) / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) (maxfreq * 15 + 999999) / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* https://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct ssb_bus *bus = cc->dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) switch (bus->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case 0x4312:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case 0x4322:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case 0x4328:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 7000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case 0x4325:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* TODO: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 15000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* https://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct ssb_bus *bus = cc->dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int minfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 pll_on_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (bus->bustype != SSB_BUSTYPE_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) minfreq = chipco_pctl_clockfreqlimit(cc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) WARN_ON(tmp & ~0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) cc->fast_pwrup_delay = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ssb_pmu_get_alp_clock(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 20000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (cc->dev->id.revision < 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) nb = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) nb = (cc->dev->id.revision >= 37) ? 32 : 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) nb = 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (nb == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return (1 << nb) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return ssb_chipco_watchdog_timer_set(cc, ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ticks / cc->ticks_per_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct ssb_bus *bus = cc->dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* based on 32KHz ILP clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (cc->dev->id.revision < 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return ssb_clockspeed(bus) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return ssb_chipco_alp_clock(cc) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) void ssb_chipcommon_init(struct ssb_chipcommon *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (!cc->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return; /* We don't have a ChipCommon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) spin_lock_init(&cc->gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (cc->dev->id.revision >= 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dev_dbg(cc->dev->dev, "chipcommon status is 0x%x\n", cc->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (cc->dev->id.revision >= 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ssb_pmu_init(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) chipco_powercontrol_init(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) calc_fast_powerup_delay(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) void ssb_chipco_suspend(struct ssb_chipcommon *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (!cc->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) void ssb_chipco_resume(struct ssb_chipcommon *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (!cc->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) chipco_powercontrol_init(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Get the processor clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 *plltype, u32 *n, u32 *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) switch (*plltype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case SSB_PLLTYPE_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case SSB_PLLTYPE_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case SSB_PLLTYPE_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case SSB_PLLTYPE_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case SSB_PLLTYPE_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* 5350 uses m2 to control mips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Get the bus clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 *plltype, u32 *n, u32 *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) switch (*plltype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (cc->dev->bus->chip_id != 0x5365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned long ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct ssb_device *dev = cc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct ssb_bus *bus = dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* set register for external IO to control LED. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) tmp |= DIV_ROUND_UP(240, ns); /* Waitcount-0 = 240ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Set timing for the flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120nS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if ((bus->chip_id == 0x5365) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) (dev->id.revision < 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if ((bus->chip_id == 0x5365) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) (dev->id.revision < 9) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (bus->chip_id == 0x5350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Enable EXTIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u32 maxt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) enum ssb_clkmode clkmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) maxt = ssb_chipco_watchdog_get_max_timer(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (ticks == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ticks = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) else if (ticks > maxt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ticks = maxt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ssb_chipco_set_clockmode(cc, clkmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (ticks > maxt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ticks = maxt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* instant NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) spin_lock_irqsave(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) spin_unlock_irqrestore(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) spin_lock_irqsave(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) spin_unlock_irqrestore(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) spin_lock_irqsave(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) spin_unlock_irqrestore(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) EXPORT_SYMBOL(ssb_chipco_gpio_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) spin_lock_irqsave(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) spin_unlock_irqrestore(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) spin_lock_irqsave(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) spin_unlock_irqrestore(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (cc->dev->id.revision < 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) spin_lock_irqsave(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) spin_unlock_irqrestore(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (cc->dev->id.revision < 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) spin_lock_irqsave(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) spin_unlock_irqrestore(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #ifdef CONFIG_SSB_SERIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct ssb_serial_port *ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct ssb_bus *bus = cc->dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int nr_ports = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u32 plltype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u32 baud_base, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u32 i, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) unsigned int ccrev = cc->dev->id.revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) irq = ssb_mips_irq(cc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (plltype == SSB_PLLTYPE_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* PLL clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) baud_base = ssb_calc_clock_rate(plltype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (ccrev == 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* BCM5354 uses constant 25MHz clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) baud_base = 25000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) div = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* Set the override bit so we don't divide it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) chipco_write32(cc, SSB_CHIPCO_CORECTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) chipco_read32(cc, SSB_CHIPCO_CORECTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) | SSB_CHIPCO_CORECTL_UARTCLK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) } else if ((ccrev >= 11) && (ccrev != 15)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) baud_base = ssb_chipco_alp_clock(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (ccrev >= 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Turn off UART clock before switching clocksource. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) chipco_write32(cc, SSB_CHIPCO_CORECTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) chipco_read32(cc, SSB_CHIPCO_CORECTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) & ~SSB_CHIPCO_CORECTL_UARTCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Set the override bit so we don't divide it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) chipco_write32(cc, SSB_CHIPCO_CORECTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) chipco_read32(cc, SSB_CHIPCO_CORECTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) | SSB_CHIPCO_CORECTL_UARTCLK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (ccrev >= 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Re-enable the UART clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) chipco_write32(cc, SSB_CHIPCO_CORECTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) chipco_read32(cc, SSB_CHIPCO_CORECTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) | SSB_CHIPCO_CORECTL_UARTCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) } else if (ccrev >= 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Internal backplane clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) baud_base = ssb_clockspeed(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) & SSB_CHIPCO_CLKDIV_UART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* Fixed internal backplane clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) baud_base = 88000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) div = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Clock source depends on strapping if UartClkOverride is unset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if ((ccrev > 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) SSB_CHIPCO_CAP_UARTCLK_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* Internal divided backplane clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) baud_base /= div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* Assume external clock of 1.8432 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) baud_base = 1843200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* Determine the registers of the UARTs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) for (i = 0; i < n; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) void __iomem *cc_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) void __iomem *uart_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Offset changed at after rev 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (ccrev == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) uart_regs += (i * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) uart_regs += (i * 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) nr_ports++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ports[i].regs = uart_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ports[i].irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ports[i].baud_base = baud_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ports[i].reg_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return nr_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #endif /* CONFIG_SSB_SERIAL */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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