^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (master mode only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009 - 2015 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/firmware/xlnx-zynqmp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spi/spi-mem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Generic QSPI register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GQSPI_CONFIG_OFST 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GQSPI_ISR_OFST 0x00000104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GQSPI_IDR_OFST 0x0000010C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GQSPI_IER_OFST 0x00000108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GQSPI_IMASK_OFST 0x00000110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GQSPI_EN_OFST 0x00000114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GQSPI_TXD_OFST 0x0000011C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GQSPI_RXD_OFST 0x00000120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GQSPI_TX_THRESHOLD_OFST 0x00000128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GQSPI_RX_THRESHOLD_OFST 0x0000012C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GQSPI_LPBK_DLY_ADJ_OFST 0x00000138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GQSPI_GEN_FIFO_OFST 0x00000140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GQSPI_SEL_OFST 0x00000144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GQSPI_GF_THRESHOLD_OFST 0x00000150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GQSPI_FIFO_CTRL_OFST 0x0000014C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GQSPI_QSPIDMA_DST_CTRL_OFST 0x0000080C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GQSPI_QSPIDMA_DST_SIZE_OFST 0x00000804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GQSPI_QSPIDMA_DST_STS_OFST 0x00000808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GQSPI_QSPIDMA_DST_I_STS_OFST 0x00000814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GQSPI_QSPIDMA_DST_I_EN_OFST 0x00000818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GQSPI_QSPIDMA_DST_I_DIS_OFST 0x0000081C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x00000820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* GQSPI register bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GQSPI_SEL_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GQSPI_EN_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GQSPI_ISR_WR_TO_CLR_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GQSPI_IDR_ALL_MASK 0x00000FBE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GQSPI_CFG_MODE_EN_MASK 0xC0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GQSPI_CFG_GEN_FIFO_START_MODE_MASK 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GQSPI_CFG_ENDIAN_MASK 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GQSPI_CFG_EN_POLL_TO_MASK 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GQSPI_CFG_WP_HOLD_MASK 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GQSPI_CFG_BAUD_RATE_DIV_MASK 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GQSPI_CFG_CLK_PHA_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GQSPI_CFG_CLK_POL_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GQSPI_CFG_START_GEN_FIFO_MASK 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GQSPI_GENFIFO_IMM_DATA_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GQSPI_GENFIFO_DATA_XFER 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GQSPI_GENFIFO_EXP 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GQSPI_GENFIFO_MODE_SPI 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GQSPI_GENFIFO_MODE_DUALSPI 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GQSPI_GENFIFO_MODE_QUADSPI 0x00000C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GQSPI_GENFIFO_MODE_MASK 0x00000C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GQSPI_GENFIFO_CS_LOWER 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GQSPI_GENFIFO_CS_UPPER 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GQSPI_GENFIFO_BUS_LOWER 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GQSPI_GENFIFO_BUS_UPPER 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GQSPI_GENFIFO_BUS_BOTH 0x0000C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GQSPI_GENFIFO_BUS_MASK 0x0000C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GQSPI_GENFIFO_TX 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GQSPI_GENFIFO_RX 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GQSPI_GENFIFO_STRIPE 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GQSPI_GENFIFO_POLL 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GQSPI_GENFIFO_EXP_START 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GQSPI_ISR_RXEMPTY_MASK 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GQSPI_ISR_GENFIFOFULL_MASK 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GQSPI_ISR_GENFIFONOT_FULL_MASK 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GQSPI_ISR_TXEMPTY_MASK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GQSPI_ISR_GENFIFOEMPTY_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GQSPI_ISR_RXFULL_MASK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GQSPI_ISR_RXNEMPTY_MASK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GQSPI_ISR_TXFULL_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GQSPI_ISR_TXNOT_FULL_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GQSPI_ISR_POLL_TIME_EXPIRE_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GQSPI_IER_TXNOT_FULL_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GQSPI_IER_RXEMPTY_MASK 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GQSPI_IER_POLL_TIME_EXPIRE_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GQSPI_IER_RXNEMPTY_MASK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GQSPI_IER_GENFIFOEMPTY_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GQSPI_IER_TXEMPTY_MASK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GQSPI_QSPIDMA_DST_INTR_ALL_MASK 0x000000FE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GQSPI_QSPIDMA_DST_STS_WTC 0x0000E000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GQSPI_CFG_MODE_EN_DMA_MASK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GQSPI_ISR_IDR_MASK 0x00000994
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GQSPI_IRQ_MASK 0x00000980
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GQSPI_CFG_BAUD_RATE_DIV_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GQSPI_GENFIFO_CS_SETUP 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GQSPI_GENFIFO_CS_HOLD 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GQSPI_TXD_DEPTH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GQSPI_RX_FIFO_THRESHOLD 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GQSPI_RX_FIFO_FILL (GQSPI_RX_FIFO_THRESHOLD * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL 0X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GQSPI_SELECT_FLASH_CS_LOWER 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GQSPI_SELECT_FLASH_CS_UPPER 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GQSPI_SELECT_FLASH_CS_BOTH 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GQSPI_SELECT_FLASH_BUS_LOWER 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GQSPI_SELECT_FLASH_BUS_UPPER 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GQSPI_SELECT_FLASH_BUS_BOTH 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GQSPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GQSPI_BAUD_DIV_SHIFT 2 /* Baud rate divisor shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GQSPI_SELECT_MODE_SPI 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GQSPI_SELECT_MODE_DUALSPI 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GQSPI_SELECT_MODE_QUADSPI 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GQSPI_DMA_UNALIGN 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SPI_AUTOSUSPEND_TIMEOUT 3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * struct zynqmp_qspi - Defines qspi driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @regs: Virtual address of the QSPI controller registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @refclk: Pointer to the peripheral clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @pclk: Pointer to the APB clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @irq: IRQ number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @dev: Pointer to struct device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @txbuf: Pointer to the TX buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @rxbuf: Pointer to the RX buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @bytes_to_transfer: Number of bytes left to transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @bytes_to_receive: Number of bytes left to receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * @genfifocs: Used for chip select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @genfifobus: Used to select the upper or lower bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @dma_rx_bytes: Remaining bytes to receive by DMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @dma_addr: DMA address after mapping the kernel buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @genfifoentry: Used for storing the genfifoentry instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @mode: Defines the mode in which QSPI is operating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @data_completion: completion structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct zynqmp_qspi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct clk *refclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) const void *txbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void *rxbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int bytes_to_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int bytes_to_receive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 genfifocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 genfifobus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 dma_rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 genfifoentry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) enum mode_type mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct completion data_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct mutex op_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * zynqmp_gqspi_read - For GQSPI controller read operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @xqspi: Pointer to the zynqmp_qspi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @offset: Offset from where to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Return: Value at the offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return readl_relaxed(xqspi->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * zynqmp_gqspi_write - For GQSPI controller write operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @xqspi: Pointer to the zynqmp_qspi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @offset: Offset where to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @val: Value to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) writel_relaxed(val, (xqspi->regs + offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * zynqmp_gqspi_selectslave - For selection of slave device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * @instanceptr: Pointer to the zynqmp_qspi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @slavecs: For chip select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * @slavebus: To check which bus is selected- upper or lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 slavecs, u8 slavebus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Bus and CS lines selected here will be updated in the instance and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * used for subsequent GENFIFO entries during transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Choose slave select line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) switch (slavecs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case GQSPI_SELECT_FLASH_CS_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) GQSPI_GENFIFO_CS_UPPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) case GQSPI_SELECT_FLASH_CS_UPPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) case GQSPI_SELECT_FLASH_CS_LOWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_warn(instanceptr->dev, "Invalid slave select\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Choose the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) switch (slavebus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case GQSPI_SELECT_FLASH_BUS_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) GQSPI_GENFIFO_BUS_UPPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) case GQSPI_SELECT_FLASH_BUS_UPPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case GQSPI_SELECT_FLASH_BUS_LOWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dev_warn(instanceptr->dev, "Invalid slave bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * zynqmp_qspi_init_hw - Initialize the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * @xqspi: Pointer to the zynqmp_qspi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * The default settings of the QSPI controller's configurable parameters on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * reset are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * - Master mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * - TX threshold set to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * - RX threshold set to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * - Flash memory interface mode enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * This function performs the following actions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * - Disable and clear all the interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * - Enable manual slave select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * - Enable manual start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * - Deselect all the chip select lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * - Set the little endian mode of TX FIFO and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * - Enable the QSPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 config_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Select the GQSPI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Clear and disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) GQSPI_ISR_WR_TO_CLR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Clear the DMA STS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) zynqmp_gqspi_read(xqspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) GQSPI_QSPIDMA_DST_I_STS_OFST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) zynqmp_gqspi_read(xqspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) GQSPI_QSPIDMA_DST_STS_OFST) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) GQSPI_QSPIDMA_DST_STS_WTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) zynqmp_gqspi_write(xqspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) GQSPI_QSPIDMA_DST_I_DIS_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Disable the GQSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Manual start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Little endian by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Disable poll time out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Set hold bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) config_reg |= GQSPI_CFG_WP_HOLD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Clear pre-scalar by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* CPHA 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* CPOL 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Clear the TX and RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Set by default to allow for high frequencies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Reset thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) GQSPI_RX_FIFO_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) zynqmp_gqspi_selectslave(xqspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) GQSPI_SELECT_FLASH_CS_LOWER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) GQSPI_SELECT_FLASH_BUS_LOWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Initialize DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) zynqmp_gqspi_write(xqspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) GQSPI_QSPIDMA_DST_CTRL_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Enable the GQSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * zynqmp_qspi_copy_read_data - Copy data to RX buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * @xqspi: Pointer to the zynqmp_qspi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * @data: The variable where data is stored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * @size: Number of bytes to be copied from data to RX buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ulong data, u8 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) memcpy(xqspi->rxbuf, &data, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) xqspi->rxbuf += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) xqspi->bytes_to_receive -= size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * zynqmp_qspi_chipselect - Select or deselect the chip select line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * @qspi: Pointer to the spi_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * @is_high: Select(0) or deselect (1) the chip select line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ulong timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 genfifoentry = 0, statusreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (!is_high) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) genfifoentry |= xqspi->genfifobus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) genfifoentry |= xqspi->genfifocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Manually start the generic FIFO command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) GQSPI_CFG_START_GEN_FIFO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) timeout = jiffies + msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Wait until the generic FIFO command is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) (statusreg & GQSPI_ISR_TXEMPTY_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) } while (!time_after_eq(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (time_after_eq(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_err(xqspi->dev, "Chip select timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * @xqspi: xqspi is a pointer to the GQSPI instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * @spimode: spimode - SPI or DUAL or QUAD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * Return: Mask to set desired SPI mode in GENFIFO entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u8 spimode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u32 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) switch (spimode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case GQSPI_SELECT_MODE_DUALSPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mask = GQSPI_GENFIFO_MODE_DUALSPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) case GQSPI_SELECT_MODE_QUADSPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) mask = GQSPI_GENFIFO_MODE_QUADSPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) case GQSPI_SELECT_MODE_SPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mask = GQSPI_GENFIFO_MODE_SPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_warn(xqspi->dev, "Invalid SPI mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * zynqmp_qspi_config_op - Configure QSPI controller for specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * @xqspi: Pointer to the zynqmp_qspi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * @qspi: Pointer to the spi_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * Sets the operational mode of QSPI controller for the next QSPI transfer and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * sets the requested clock frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * Return: Always 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * If the requested frequency is not an exact match with what can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * obtained using the pre-scalar value, the driver sets the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * frequency which is lower than the requested frequency (maximum lower)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * for the transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * If the requested frequency is higher or lower than that is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * by the QSPI controller the driver will set the highest or lowest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * frequency supported by controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct spi_device *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ulong clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u32 config_reg, baud_rate_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Set the clock frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* If req_hz == 0, default to lowest speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) clk_rate = clk_get_rate(xqspi->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) (clk_rate /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > qspi->max_speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) baud_rate_val++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Set the QSPI clock phase and clock polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (qspi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) config_reg |= GQSPI_CFG_CLK_PHA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (qspi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) config_reg |= GQSPI_CFG_CLK_POL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * zynqmp_qspi_setup_op - Configure the QSPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * @qspi: Pointer to the spi_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * Sets the operational mode of QSPI controller for the next QSPI transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * baud rate and divisor value to setup the requested qspi clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * Return: 0 on success; error value otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int zynqmp_qspi_setup_op(struct spi_device *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct spi_controller *ctlr = qspi->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (ctlr->busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * zynqmp_qspi_filltxfifo - Fills the TX FIFO as long as there is room in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * the FIFO or the bytes required to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * transmitted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * @xqspi: Pointer to the zynqmp_qspi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * @size: Number of bytes to be copied from TX buffer to TX FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u32 count = 0, intermediate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) while ((xqspi->bytes_to_transfer > 0) && (count < size) && (xqspi->txbuf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) memcpy(&intermediate, xqspi->txbuf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (xqspi->bytes_to_transfer >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) xqspi->txbuf += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) xqspi->bytes_to_transfer -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) xqspi->txbuf += xqspi->bytes_to_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) xqspi->bytes_to_transfer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * zynqmp_qspi_readrxfifo - Fills the RX FIFO as long as there is room in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * the FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * @xqspi: Pointer to the zynqmp_qspi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * @size: Number of bytes to be copied from RX buffer to RX FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ulong data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) while ((count < size) && (xqspi->bytes_to_receive > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (xqspi->bytes_to_receive >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) (*(u32 *)xqspi->rxbuf) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) xqspi->rxbuf += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) xqspi->bytes_to_receive -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) count += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) count += xqspi->bytes_to_receive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) zynqmp_qspi_copy_read_data(xqspi, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) xqspi->bytes_to_receive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) xqspi->bytes_to_receive = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * zynqmp_qspi_fillgenfifo - Fills the GENFIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * @xqspi: Pointer to the zynqmp_qspi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * @nbits: Transfer/Receive buswidth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * @genfifoentry: Variable in which GENFIFO mask is saved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static void zynqmp_qspi_fillgenfifo(struct zynqmp_qspi *xqspi, u8 nbits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 genfifoentry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u32 transfer_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (xqspi->txbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) genfifoentry &= ~GQSPI_GENFIFO_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) genfifoentry |= GQSPI_GENFIFO_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) transfer_len = xqspi->bytes_to_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) } else if (xqspi->rxbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) genfifoentry &= ~GQSPI_GENFIFO_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) genfifoentry |= GQSPI_GENFIFO_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (xqspi->mode == GQSPI_MODE_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) transfer_len = xqspi->dma_rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) transfer_len = xqspi->bytes_to_receive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Sending dummy circles here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) genfifoentry &= ~(GQSPI_GENFIFO_TX | GQSPI_GENFIFO_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) transfer_len = xqspi->bytes_to_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) genfifoentry |= zynqmp_qspi_selectspimode(xqspi, nbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) xqspi->genfifoentry = genfifoentry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) genfifoentry |= transfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int tempcount = transfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u32 exponent = 8; /* 2^8 = 256 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u8 imm_data = tempcount & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) tempcount &= ~(tempcount & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* Immediate entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (tempcount != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Exponent entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) genfifoentry |= GQSPI_GENFIFO_EXP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) while (tempcount != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (tempcount & GQSPI_GENFIFO_EXP_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) genfifoentry &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ~GQSPI_GENFIFO_IMM_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) genfifoentry |= exponent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) zynqmp_gqspi_write(xqspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) GQSPI_GEN_FIFO_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) genfifoentry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) tempcount = tempcount >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) exponent++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (imm_data != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) genfifoentry &= ~GQSPI_GENFIFO_EXP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) genfifoentry |= (u8)(imm_data & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) genfifoentry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* Dummy generic FIFO entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * zynqmp_process_dma_irq - Handler for DMA done interrupt of QSPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * @xqspi: zynqmp_qspi instance pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * This function handles DMA interrupt only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 config_reg, genfifoentry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dma_unmap_single(xqspi->dev, xqspi->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) xqspi->rxbuf += xqspi->dma_rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) xqspi->dma_rx_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* Disabling the DMA interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (xqspi->bytes_to_receive > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Switch to IO mode,for remaining bytes to receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* Initiate the transfer of remaining bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) genfifoentry = xqspi->genfifoentry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) genfifoentry |= xqspi->bytes_to_receive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Dummy generic FIFO entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* Manual start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) (zynqmp_gqspi_read(xqspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) GQSPI_CONFIG_OFST) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) GQSPI_CFG_START_GEN_FIFO_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* Enable the RX interrupts for IO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) GQSPI_IER_GENFIFOEMPTY_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) GQSPI_IER_RXNEMPTY_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) GQSPI_IER_RXEMPTY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * zynqmp_qspi_irq - Interrupt service routine of the QSPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * @irq: IRQ number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * @dev_id: Pointer to the xqspi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * This function handles TX empty only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * On TX empty interrupt this function reads the received data from RX FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * and fills the TX FIFO if there is any data remaining to be transferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * Return: IRQ_HANDLED when interrupt is handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * IRQ_NONE otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u32 status, mask, dma_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Read and clear DMA status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (xqspi->mode == GQSPI_MODE_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dma_status =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dma_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) zynqmp_process_dma_irq(xqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (xqspi->bytes_to_receive == 0 && xqspi->bytes_to_transfer == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) complete(&xqspi->data_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * @xqspi: xqspi is a pointer to the GQSPI instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static int zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) u32 rx_bytes, rx_rem, config_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (xqspi->bytes_to_receive < 8 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* Setting to IO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) xqspi->mode = GQSPI_MODE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) xqspi->dma_rx_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) rx_rem = xqspi->bytes_to_receive % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) rx_bytes = (xqspi->bytes_to_receive - rx_rem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) rx_bytes, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (dma_mapping_error(xqspi->dev, addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) xqspi->dma_rx_bytes = rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) xqspi->dma_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) (u32)(addr & 0xffffffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) addr = ((addr >> 16) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ((u32)addr) & 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* Enabling the DMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* Switch to DMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) xqspi->mode = GQSPI_MODE_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* Write the number of bytes to transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * zynqmp_qspi_write_op - This function sets up the GENFIFO entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * TX FIFO, and fills the TX FIFO with as many
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * bytes as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * @xqspi: Pointer to the GQSPI instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * @tx_nbits: Transfer buswidth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * @genfifoentry: Variable in which GENFIFO mask is returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * to calling function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static void zynqmp_qspi_write_op(struct zynqmp_qspi *xqspi, u8 tx_nbits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u32 genfifoentry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u32 config_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) zynqmp_qspi_fillgenfifo(xqspi, tx_nbits, genfifoentry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (xqspi->mode == GQSPI_MODE_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) config_reg = zynqmp_gqspi_read(xqspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) GQSPI_CONFIG_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) config_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) xqspi->mode = GQSPI_MODE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * zynqmp_qspi_read_op - This function sets up the GENFIFO entries and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * RX DMA operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * @xqspi: xqspi is a pointer to the GQSPI instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * @rx_nbits: Receive buswidth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * @genfifoentry: genfifoentry is pointer to the variable in which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * GENFIFO mask is returned to calling function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static int zynqmp_qspi_read_op(struct zynqmp_qspi *xqspi, u8 rx_nbits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u32 genfifoentry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ret = zynqmp_qspi_setuprxdma(xqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) zynqmp_qspi_fillgenfifo(xqspi, rx_nbits, genfifoentry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * zynqmp_qspi_suspend - Suspend method for the QSPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * @dev: Address of the platform_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * This function stops the QSPI driver queue and disables the QSPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * Return: Always 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct spi_controller *ctlr = xqspi->ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ret = spi_controller_suspend(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * zynqmp_qspi_resume - Resume method for the QSPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * @dev: Address of the platform_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * The function starts the QSPI driver queue and initializes the QSPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * Return: 0 on success; error value otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct spi_controller *ctlr = xqspi->ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) spi_controller_resume(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * @dev: Address of the platform_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * This function disables the clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * Return: Always 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) clk_disable_unprepare(xqspi->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) clk_disable_unprepare(xqspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * zynqmp_runtime_resume - Runtime resume method for the SPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * @dev: Address of the platform_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * This function enables the clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * Return: 0 on success and error value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static int __maybe_unused zynqmp_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ret = clk_prepare_enable(xqspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) dev_err(dev, "Cannot enable APB clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ret = clk_prepare_enable(xqspi->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dev_err(dev, "Cannot enable device clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) clk_disable_unprepare(xqspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * zynqmp_qspi_exec_op() - Initiates the QSPI transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * @mem: The SPI memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * @op: The memory operation to execute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * Executes a memory operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * This function first selects the chip and starts the memory operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * Return: 0 in case of success, a negative error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static int zynqmp_qspi_exec_op(struct spi_mem *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct zynqmp_qspi *xqspi = spi_controller_get_devdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) (mem->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) int err = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) u32 genfifoentry = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) u16 opcode = op->cmd.opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) u64 opaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) op->dummy.buswidth, op->data.buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) mutex_lock(&xqspi->op_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) zynqmp_qspi_config_op(xqspi, mem->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) zynqmp_qspi_chipselect(mem->spi, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) genfifoentry |= xqspi->genfifocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) genfifoentry |= xqspi->genfifobus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (op->cmd.opcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) reinit_completion(&xqspi->data_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) xqspi->txbuf = &opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) xqspi->rxbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) xqspi->bytes_to_transfer = op->cmd.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) xqspi->bytes_to_receive = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) zynqmp_qspi_write_op(xqspi, op->cmd.buswidth, genfifoentry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) GQSPI_CFG_START_GEN_FIFO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) GQSPI_IER_GENFIFOEMPTY_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) GQSPI_IER_TXNOT_FULL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (!wait_for_completion_timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) (&xqspi->data_completion, msecs_to_jiffies(1000))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) goto return_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (op->addr.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) xqspi->txbuf = &opaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) for (i = 0; i < op->addr.nbytes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) *(((u8 *)xqspi->txbuf) + i) = op->addr.val >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) (8 * (op->addr.nbytes - i - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) reinit_completion(&xqspi->data_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) xqspi->rxbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) xqspi->bytes_to_transfer = op->addr.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) xqspi->bytes_to_receive = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) zynqmp_qspi_write_op(xqspi, op->addr.buswidth, genfifoentry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) zynqmp_gqspi_read(xqspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) GQSPI_CONFIG_OFST) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) GQSPI_CFG_START_GEN_FIFO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) GQSPI_IER_TXEMPTY_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) GQSPI_IER_GENFIFOEMPTY_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) GQSPI_IER_TXNOT_FULL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (!wait_for_completion_timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) (&xqspi->data_completion, msecs_to_jiffies(1000))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) goto return_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (op->dummy.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) xqspi->txbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) xqspi->rxbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * xqspi->bytes_to_transfer here represents the dummy circles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * which need to be sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) xqspi->bytes_to_transfer = op->dummy.nbytes * 8 / op->dummy.buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) xqspi->bytes_to_receive = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * Using op->data.buswidth instead of op->dummy.buswidth here because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * we need to use it to configure the correct SPI mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) zynqmp_qspi_write_op(xqspi, op->data.buswidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) genfifoentry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) GQSPI_CFG_START_GEN_FIFO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (op->data.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) reinit_completion(&xqspi->data_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (op->data.dir == SPI_MEM_DATA_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) xqspi->txbuf = (u8 *)op->data.buf.out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) xqspi->rxbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) xqspi->bytes_to_transfer = op->data.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) xqspi->bytes_to_receive = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) zynqmp_qspi_write_op(xqspi, op->data.buswidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) genfifoentry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) zynqmp_gqspi_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) (xqspi, GQSPI_CONFIG_OFST) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) GQSPI_CFG_START_GEN_FIFO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) GQSPI_IER_TXEMPTY_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) GQSPI_IER_GENFIFOEMPTY_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) GQSPI_IER_TXNOT_FULL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) xqspi->txbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) xqspi->rxbuf = (u8 *)op->data.buf.in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) xqspi->bytes_to_receive = op->data.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) xqspi->bytes_to_transfer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) err = zynqmp_qspi_read_op(xqspi, op->data.buswidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) genfifoentry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) goto return_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) zynqmp_gqspi_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) (xqspi, GQSPI_CONFIG_OFST) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) GQSPI_CFG_START_GEN_FIFO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (xqspi->mode == GQSPI_MODE_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) zynqmp_gqspi_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) (xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) GQSPI_IER_GENFIFOEMPTY_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) GQSPI_IER_RXNEMPTY_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) GQSPI_IER_RXEMPTY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (!wait_for_completion_timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) (&xqspi->data_completion, msecs_to_jiffies(1000)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) zynqmp_qspi_chipselect(mem->spi, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) mutex_unlock(&xqspi->op_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) zynqmp_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .exec_op = zynqmp_qspi_exec_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * zynqmp_qspi_probe - Probe method for the QSPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * @pdev: Pointer to the platform_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * This function initializes the driver data structures and the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * Return: 0 on success; error value otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static int zynqmp_qspi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct zynqmp_qspi *xqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (!ctlr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) xqspi = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) xqspi->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) xqspi->ctlr = ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) platform_set_drvdata(pdev, xqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (IS_ERR(xqspi->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) ret = PTR_ERR(xqspi->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) goto remove_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (IS_ERR(xqspi->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) dev_err(dev, "pclk clock not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) ret = PTR_ERR(xqspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) goto remove_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (IS_ERR(xqspi->refclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) dev_err(dev, "ref_clk clock not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ret = PTR_ERR(xqspi->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) goto remove_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) ret = clk_prepare_enable(xqspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) dev_err(dev, "Unable to enable APB clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) goto remove_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ret = clk_prepare_enable(xqspi->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) dev_err(dev, "Unable to enable device clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) goto clk_dis_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) init_completion(&xqspi->data_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) mutex_init(&xqspi->op_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* QSPI controller initializations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) zynqmp_qspi_init_hw(xqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) pm_runtime_mark_last_busy(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) pm_runtime_put_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) xqspi->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (xqspi->irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) goto clk_dis_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) 0, pdev->name, xqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) dev_err(dev, "request_irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) goto clk_dis_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) goto clk_dis_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ctlr->mem_ops = &zynqmp_qspi_mem_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ctlr->setup = zynqmp_qspi_setup_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) SPI_TX_DUAL | SPI_TX_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ctlr->dev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ret = devm_spi_register_controller(&pdev->dev, ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) dev_err(&pdev->dev, "spi_register_controller failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) goto clk_dis_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) clk_dis_all:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) clk_disable_unprepare(xqspi->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) clk_dis_pclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) clk_disable_unprepare(xqspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) remove_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) spi_controller_put(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * zynqmp_qspi_remove - Remove method for the QSPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * @pdev: Pointer to the platform_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * This function is called if a device is physically removed from the system or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * if the driver module is being unloaded. It frees all resources allocated to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) * Return: 0 Always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static int zynqmp_qspi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct zynqmp_qspi *xqspi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) clk_disable_unprepare(xqspi->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) clk_disable_unprepare(xqspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) static const struct of_device_id zynqmp_qspi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) { .compatible = "xlnx,zynqmp-qspi-1.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) { /* End of table */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static struct platform_driver zynqmp_qspi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .probe = zynqmp_qspi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .remove = zynqmp_qspi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .name = "zynqmp-qspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .of_match_table = zynqmp_qspi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .pm = &zynqmp_qspi_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) module_platform_driver(zynqmp_qspi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) MODULE_AUTHOR("Xilinx, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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