^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2019 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Naga Sureshkumar Relli <nagasure@xilinx.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spi/spi-mem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Register offset definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ZYNQ_QSPI_CONFIG_OFFSET 0x00 /* Configuration Register, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ZYNQ_QSPI_STATUS_OFFSET 0x04 /* Interrupt Status Register, RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ZYNQ_QSPI_IEN_OFFSET 0x08 /* Interrupt Enable Register, WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ZYNQ_QSPI_IDIS_OFFSET 0x0C /* Interrupt Disable Reg, WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ZYNQ_QSPI_IMASK_OFFSET 0x10 /* Interrupt Enabled Mask Reg,RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ZYNQ_QSPI_ENABLE_OFFSET 0x14 /* Enable/Disable Register, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ZYNQ_QSPI_DELAY_OFFSET 0x18 /* Delay Register, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ZYNQ_QSPI_RXD_OFFSET 0x20 /* Data Receive Register, RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ZYNQ_QSPI_SIC_OFFSET 0x24 /* Slave Idle Count Register, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ZYNQ_QSPI_TX_THRESH_OFFSET 0x28 /* TX FIFO Watermark Reg, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ZYNQ_QSPI_RX_THRESH_OFFSET 0x2C /* RX FIFO Watermark Reg, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ZYNQ_QSPI_GPIO_OFFSET 0x30 /* GPIO Register, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ZYNQ_QSPI_LINEAR_CFG_OFFSET 0xA0 /* Linear Adapter Config Ref, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ZYNQ_QSPI_MOD_ID_OFFSET 0xFC /* Module ID Register, RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * QSPI Configuration Register bit Masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * This register contains various control bits that effect the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * of the QSPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ZYNQ_QSPI_CONFIG_IFMODE_MASK BIT(31) /* Flash Memory Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ZYNQ_QSPI_CONFIG_MANSRT_MASK BIT(16) /* Manual TX Start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ZYNQ_QSPI_CONFIG_MANSRTEN_MASK BIT(15) /* Enable Manual TX Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ZYNQ_QSPI_CONFIG_SSFORCE_MASK BIT(14) /* Manual Chip Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ZYNQ_QSPI_CONFIG_BDRATE_MASK GENMASK(5, 3) /* Baud Rate Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ZYNQ_QSPI_CONFIG_CPHA_MASK BIT(2) /* Clock Phase Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ZYNQ_QSPI_CONFIG_CPOL_MASK BIT(1) /* Clock Polarity Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ZYNQ_QSPI_CONFIG_FWIDTH_MASK GENMASK(7, 6) /* FIFO width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ZYNQ_QSPI_CONFIG_MSTREN_MASK BIT(0) /* Master Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * QSPI Configuration Register - Baud rate and slave select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * These are the values used in the calculation of baud rate divisor and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * setting the slave select.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX GENMASK(2, 0) /* Baud rate maximum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ZYNQ_QSPI_CONFIG_PCS BIT(10) /* Peripheral Chip Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * QSPI Interrupt Registers bit Masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * bit definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK BIT(0) /* QSPI RX FIFO Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ZYNQ_QSPI_IXR_TXNFULL_MASK BIT(2) /* QSPI TX FIFO Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ZYNQ_QSPI_IXR_TXFULL_MASK BIT(3) /* QSPI TX FIFO is full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ZYNQ_QSPI_IXR_RXNEMTY_MASK BIT(4) /* QSPI RX FIFO Not Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ZYNQ_QSPI_IXR_RXF_FULL_MASK BIT(5) /* QSPI RX FIFO is full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK BIT(6) /* QSPI TX FIFO Underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ZYNQ_QSPI_IXR_ALL_MASK (ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ZYNQ_QSPI_IXR_TXNFULL_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ZYNQ_QSPI_IXR_TXFULL_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ZYNQ_QSPI_IXR_RXNEMTY_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ZYNQ_QSPI_IXR_RXF_FULL_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ZYNQ_QSPI_IXR_RXTX_MASK (ZYNQ_QSPI_IXR_TXNFULL_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ZYNQ_QSPI_IXR_RXNEMTY_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * QSPI Enable Register bit Masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * This register is used to enable or disable the QSPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ZYNQ_QSPI_ENABLE_ENABLE_MASK BIT(0) /* QSPI Enable Bit Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * QSPI Linear Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * It is named Linear Configuration but it controls other modes when not in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * linear mode also.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ZYNQ_QSPI_LCFG_TWO_MEM BIT(30) /* LQSPI Two memories */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ZYNQ_QSPI_LCFG_SEP_BUS BIT(29) /* LQSPI Separate bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ZYNQ_QSPI_LCFG_U_PAGE BIT(28) /* LQSPI Upper Page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ZYNQ_QSPI_LCFG_DUMMY_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ZYNQ_QSPI_FAST_READ_QOUT_CODE 0x6B /* read instruction code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ZYNQ_QSPI_FIFO_DEPTH 63 /* FIFO depth in words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ZYNQ_QSPI_RX_THRESHOLD 32 /* Rx FIFO threshold level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ZYNQ_QSPI_TX_THRESHOLD 1 /* Tx FIFO threshold level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * The modebits configurable by the driver to make the SPI support different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * data formats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ZYNQ_QSPI_MODEBITS (SPI_CPOL | SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Maximum number of chip selects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ZYNQ_QSPI_MAX_NUM_CS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * struct zynq_qspi - Defines qspi driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @dev: Pointer to the this device's information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @regs: Virtual address of the QSPI controller registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @refclk: Pointer to the peripheral clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @pclk: Pointer to the APB clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @irq: IRQ number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @txbuf: Pointer to the TX buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @rxbuf: Pointer to the RX buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @tx_bytes: Number of bytes left to transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @rx_bytes: Number of bytes left to receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @data_completion: completion structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct zynq_qspi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct clk *refclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 *txbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u8 *rxbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct completion data_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Inline functions for the QSPI controller read/write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static inline u32 zynq_qspi_read(struct zynq_qspi *xqspi, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return readl_relaxed(xqspi->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static inline void zynq_qspi_write(struct zynq_qspi *xqspi, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) writel_relaxed(val, xqspi->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * zynq_qspi_init_hw - Initialize the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @xqspi: Pointer to the zynq_qspi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @num_cs: Number of connected CS (to enable dual memories if needed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * The default settings of the QSPI controller's configurable parameters on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * reset are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * - Master mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * - Baud rate divisor is set to 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * - Tx threshold set to 1l Rx threshold set to 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * - Flash memory interface mode enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * - Size of the word to be transferred as 8 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * This function performs the following actions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * - Disable and clear all the interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * - Enable manual slave select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * - Enable manual start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * - Deselect all the chip select lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * - Set the size of the word to be transferred as 32 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * - Set the little endian mode of TX FIFO and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * - Enable the QSPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void zynq_qspi_init_hw(struct zynq_qspi *xqspi, unsigned int num_cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 config_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) zynq_qspi_write(xqspi, ZYNQ_QSPI_IDIS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Disable linear mode as the boot loader may have used it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) config_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* At the same time, enable dual mode if more than 1 CS is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (num_cs > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) config_reg |= ZYNQ_QSPI_LCFG_TWO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Clear the RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) while (zynq_qspi_read(xqspi, ZYNQ_QSPI_STATUS_OFFSET) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ZYNQ_QSPI_IXR_RXNEMTY_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) zynq_qspi_read(xqspi, ZYNQ_QSPI_RXD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) config_reg &= ~(ZYNQ_QSPI_CONFIG_MSTREN_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ZYNQ_QSPI_CONFIG_CPOL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ZYNQ_QSPI_CONFIG_CPHA_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ZYNQ_QSPI_CONFIG_BDRATE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ZYNQ_QSPI_CONFIG_SSFORCE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ZYNQ_QSPI_CONFIG_MANSRTEN_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ZYNQ_QSPI_CONFIG_MANSRT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) config_reg |= (ZYNQ_QSPI_CONFIG_MSTREN_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ZYNQ_QSPI_CONFIG_SSFORCE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ZYNQ_QSPI_CONFIG_FWIDTH_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ZYNQ_QSPI_CONFIG_IFMODE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) zynq_qspi_write(xqspi, ZYNQ_QSPI_RX_THRESH_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ZYNQ_QSPI_RX_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) zynq_qspi_write(xqspi, ZYNQ_QSPI_TX_THRESH_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ZYNQ_QSPI_TX_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ZYNQ_QSPI_ENABLE_ENABLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static bool zynq_qspi_supports_op(struct spi_mem *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!spi_mem_default_supports_op(mem, op))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * The number of address bytes should be equal to or less than 3 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (op->addr.nbytes > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * zynq_qspi_rxfifo_op - Read 1..4 bytes from RxFIFO to RX buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @xqspi: Pointer to the zynq_qspi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * @size: Number of bytes to be read (1..4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void zynq_qspi_rxfifo_op(struct zynq_qspi *xqspi, unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) data = zynq_qspi_read(xqspi, ZYNQ_QSPI_RXD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (xqspi->rxbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) memcpy(xqspi->rxbuf, ((u8 *)&data) + 4 - size, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) xqspi->rxbuf += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) xqspi->rx_bytes -= size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (xqspi->rx_bytes < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) xqspi->rx_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * zynq_qspi_txfifo_op - Write 1..4 bytes from TX buffer to TxFIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * @xqspi: Pointer to the zynq_qspi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * @size: Number of bytes to be written (1..4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void zynq_qspi_txfifo_op(struct zynq_qspi *xqspi, unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const unsigned int offset[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ZYNQ_QSPI_TXD_00_01_OFFSET, ZYNQ_QSPI_TXD_00_10_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ZYNQ_QSPI_TXD_00_11_OFFSET, ZYNQ_QSPI_TXD_00_00_OFFSET };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (xqspi->txbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) data = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) memcpy(&data, xqspi->txbuf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) xqspi->txbuf += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) xqspi->tx_bytes -= size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) zynq_qspi_write(xqspi, offset[size - 1], data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * zynq_qspi_chipselect - Select or deselect the chip select line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * @spi: Pointer to the spi_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * @assert: 1 for select or 0 for deselect the chip select line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void zynq_qspi_chipselect(struct spi_device *spi, bool assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct spi_controller *ctlr = spi->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct zynq_qspi *xqspi = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 config_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Select the lower (CS0) or upper (CS1) memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (ctlr->num_chipselect > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (!spi->chip_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) config_reg &= ~ZYNQ_QSPI_LCFG_U_PAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) config_reg |= ZYNQ_QSPI_LCFG_U_PAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Ground the line to assert the CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) config_reg &= ~ZYNQ_QSPI_CONFIG_PCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) config_reg |= ZYNQ_QSPI_CONFIG_PCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * zynq_qspi_config_op - Configure QSPI controller for specified transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * @xqspi: Pointer to the zynq_qspi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * @spi: Pointer to the spi_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * Sets the operational mode of QSPI controller for the next QSPI transfer and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * sets the requested clock frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Return: 0 on success and -EINVAL on invalid input parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Note: If the requested frequency is not an exact match with what can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * obtained using the prescalar value, the driver sets the clock frequency which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * is lower than the requested frequency (maximum lower) for the transfer. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * the requested frequency is higher or lower than that is supported by the QSPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * controller the driver will set the highest or lowest frequency supported by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 config_reg, baud_rate_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * Set the clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * The baud rate divisor is not a direct mapping to the value written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * into the configuration register (config_reg[5:3])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * i.e. 000 - divide by 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * 001 - divide by 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * ----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * 111 - divide by 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) while ((baud_rate_val < ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) spi->max_speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) baud_rate_val++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Set the QSPI clock phase and clock polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) config_reg &= (~ZYNQ_QSPI_CONFIG_CPHA_MASK) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) (~ZYNQ_QSPI_CONFIG_CPOL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) config_reg |= ZYNQ_QSPI_CONFIG_CPHA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) config_reg &= ~ZYNQ_QSPI_CONFIG_BDRATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) config_reg |= (baud_rate_val << ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * zynq_qspi_setup - Configure the QSPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * @spi: Pointer to the spi_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * Sets the operational mode of QSPI controller for the next QSPI transfer, baud
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * rate and divisor value to setup the requested qspi clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * Return: 0 on success and error value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int zynq_qspi_setup_op(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct spi_controller *ctlr = spi->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct zynq_qspi *qspi = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (ctlr->busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) clk_enable(qspi->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) clk_enable(qspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) zynq_qspi_write(qspi, ZYNQ_QSPI_ENABLE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ZYNQ_QSPI_ENABLE_ENABLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * zynq_qspi_write_op - Fills the TX FIFO with as many bytes as possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * @xqspi: Pointer to the zynq_qspi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * @txcount: Maximum number of words to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * @txempty: Indicates that TxFIFO is empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static void zynq_qspi_write_op(struct zynq_qspi *xqspi, int txcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) bool txempty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int count, len, k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) len = xqspi->tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (len && len < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * We must empty the TxFIFO between accesses to TXD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * TXD1, TXD2, TXD3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (txempty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) zynq_qspi_txfifo_op(xqspi, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) count = len / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (count > txcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) count = txcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (xqspi->txbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) iowrite32_rep(xqspi->regs + ZYNQ_QSPI_TXD_00_00_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) xqspi->txbuf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) xqspi->txbuf += count * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) for (k = 0; k < count; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) writel_relaxed(0, xqspi->regs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ZYNQ_QSPI_TXD_00_00_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) xqspi->tx_bytes -= count * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * zynq_qspi_read_op - Drains the RX FIFO by as many bytes as possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * @xqspi: Pointer to the zynq_qspi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * @rxcount: Maximum number of words to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static void zynq_qspi_read_op(struct zynq_qspi *xqspi, int rxcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int count, len, k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) len = xqspi->rx_bytes - xqspi->tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) count = len / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (count > rxcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) count = rxcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (xqspi->rxbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ioread32_rep(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) xqspi->rxbuf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) xqspi->rxbuf += count * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) for (k = 0; k < count; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) readl_relaxed(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) xqspi->rx_bytes -= count * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) len -= count * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (len && len < 4 && count < rxcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) zynq_qspi_rxfifo_op(xqspi, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * zynq_qspi_irq - Interrupt service routine of the QSPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * @irq: IRQ number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * @dev_id: Pointer to the xqspi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * This function handles TX empty only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * On TX empty interrupt this function reads the received data from RX FIFO and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * fills the TX FIFO if there is any data remaining to be transferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * Return: IRQ_HANDLED when interrupt is handled; IRQ_NONE otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static irqreturn_t zynq_qspi_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u32 intr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) bool txempty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct zynq_qspi *xqspi = (struct zynq_qspi *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) intr_status = zynq_qspi_read(xqspi, ZYNQ_QSPI_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if ((intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) (intr_status & ZYNQ_QSPI_IXR_RXNEMTY_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * This bit is set when Tx FIFO has < THRESHOLD entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * We have the THRESHOLD value set to 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * so this bit indicates Tx FIFO is empty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) txempty = !!(intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Read out the data from the RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) zynq_qspi_read_op(xqspi, ZYNQ_QSPI_RX_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (xqspi->tx_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* There is more data to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) zynq_qspi_write_op(xqspi, ZYNQ_QSPI_RX_THRESHOLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) txempty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * If transfer and receive is completed then only send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * complete signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!xqspi->rx_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) zynq_qspi_write(xqspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ZYNQ_QSPI_IDIS_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ZYNQ_QSPI_IXR_RXTX_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) complete(&xqspi->data_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * zynq_qspi_exec_mem_op() - Initiates the QSPI transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * @mem: the SPI memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * @op: the memory operation to execute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * Executes a memory operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * This function first selects the chip and starts the memory operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * Return: 0 in case of success, a negative error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static int zynq_qspi_exec_mem_op(struct spi_mem *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int err = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 *tmpbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) op->dummy.buswidth, op->data.buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) zynq_qspi_chipselect(mem->spi, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) zynq_qspi_config_op(xqspi, mem->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (op->cmd.opcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) reinit_completion(&xqspi->data_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) xqspi->txbuf = (u8 *)&op->cmd.opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) xqspi->rxbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) xqspi->tx_bytes = op->cmd.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) xqspi->rx_bytes = op->cmd.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ZYNQ_QSPI_IXR_RXTX_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (!wait_for_completion_timeout(&xqspi->data_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) msecs_to_jiffies(1000)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (op->addr.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) for (i = 0; i < op->addr.nbytes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) xqspi->txbuf[i] = op->addr.val >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) (8 * (op->addr.nbytes - i - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) reinit_completion(&xqspi->data_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) xqspi->rxbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) xqspi->tx_bytes = op->addr.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) xqspi->rx_bytes = op->addr.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ZYNQ_QSPI_IXR_RXTX_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (!wait_for_completion_timeout(&xqspi->data_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) msecs_to_jiffies(1000)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (op->dummy.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) tmpbuf = kzalloc(op->dummy.nbytes, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (!tmpbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) memset(tmpbuf, 0xff, op->dummy.nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) reinit_completion(&xqspi->data_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) xqspi->txbuf = tmpbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) xqspi->rxbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) xqspi->tx_bytes = op->dummy.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) xqspi->rx_bytes = op->dummy.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ZYNQ_QSPI_IXR_RXTX_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (!wait_for_completion_timeout(&xqspi->data_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) msecs_to_jiffies(1000)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) kfree(tmpbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (op->data.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) reinit_completion(&xqspi->data_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (op->data.dir == SPI_MEM_DATA_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) xqspi->txbuf = (u8 *)op->data.buf.out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) xqspi->tx_bytes = op->data.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) xqspi->rxbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) xqspi->rx_bytes = op->data.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) xqspi->txbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) xqspi->rxbuf = (u8 *)op->data.buf.in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) xqspi->rx_bytes = op->data.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) xqspi->tx_bytes = op->data.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ZYNQ_QSPI_IXR_RXTX_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (!wait_for_completion_timeout(&xqspi->data_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) msecs_to_jiffies(1000)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) zynq_qspi_chipselect(mem->spi, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static const struct spi_controller_mem_ops zynq_qspi_mem_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .supports_op = zynq_qspi_supports_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .exec_op = zynq_qspi_exec_mem_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * zynq_qspi_probe - Probe method for the QSPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * @pdev: Pointer to the platform_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * This function initializes the driver data structures and the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * Return: 0 on success and error value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static int zynq_qspi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct zynq_qspi *xqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u32 num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (!ctlr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) xqspi = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) xqspi->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) platform_set_drvdata(pdev, xqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (IS_ERR(xqspi->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ret = PTR_ERR(xqspi->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) goto remove_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (IS_ERR(xqspi->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dev_err(&pdev->dev, "pclk clock not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ret = PTR_ERR(xqspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) goto remove_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) init_completion(&xqspi->data_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (IS_ERR(xqspi->refclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) dev_err(&pdev->dev, "ref_clk clock not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ret = PTR_ERR(xqspi->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) goto remove_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ret = clk_prepare_enable(xqspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dev_err(&pdev->dev, "Unable to enable APB clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) goto remove_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ret = clk_prepare_enable(xqspi->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dev_err(&pdev->dev, "Unable to enable device clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) goto clk_dis_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) xqspi->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (xqspi->irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) goto clk_dis_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ret = devm_request_irq(&pdev->dev, xqspi->irq, zynq_qspi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 0, pdev->name, xqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dev_err(&pdev->dev, "request_irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) goto clk_dis_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ret = of_property_read_u32(np, "num-cs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) &num_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ctlr->num_chipselect = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) } else if (num_cs > ZYNQ_QSPI_MAX_NUM_CS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_err(&pdev->dev, "only 2 chip selects are available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) goto clk_dis_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ctlr->num_chipselect = num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) SPI_TX_DUAL | SPI_TX_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ctlr->mem_ops = &zynq_qspi_mem_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ctlr->setup = zynq_qspi_setup_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ctlr->dev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* QSPI controller initializations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) zynq_qspi_init_hw(xqspi, ctlr->num_chipselect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ret = devm_spi_register_controller(&pdev->dev, ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev_err(&pdev->dev, "spi_register_master failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) goto clk_dis_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) clk_dis_all:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) clk_disable_unprepare(xqspi->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) clk_dis_pclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) clk_disable_unprepare(xqspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) remove_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) spi_controller_put(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * zynq_qspi_remove - Remove method for the QSPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * @pdev: Pointer to the platform_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * This function is called if a device is physically removed from the system or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * if the driver module is being unloaded. It frees all resources allocated to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * Return: 0 on success and error value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static int zynq_qspi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct zynq_qspi *xqspi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) clk_disable_unprepare(xqspi->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) clk_disable_unprepare(xqspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static const struct of_device_id zynq_qspi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) { .compatible = "xlnx,zynq-qspi-1.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) { /* end of table */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) MODULE_DEVICE_TABLE(of, zynq_qspi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * zynq_qspi_driver - This structure defines the QSPI platform driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static struct platform_driver zynq_qspi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .probe = zynq_qspi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .remove = zynq_qspi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .name = "zynq-qspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .of_match_table = zynq_qspi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) module_platform_driver(zynq_qspi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) MODULE_AUTHOR("Xilinx, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) MODULE_DESCRIPTION("Xilinx Zynq QSPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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