^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Xtensa xtfpga SPI controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Cadence Design Systems Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spi/spi_bitbang.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define XTFPGA_SPI_NAME "xtfpga_spi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define XTFPGA_SPI_START 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define XTFPGA_SPI_BUSY 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define XTFPGA_SPI_DATA 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BUSY_WAIT_US 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct xtfpga_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct spi_bitbang bitbang;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned data_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static inline void xtfpga_spi_write32(const struct xtfpga_spi *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned addr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) __raw_writel(val, spi->regs + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static inline unsigned int xtfpga_spi_read32(const struct xtfpga_spi *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return __raw_readl(spi->regs + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static inline void xtfpga_spi_wait_busy(struct xtfpga_spi *xspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) for (i = 0; xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) i < BUSY_WAIT_US; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) WARN_ON_ONCE(i == BUSY_WAIT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static u32 xtfpga_spi_txrx_word(struct spi_device *spi, unsigned nsecs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 v, u8 bits, unsigned flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct xtfpga_spi *xspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) xspi->data = (xspi->data << bits) | (v & GENMASK(bits - 1, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) xspi->data_sz += bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (xspi->data_sz >= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) xtfpga_spi_write32(xspi, XTFPGA_SPI_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) xspi->data >> (xspi->data_sz - 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) xspi->data_sz -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) xtfpga_spi_wait_busy(xspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void xtfpga_spi_chipselect(struct spi_device *spi, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct xtfpga_spi *xspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) WARN_ON(xspi->data_sz != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) xspi->data_sz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int xtfpga_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct xtfpga_spi *xspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) master = spi_alloc_master(&pdev->dev, sizeof(struct xtfpga_spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) master->flags = SPI_MASTER_NO_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) master->bus_num = pdev->dev.id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) xspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) xspi->bitbang.master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) xspi->bitbang.chipselect = xtfpga_spi_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) xspi->bitbang.txrx_word[SPI_MODE_0] = xtfpga_spi_txrx_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) xspi->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (IS_ERR(xspi->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ret = PTR_ERR(xspi->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dev_err(&pdev->dev, "Device stuck in busy state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = spi_bitbang_start(&xspi->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dev_err(&pdev->dev, "spi_bitbang_start failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int xtfpga_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct xtfpga_spi *xspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) spi_bitbang_stop(&xspi->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MODULE_ALIAS("platform:" XTFPGA_SPI_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct of_device_id xtfpga_spi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { .compatible = "cdns,xtfpga-spi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MODULE_DEVICE_TABLE(of, xtfpga_spi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static struct platform_driver xtfpga_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .probe = xtfpga_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .remove = xtfpga_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .name = XTFPGA_SPI_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .of_match_table = of_match_ptr(xtfpga_spi_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) module_platform_driver(xtfpga_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MODULE_DESCRIPTION("xtensa xtfpga SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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