^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Xilinx SPI controller driver (master mode only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * source@mvista.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2010 Secret Lab Technologies, Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2009 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 2002-2007 (c) MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spi/spi_bitbang.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spi/xilinx_spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define XILINX_SPI_MAX_CS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define XILINX_SPI_NAME "xilinx_spi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Product Specification", DS464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define XSPI_CR_OFFSET 0x60 /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define XSPI_CR_LOOP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define XSPI_CR_ENABLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define XSPI_CR_MASTER_MODE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define XSPI_CR_CPOL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define XSPI_CR_CPHA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) XSPI_CR_LSB_FIRST | XSPI_CR_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define XSPI_CR_TXFIFO_RESET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define XSPI_CR_RXFIFO_RESET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define XSPI_CR_MANUAL_SSELECT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define XSPI_CR_TRANS_INHIBIT 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define XSPI_CR_LSB_FIRST 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define XSPI_SR_OFFSET 0x64 /* Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * IPIF registers are 32 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define XIPIF_V123B_GINTR_ENABLE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct xilinx_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* bitbang has to be first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct spi_bitbang bitbang;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void __iomem *regs; /* virt. address of the control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 *rx_ptr; /* pointer in the Tx buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const u8 *tx_ptr; /* pointer in the Rx buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int buffer_size; /* buffer size in words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 cs_inactive; /* Level of the CS pins when inactive*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int (*read_fn)(void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void (*write_fn)(u32, void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void xspi_write32(u32 val, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) iowrite32(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static unsigned int xspi_read32(void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return ioread32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void xspi_write32_be(u32 val, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) iowrite32be(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static unsigned int xspi_read32_be(void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ioread32be(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void xilinx_spi_tx(struct xilinx_spi *xspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (!xspi->tx_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) switch (xspi->bytes_per_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) data = *(u8 *)(xspi->tx_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) data = *(u16 *)(xspi->tx_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) data = *(u32 *)(xspi->tx_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) xspi->tx_ptr += xspi->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void xilinx_spi_rx(struct xilinx_spi *xspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (!xspi->rx_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) switch (xspi->bytes_per_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *(u8 *)(xspi->rx_ptr) = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *(u16 *)(xspi->rx_ptr) = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) *(u32 *)(xspi->rx_ptr) = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) xspi->rx_ptr += xspi->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void xspi_init_hw(struct xilinx_spi *xspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) void __iomem *regs_base = xspi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Reset the SPI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) xspi->write_fn(XIPIF_V123B_RESET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) regs_base + XIPIF_V123B_RESETR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Enable the transmit empty interrupt, which we use to determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * progress on the transmission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) xspi->write_fn(XSPI_INTR_TX_EMPTY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) regs_base + XIPIF_V123B_IIER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Disable the global IPIF interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Deselect the slave on the SPI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Disable the transmitter, enable Manual Slave Select Assertion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * put SPI controller into master mode, and enable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) xspi->write_fn(XSPI_CR_MANUAL_SSELECT | XSPI_CR_MASTER_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | XSPI_CR_RXFIFO_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) regs_base + XSPI_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u16 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (is_on == BITBANG_CS_INACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Deselect the slave on the SPI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Set the SPI clock phase and polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) cr |= XSPI_CR_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) cr |= XSPI_CR_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (spi->mode & SPI_LSB_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) cr |= XSPI_CR_LSB_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (spi->mode & SPI_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) cr |= XSPI_CR_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* We do not check spi->max_speed_hz here as the SPI clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * frequency is not software programmable (the IP block design
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * parameter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) cs = xspi->cs_inactive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) cs ^= BIT(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Activate the chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* spi_bitbang requires custom setup_transfer() to be defined if there is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * custom txrx_bufs().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int xilinx_spi_setup_transfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (spi->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) xspi->cs_inactive &= ~BIT(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) xspi->cs_inactive |= BIT(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int remaining_words; /* the number of words left to transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) bool use_irq = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u16 cr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* We get here with transmitter inhibited */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) xspi->tx_ptr = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) xspi->rx_ptr = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) remaining_words = t->len / xspi->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (xspi->irq >= 0 && remaining_words > xspi->buffer_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) use_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Inhibit irq to avoid spurious irqs on tx_empty*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) xspi->regs + XSPI_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* ACK old irqs (if any) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (isr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) xspi->write_fn(isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) xspi->regs + XIPIF_V123B_IISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Enable the global IPIF interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) xspi->regs + XIPIF_V123B_DGIER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) reinit_completion(&xspi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) while (remaining_words) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int n_words, tx_words, rx_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int stalled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) n_words = min(remaining_words, xspi->buffer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) tx_words = n_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) while (tx_words--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) xilinx_spi_tx(xspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Start the transfer by not inhibiting the transmitter any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * longer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (use_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) wait_for_completion(&xspi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* A transmit has just completed. Process received data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * and check for more data to transmit. Always inhibit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * the transmitter while the Isr refills the transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * register/FIFO, or make sure it is stopped if we're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) xspi->regs + XSPI_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) sr = XSPI_SR_TX_EMPTY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Read out all the data from the Rx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) rx_words = n_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) stalled = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) while (rx_words) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (rx_words == n_words && !(stalled--) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) !(sr & XSPI_SR_TX_EMPTY_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) (sr & XSPI_SR_RX_EMPTY_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "Detected stall. Check C_SPI_MODE and C_SPI_MEMORY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) xspi_init_hw(xspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if ((sr & XSPI_SR_TX_EMPTY_MASK) && (rx_words > 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) xilinx_spi_rx(xspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) rx_words--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (!(sr & XSPI_SR_RX_EMPTY_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) xilinx_spi_rx(xspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) rx_words--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) remaining_words -= n_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (use_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* This driver supports single master mode only. Hence Tx FIFO Empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * is the only interrupt we care about.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * Fault are not to happen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct xilinx_spi *xspi = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 ipif_isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Get the IPIF interrupts, and clear them immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) complete(&xspi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u8 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int n_words = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * Before the buffer_size detection we reset the core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * to make sure we start with a clean state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) xspi->write_fn(XIPIF_V123B_RESET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) xspi->regs + XIPIF_V123B_RESETR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Fill the Tx FIFO with as many words as possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) n_words++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) } while (!(sr & XSPI_SR_TX_FULL_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return n_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const struct of_device_id xilinx_spi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { .compatible = "xlnx,axi-quad-spi-1.00.a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { .compatible = "xlnx,xps-spi-2.00.a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { .compatible = "xlnx,xps-spi-2.00.b", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int xilinx_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct xilinx_spi *xspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct xspi_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int ret, num_cs = 0, bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) num_cs = pdata->num_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) bits_per_word = pdata->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) &num_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ret = of_property_read_u32(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) "xlnx,num-transfer-bits",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) &bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (!num_cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "Missing slave select configuration data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (num_cs > XILINX_SPI_MAX_CS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_err(&pdev->dev, "Invalid number of spi slaves\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* the spi->mode bits understood by this driver: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) xspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) xspi->cs_inactive = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) xspi->bitbang.master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) xspi->bitbang.chipselect = xilinx_spi_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) init_completion(&xspi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) xspi->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (IS_ERR(xspi->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ret = PTR_ERR(xspi->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) goto put_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) master->bus_num = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) master->num_chipselect = num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * Detect endianess on the IP via loop bit in CR. Detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * must be done before reset is sent because incorrect reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * value generates error interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * Setup little endian helper functions first and try to use them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * and check if bit was correctly setup or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) xspi->read_fn = xspi_read32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) xspi->write_fn = xspi_write32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) tmp &= XSPI_CR_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (tmp != XSPI_CR_LOOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) xspi->read_fn = xspi_read32_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) xspi->write_fn = xspi_write32_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) xspi->bytes_per_word = bits_per_word / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) xspi->buffer_size = xilinx_spi_find_buffer_size(xspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) xspi->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (xspi->irq < 0 && xspi->irq != -ENXIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = xspi->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) goto put_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) } else if (xspi->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Register for SPI Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_name(&pdev->dev), xspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) goto put_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* SPI controller initializations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) xspi_init_hw(xspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = spi_bitbang_start(&xspi->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) goto put_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dev_info(&pdev->dev, "at %pR, irq=%d\n", res, xspi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) for (i = 0; i < pdata->num_devices; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) spi_new_device(master, pdata->devices + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) put_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int xilinx_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct xilinx_spi *xspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) void __iomem *regs_base = xspi->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) spi_bitbang_stop(&xspi->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Disable all the interrupts just in case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* Disable the global IPIF interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) spi_master_put(xspi->bitbang.master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* work with hotplug and coldplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) MODULE_ALIAS("platform:" XILINX_SPI_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static struct platform_driver xilinx_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .probe = xilinx_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .remove = xilinx_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .name = XILINX_SPI_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .of_match_table = xilinx_spi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) module_platform_driver(xilinx_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) MODULE_DESCRIPTION("Xilinx SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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