^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Analog Devices AD-FMCOMMS1-EBZ board I2C-SPI bridge driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2012 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Lars-Peter Clausen <lars@metafoo.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SPI_XCOMM_SETTINGS_LEN_OFFSET 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SPI_XCOMM_SETTINGS_3WIRE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SPI_XCOMM_SETTINGS_CS_HIGH BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SPI_XCOMM_SETTINGS_SAMPLE_END BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SPI_XCOMM_SETTINGS_CPHA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SPI_XCOMM_SETTINGS_CPOL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPI_XCOMM_SETTINGS_CLOCK_DIV_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SPI_XCOMM_SETTINGS_CLOCK_DIV_64 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPI_XCOMM_SETTINGS_CLOCK_DIV_16 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPI_XCOMM_SETTINGS_CLOCK_DIV_4 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPI_XCOMM_CMD_UPDATE_CONFIG 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPI_XCOMM_CMD_WRITE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPI_XCOMM_CLOCK 48000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct spi_xcomm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct i2c_client *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) uint16_t settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) uint16_t chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int current_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) uint8_t buf[63];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int spi_xcomm_sync_config(struct spi_xcomm *spi_xcomm, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) uint16_t settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) uint8_t *buf = spi_xcomm->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) settings = spi_xcomm->settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) settings |= len << SPI_XCOMM_SETTINGS_LEN_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) buf[0] = SPI_XCOMM_CMD_UPDATE_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) put_unaligned_be16(settings, &buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) put_unaligned_be16(spi_xcomm->chipselect, &buf[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return i2c_master_send(spi_xcomm->i2c, buf, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void spi_xcomm_chipselect(struct spi_xcomm *spi_xcomm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct spi_device *spi, int is_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned long cs = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) uint16_t chipselect = spi_xcomm->chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (is_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) chipselect |= BIT(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) chipselect &= ~BIT(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) spi_xcomm->chipselect = chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int spi_xcomm_setup_transfer(struct spi_xcomm *spi_xcomm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct spi_device *spi, struct spi_transfer *t, unsigned int *settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (t->len > 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (t->speed_hz != spi_xcomm->current_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) divider = DIV_ROUND_UP(SPI_XCOMM_CLOCK, t->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (divider >= 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *settings |= SPI_XCOMM_SETTINGS_CLOCK_DIV_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) else if (divider >= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *settings |= SPI_XCOMM_SETTINGS_CLOCK_DIV_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *settings |= SPI_XCOMM_SETTINGS_CLOCK_DIV_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) spi_xcomm->current_speed = t->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *settings |= SPI_XCOMM_SETTINGS_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *settings &= ~SPI_XCOMM_SETTINGS_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *settings &= ~SPI_XCOMM_SETTINGS_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *settings |= SPI_XCOMM_SETTINGS_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (spi->mode & SPI_3WIRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *settings |= SPI_XCOMM_SETTINGS_3WIRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *settings &= ~SPI_XCOMM_SETTINGS_3WIRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int spi_xcomm_txrx_bufs(struct spi_xcomm *spi_xcomm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct spi_device *spi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (t->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) spi_xcomm->buf[0] = SPI_XCOMM_CMD_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) memcpy(spi_xcomm->buf + 1, t->tx_buf, t->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ret = i2c_master_send(spi_xcomm->i2c, spi_xcomm->buf, t->len + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) else if (ret != t->len + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) } else if (t->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ret = i2c_master_recv(spi_xcomm->i2c, t->rx_buf, t->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) else if (ret != t->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int spi_xcomm_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct spi_xcomm *spi_xcomm = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned int settings = spi_xcomm->settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct spi_device *spi = msg->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned cs_change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct spi_transfer *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) bool is_first = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) bool is_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) spi_xcomm_chipselect(spi_xcomm, spi, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) list_for_each_entry(t, &msg->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (!t->tx_buf && !t->rx_buf && t->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) status = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) status = spi_xcomm_setup_transfer(spi_xcomm, spi, t, &settings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) is_last = list_is_last(&t->transfer_list, &msg->transfers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) cs_change = t->cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (cs_change ^ is_last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) settings |= BIT(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) settings &= ~BIT(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (t->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) spi_xcomm->settings = settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) status = spi_xcomm_sync_config(spi_xcomm, t->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) } else if (settings != spi_xcomm->settings || is_first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) spi_xcomm->settings = settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) status = spi_xcomm_sync_config(spi_xcomm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (t->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) status = spi_xcomm_txrx_bufs(spi_xcomm, spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (status > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) msg->actual_length += status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) spi_transfer_delay_exec(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) is_first = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (status != 0 || !cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) spi_xcomm_chipselect(spi_xcomm, spi, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) msg->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) spi_finalize_current_message(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int spi_xcomm_probe(struct i2c_client *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct spi_xcomm *spi_xcomm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) master = spi_alloc_master(&i2c->dev, sizeof(*spi_xcomm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) spi_xcomm = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) spi_xcomm->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) master->num_chipselect = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_3WIRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) master->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) master->flags = SPI_MASTER_HALF_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) master->transfer_one_message = spi_xcomm_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) master->dev.of_node = i2c->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) i2c_set_clientdata(i2c, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ret = devm_spi_register_master(&i2c->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const struct i2c_device_id spi_xcomm_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { "spi-xcomm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MODULE_DEVICE_TABLE(i2c, spi_xcomm_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct i2c_driver spi_xcomm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .name = "spi-xcomm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .id_table = spi_xcomm_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .probe = spi_xcomm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) module_i2c_driver(spi_xcomm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MODULE_DESCRIPTION("Analog Devices AD-FMCOMMS1-EBZ board I2C-SPI bridge driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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