^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * TXx9 SPI controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Based on linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2000-2001 Toshiba Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * terms of the GNU General Public License version 2. This program is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Convert to generic SPI framework - Atsushi Nemoto (anemo@mba.ocn.ne.jp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPI_FIFO_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPI_MAX_DIVIDER 0xff /* Max. value for SPCR1.SER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPI_MIN_DIVIDER 1 /* Min. value for SPCR1.SER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TXx9_SPMCR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TXx9_SPCR0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TXx9_SPCR1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TXx9_SPFS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TXx9_SPSR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TXx9_SPDR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* SPMCR : SPI Master Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TXx9_SPMCR_OPMODE 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TXx9_SPMCR_CONFIG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TXx9_SPMCR_ACTIVE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TXx9_SPMCR_SPSTP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TXx9_SPMCR_BCLR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* SPCR0 : SPI Control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TXx9_SPCR0_TXIFL_MASK 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TXx9_SPCR0_RXIFL_MASK 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TXx9_SPCR0_SIDIE 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TXx9_SPCR0_SOEIE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TXx9_SPCR0_RBSIE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TXx9_SPCR0_TBSIE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TXx9_SPCR0_IFSPSE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TXx9_SPCR0_SBOS 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TXx9_SPCR0_SPHA 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TXx9_SPCR0_SPOL 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* SPSR : SPI Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TXx9_SPSR_TBSI 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TXx9_SPSR_RBSI 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TXx9_SPSR_TBS_MASK 0x3800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TXx9_SPSR_RBS_MASK 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TXx9_SPSR_SPOE 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TXx9_SPSR_IFSD 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TXx9_SPSR_SIDLE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TXx9_SPSR_STRDY 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TXx9_SPSR_SRRDY 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct txx9spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) spinlock_t lock; /* protect 'queue' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) wait_queue_head_t waitq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int baseclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct gpio_desc *last_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int last_chipselect_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static u32 txx9spi_rd(struct txx9spi *c, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return __raw_readl(c->membase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void txx9spi_wr(struct txx9spi *c, u32 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __raw_writel(val, c->membase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void txx9spi_cs_func(struct spi_device *spi, struct txx9spi *c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int on, unsigned int cs_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * The GPIO descriptor will track polarity inversion inside
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * gpiolib.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* deselect the chip with cs_change hint in last transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (c->last_chipselect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) gpiod_set_value(c->last_chipselect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) !c->last_chipselect_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) c->last_chipselect = spi->cs_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) c->last_chipselect_val = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) c->last_chipselect = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ndelay(cs_delay); /* CS Hold Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) gpiod_set_value(spi->cs_gpiod, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ndelay(cs_delay); /* CS Setup Time / CS Recovery Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int txx9spi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct txx9spi *c = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (!spi->max_speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* deselect chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) spin_lock(&c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) txx9spi_cs_func(spi, c, 0, (NSEC_PER_SEC / 2) / spi->max_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) spin_unlock(&c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static irqreturn_t txx9spi_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct txx9spi *c = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* disable rx intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) txx9spi_wr(c, txx9spi_rd(c, TXx9_SPCR0) & ~TXx9_SPCR0_RBSIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) TXx9_SPCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) wake_up(&c->waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void txx9spi_work_one(struct txx9spi *c, struct spi_message *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct spi_device *spi = m->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct spi_transfer *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int cs_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int cs_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 prev_speed_hz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u8 prev_bits_per_word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* CS setup/hold/recovery time in nsec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) cs_delay = 100 + (NSEC_PER_SEC / 2) / spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) mcr = txx9spi_rd(c, TXx9_SPMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (unlikely((mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dev_err(&spi->dev, "Bad mode.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* enter config mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) txx9spi_wr(c, TXx9_SPCR0_SBOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) | ((spi->mode & SPI_CPOL) ? TXx9_SPCR0_SPOL : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) | ((spi->mode & SPI_CPHA) ? TXx9_SPCR0_SPHA : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) | 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) TXx9_SPCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) list_for_each_entry(t, &m->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) const void *txbuf = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) void *rxbuf = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int len = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int wsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 speed_hz = t->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u8 bits_per_word = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) wsize = bits_per_word >> 3; /* in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (prev_speed_hz != speed_hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) || prev_bits_per_word != bits_per_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int n = DIV_ROUND_UP(c->baseclk, speed_hz) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) n = clamp(n, SPI_MIN_DIVIDER, SPI_MAX_DIVIDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* enter config mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) TXx9_SPMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) txx9spi_wr(c, (n << 8) | bits_per_word, TXx9_SPCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* enter active mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) txx9spi_wr(c, mcr | TXx9_SPMCR_ACTIVE, TXx9_SPMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) prev_speed_hz = speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) prev_bits_per_word = bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) txx9spi_cs_func(spi, c, 1, cs_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) cs_change = t->cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned int count = SPI_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 cr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (len < count * wsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) count = len / wsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* now tx must be idle... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) while (!(txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_SIDLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) cr0 = txx9spi_rd(c, TXx9_SPCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) cr0 &= ~TXx9_SPCR0_RXIFL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) cr0 |= (count - 1) << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* enable rx intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) cr0 |= TXx9_SPCR0_RBSIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) txx9spi_wr(c, cr0, TXx9_SPCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (txbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) data = (wsize == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ? *(const u8 *)txbuf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) : *(const u16 *)txbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) txx9spi_wr(c, data, TXx9_SPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) txbuf += wsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) txx9spi_wr(c, 0, TXx9_SPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* wait all rx data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) wait_event(c->waitq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_RBSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) data = txx9spi_rd(c, TXx9_SPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (rxbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (wsize == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *(u8 *)rxbuf = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) *(u16 *)rxbuf = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) rxbuf += wsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) len -= count * wsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) m->actual_length += t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) spi_transfer_delay_exec(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (!cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (t->transfer_list.next == &m->transfers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* sometimes a short mid-message deselect of the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * may be needed to terminate a mode or command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) txx9spi_cs_func(spi, c, 0, cs_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) m->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (m->complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) m->complete(m->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* normally deactivate chipselect ... unless no error and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * cs_change has hinted that the next message will probably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * be for this chip too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (!(status == 0 && cs_change))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) txx9spi_cs_func(spi, c, 0, cs_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* enter config mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void txx9spi_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct txx9spi *c = container_of(work, struct txx9spi, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) spin_lock_irqsave(&c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) while (!list_empty(&c->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct spi_message *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) m = container_of(c->queue.next, struct spi_message, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) list_del_init(&m->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) spin_unlock_irqrestore(&c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) txx9spi_work_one(c, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) spin_lock_irqsave(&c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) spin_unlock_irqrestore(&c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int txx9spi_transfer(struct spi_device *spi, struct spi_message *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct spi_master *master = spi->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct txx9spi *c = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct spi_transfer *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) m->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* check each transfer's parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) list_for_each_entry(t, &m->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (!t->tx_buf && !t->rx_buf && t->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) spin_lock_irqsave(&c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) list_add_tail(&m->queue, &c->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) schedule_work(&c->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) spin_unlock_irqrestore(&c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Chip select uses GPIO only, further the driver is using the chip select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * numer (from the device tree "reg" property, and this can only come from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * device tree since this i MIPS and there is no way to pass platform data) as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * the GPIO number. As the platform has only one GPIO controller (the txx9 GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * chip) it is thus using the chip select number as an offset into that chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * This chip has a maximum of 16 GPIOs 0..15 and this is what all platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * We modernized this behaviour by explicitly converting that offset to an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * offset on the GPIO chip using a GPIO descriptor machine table of the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * size as the txx9 GPIO chip with a 1-to-1 mapping of chip select to GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * This is admittedly a hack, but it is countering the hack of using "reg" to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * contain a GPIO offset when it should be using "cs-gpios" as the SPI bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static struct gpiod_lookup_table txx9spi_cs_gpio_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .dev_id = "spi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) GPIO_LOOKUP_IDX("TXx9", 0, "cs", 0, GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) GPIO_LOOKUP_IDX("TXx9", 1, "cs", 1, GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) GPIO_LOOKUP_IDX("TXx9", 2, "cs", 2, GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) GPIO_LOOKUP_IDX("TXx9", 3, "cs", 3, GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) GPIO_LOOKUP_IDX("TXx9", 4, "cs", 4, GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) GPIO_LOOKUP_IDX("TXx9", 5, "cs", 5, GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) GPIO_LOOKUP_IDX("TXx9", 6, "cs", 6, GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) GPIO_LOOKUP_IDX("TXx9", 7, "cs", 7, GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) GPIO_LOOKUP_IDX("TXx9", 8, "cs", 8, GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) GPIO_LOOKUP_IDX("TXx9", 9, "cs", 9, GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) GPIO_LOOKUP_IDX("TXx9", 10, "cs", 10, GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) GPIO_LOOKUP_IDX("TXx9", 11, "cs", 11, GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) GPIO_LOOKUP_IDX("TXx9", 12, "cs", 12, GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) GPIO_LOOKUP_IDX("TXx9", 13, "cs", 13, GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) GPIO_LOOKUP_IDX("TXx9", 14, "cs", 14, GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) GPIO_LOOKUP_IDX("TXx9", 15, "cs", 15, GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int txx9spi_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct txx9spi *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) master = spi_alloc_master(&dev->dev, sizeof(*c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) c = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) platform_set_drvdata(dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) INIT_WORK(&c->work, txx9spi_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) spin_lock_init(&c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) INIT_LIST_HEAD(&c->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) init_waitqueue_head(&c->waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) c->clk = devm_clk_get(&dev->dev, "spi-baseclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (IS_ERR(c->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ret = PTR_ERR(c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) c->clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = clk_prepare_enable(c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) c->clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) c->baseclk = clk_get_rate(c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) master->min_speed_hz = DIV_ROUND_UP(c->baseclk, SPI_MAX_DIVIDER + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) master->max_speed_hz = c->baseclk / (SPI_MIN_DIVIDER + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) res = platform_get_resource(dev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) c->membase = devm_ioremap_resource(&dev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (IS_ERR(c->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) goto exit_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* enter config mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) mcr = txx9spi_rd(c, TXx9_SPMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) irq = platform_get_irq(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) goto exit_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret = devm_request_irq(&dev->dev, irq, txx9spi_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "spi_txx9", c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) c->last_chipselect = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dev_info(&dev->dev, "at %#llx, irq %d, %dMHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) (unsigned long long)res->start, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) (c->baseclk + 500000) / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) gpiod_add_lookup_table(&txx9spi_cs_gpio_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* the spi->mode bits understood by this driver: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) master->bus_num = dev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) master->setup = txx9spi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) master->transfer = txx9spi_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) master->num_chipselect = (u16)UINT_MAX; /* any GPIO numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) master->use_gpio_descriptors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = devm_spi_register_master(&dev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) exit_busy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) clk_disable_unprepare(c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int txx9spi_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct spi_master *master = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct txx9spi *c = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) flush_work(&c->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) clk_disable_unprepare(c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* work with hotplug and coldplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MODULE_ALIAS("platform:spi_txx9");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static struct platform_driver txx9spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .probe = txx9spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .remove = txx9spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .name = "spi_txx9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int __init txx9spi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return platform_driver_register(&txx9spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) subsys_initcall(txx9spi_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static void __exit txx9spi_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) platform_driver_unregister(&txx9spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) module_exit(txx9spi_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MODULE_DESCRIPTION("TXx9 SPI Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags