^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SPI bus driver for the Topcliff PCH used by Intel SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spi/spidev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pch_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCH_SPCR 0x00 /* SPI control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCH_SPBRR 0x04 /* SPI baud rate register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCH_SPSR 0x08 /* SPI status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCH_SPDWR 0x0C /* SPI write data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCH_SPDRR 0x10 /* SPI read data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCH_SSNXCR 0x18 /* SSN Expand Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCH_SRST 0x1C /* SPI reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCH_ADDRESS_SIZE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCH_SPSR_TFD 0x000007C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCH_SPSR_RFD 0x0000F800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCH_RX_THOLD 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCH_RX_THOLD_MAX 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCH_TX_THOLD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCH_MAX_BAUDRATE 5000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCH_MAX_FIFO_DEPTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define STATUS_RUNNING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define STATUS_EXITING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCH_SLEEP_TIME 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SSN_LOW 0x02U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SSN_HIGH 0x03U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SSN_NO_CONTROL 0x00U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCH_MAX_CS 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PCI_DEVICE_ID_GE_SPI 0x8816
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPCR_SPE_BIT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPCR_MSTR_BIT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPCR_LSBF_BIT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPCR_CPHA_BIT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPCR_CPOL_BIT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SPCR_TFIE_BIT (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPCR_RFIE_BIT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SPCR_FIE_BIT (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPCR_ORIE_BIT (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPCR_MDFIE_BIT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SPCR_FICLR_BIT (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPSR_TFI_BIT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SPSR_RFI_BIT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SPSR_FI_BIT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SPSR_ORF_BIT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SPBRR_SIZE_BIT (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SPCR_RFIC_FIELD 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SPCR_TFIC_FIELD 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCH_CLOCK_HZ 50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PCH_MAX_SPBR 1023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PCI_DEVICE_ID_ML7213_SPI 0x802c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PCI_DEVICE_ID_ML7223_SPI 0x800F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PCI_DEVICE_ID_ML7831_SPI 0x8816
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Set the number of SPI instance max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Intel EG20T PCH : 1ch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * LAPIS Semiconductor ML7213 IOH : 2ch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * LAPIS Semiconductor ML7223 IOH : 1ch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * LAPIS Semiconductor ML7831 IOH : 1ch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PCH_SPI_MAX_DEV 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCH_BUF_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PCH_DMA_TRANS_SIZE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int use_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct pch_spi_dma_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct dma_async_tx_descriptor *desc_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct dma_async_tx_descriptor *desc_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct pch_dma_slave param_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct pch_dma_slave param_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct dma_chan *chan_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct dma_chan *chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct scatterlist *sg_tx_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct scatterlist *sg_rx_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct scatterlist sg_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct scatterlist sg_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int nent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void *tx_buf_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void *rx_buf_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dma_addr_t tx_buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dma_addr_t rx_buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * struct pch_spi_data - Holds the SPI channel specific details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @io_remap_addr: The remapped PCI base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @io_base_addr: Base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @master: Pointer to the SPI master structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @work: Reference to work queue handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @wait: Wait queue for waking up upon receiving an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @transfer_complete: Status of SPI Transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @bcurrent_msg_processing: Status flag for message processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @lock: Lock for protecting this structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @queue: SPI Message queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @status: Status of the SPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @bpw_len: Length of data to be transferred in bits per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @transfer_active: Flag showing active transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @tx_index: Transmit data count; for bookkeeping during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @rx_index: Receive data count; for bookkeeping during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @pkt_tx_buff: Buffer for data to be transmitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @pkt_rx_buff: Buffer for received data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @n_curnt_chip: The chip number that this SPI driver currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * operates on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @current_chip: Reference to the current chip that this SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * driver currently operates on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @current_msg: The current message that this SPI driver is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @cur_trans: The current transfer that this SPI driver is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @board_dat: Reference to the SPI device data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @plat_dev: platform_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @ch: SPI channel number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @dma: Local DMA information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @use_dma: True if DMA is to be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @irq_reg_sts: Status of IRQ registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @save_total_len: Save length while data is being transferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct pch_spi_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) void __iomem *io_remap_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned long io_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) wait_queue_head_t wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 transfer_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u8 bcurrent_msg_processing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 bpw_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u8 transfer_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 tx_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 rx_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u16 *pkt_tx_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u16 *pkt_rx_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u8 n_curnt_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct spi_device *current_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct spi_message *current_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct spi_transfer *cur_trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct pch_spi_board_data *board_dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct platform_device *plat_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct pch_spi_dma_ctrl dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int use_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u8 irq_reg_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int save_total_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * struct pch_spi_board_data - Holds the SPI device specific details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @pdev: Pointer to the PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @suspend_sts: Status of suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @num: The number of SPI device instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct pch_spi_board_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 suspend_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct pch_pd_dev_save {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct platform_device *pd_save[PCH_SPI_MAX_DEV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct pch_spi_board_data *board_dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const struct pci_device_id pch_spi_pcidev_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * pch_spi_writereg() - Performs register writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @master: Pointer to struct spi_master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @idx: Register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @val: Value to be written to register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct pch_spi_data *data = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) iowrite32(val, (data->io_remap_addr + idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * pch_spi_readreg() - Performs register reads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @master: Pointer to struct spi_master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * @idx: Register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct pch_spi_data *data = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ioread32(data->io_remap_addr + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 set, u32 clr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 tmp = pch_spi_readreg(master, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) tmp = (tmp & ~clr) | set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pch_spi_writereg(master, idx, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void pch_spi_set_master_mode(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @master: Pointer to struct spi_master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void pch_spi_clear_fifo(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) void __iomem *io_remap_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 n_read, tx_index, rx_index, bpw_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u16 *pkt_rx_buffer, *pkt_tx_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int read_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 reg_spcr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) void __iomem *spsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) void __iomem *spdrr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) void __iomem *spdwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) spsr = io_remap_addr + PCH_SPSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) iowrite32(reg_spsr_val, spsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (data->transfer_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) rx_index = data->rx_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) tx_index = data->tx_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) bpw_len = data->bpw_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pkt_rx_buffer = data->pkt_rx_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pkt_tx_buff = data->pkt_tx_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) spdrr = io_remap_addr + PCH_SPDRR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) spdwr = io_remap_addr + PCH_SPDWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) n_read = PCH_READABLE(reg_spsr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) pkt_rx_buffer[rx_index++] = ioread32(spdrr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (tx_index < bpw_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) iowrite32(pkt_tx_buff[tx_index++], spdwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* disable RFI if not needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* reset rx threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* update counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) data->tx_index = tx_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) data->rx_index = rx_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* if transfer complete interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (reg_spsr_val & SPSR_FI_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if ((tx_index == bpw_len) && (rx_index == tx_index)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PCH_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* transfer is completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) inform pch_spi_process_messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) data->transfer_complete = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) data->transfer_active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) wake_up(&data->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dev_vdbg(&data->master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) "%s : Transfer is not completed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * pch_spi_handler() - Interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * @irq: The interrupt number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * @dev_id: Pointer to struct pch_spi_board_data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static irqreturn_t pch_spi_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 reg_spsr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) void __iomem *spsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) void __iomem *io_remap_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct pch_spi_data *data = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct pch_spi_board_data *board_dat = data->board_dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (board_dat->suspend_sts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dev_dbg(&board_dat->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "%s returning due to suspend\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) io_remap_addr = data->io_remap_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) spsr = io_remap_addr + PCH_SPSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) reg_spsr_val = ioread32(spsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (reg_spsr_val & SPSR_ORF_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (data->current_msg->complete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) data->transfer_complete = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) data->current_msg->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) data->current_msg->complete(data->current_msg->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) data->bcurrent_msg_processing = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) data->current_msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) data->cur_trans = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (data->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Check if the interrupt is for SPI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * @master: Pointer to struct spi_master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * @speed_hz: Baud rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* if baud rate is less than we can support limit it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (n_spbr > PCH_MAX_SPBR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) n_spbr = PCH_MAX_SPBR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * @master: Pointer to struct spi_master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * @bits_per_word: Bits per word for SPI transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static void pch_spi_set_bits_per_word(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u8 bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (bits_per_word == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * @spi: Pointer to struct spi_device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static void pch_spi_setup_transfer(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) spi->max_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* set bits per word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (!(spi->mode & SPI_LSB_FIRST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) flags |= SPCR_LSBF_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) flags |= SPCR_CPOL_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) flags |= SPCR_CPHA_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Clear the FIFO by toggling FICLR to 1 and back to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pch_spi_clear_fifo(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * pch_spi_reset() - Clears SPI registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * @master: Pointer to struct spi_master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static void pch_spi_reset(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* write 1 to reset SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) pch_spi_writereg(master, PCH_SRST, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* clear reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pch_spi_writereg(master, PCH_SRST, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct spi_transfer *transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) spin_lock_irqsave(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* validate Tx/Rx buffers and Transfer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (!transfer->tx_buf && !transfer->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev_err(&pspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "%s Tx and Rx buffer NULL\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) goto err_return_spinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (!transfer->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_err(&pspi->dev, "%s Transfer length invalid\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) goto err_return_spinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_dbg(&pspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) "%s Tx/Rx buffer valid. Transfer length valid\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) spin_unlock_irqrestore(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* We won't process any messages if we have been asked to terminate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (data->status == STATUS_EXITING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) retval = -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* If suspended ,return -EINVAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (data->board_dat->suspend_sts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* set status of message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pmsg->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) pmsg->status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) spin_lock_irqsave(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* add message to queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) list_add_tail(&pmsg->queue, &data->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) spin_unlock_irqrestore(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) schedule_work(&data->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) err_return_spinlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) spin_unlock_irqrestore(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static inline void pch_spi_select_chip(struct pch_spi_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct spi_device *pspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (data->current_chip != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (pspi->chip_select != data->n_curnt_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) data->current_chip = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) data->current_chip = pspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) data->n_curnt_chip = data->current_chip->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pch_spi_setup_transfer(pspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u32 n_writes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct spi_message *pmsg, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) const u8 *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) const u16 *tx_sbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* set baud rate if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (data->cur_trans->speed_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* set bits per word if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (data->cur_trans->bits_per_word &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) pch_spi_set_bits_per_word(data->master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) data->cur_trans->bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) *bpw = data->cur_trans->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) *bpw = data->current_msg->spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* reset Tx/Rx index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) data->tx_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) data->rx_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) data->bpw_len = data->cur_trans->len / (*bpw / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* find alloc size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (data->pkt_tx_buff != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (!data->pkt_rx_buff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) kfree(data->pkt_tx_buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) data->pkt_tx_buff = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (!data->pkt_rx_buff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* flush queue and set status of all transfers to -ENOMEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pmsg->status = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (pmsg->complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) pmsg->complete(pmsg->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* delete from queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) list_del_init(&pmsg->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* copy Tx Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (data->cur_trans->tx_buf != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (*bpw == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) tx_buf = data->cur_trans->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) for (j = 0; j < data->bpw_len; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) data->pkt_tx_buff[j] = *tx_buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) tx_sbuf = data->cur_trans->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) for (j = 0; j < data->bpw_len; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) data->pkt_tx_buff[j] = *tx_sbuf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) n_writes = data->bpw_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (n_writes > PCH_MAX_FIFO_DEPTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) n_writes = PCH_MAX_FIFO_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) dev_dbg(&data->master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) "\n%s:Pulling down SSN low - writing 0x2 to SSNXCR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) for (j = 0; j < n_writes; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* update tx_index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) data->tx_index = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* reset transfer complete flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) data->transfer_complete = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) data->transfer_active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static void pch_spi_nomore_transfer(struct pch_spi_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct spi_message *pmsg, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) dev_dbg(&data->master->dev, "%s called\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Invoke complete callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * [To the spi core..indicating end of transfer] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) data->current_msg->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (data->current_msg->complete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev_dbg(&data->master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) "%s:Invoking callback of SPI core\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) data->current_msg->complete(data->current_msg->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* update status in global variable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) data->bcurrent_msg_processing = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dev_dbg(&data->master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) "%s:data->bcurrent_msg_processing = false\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) data->current_msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) data->cur_trans = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* check if we have items in list and not suspending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * return 1 if list empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if ((list_empty(&data->queue) == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) (!data->board_dat->suspend_sts) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) (data->status != STATUS_EXITING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* We have some more work to do (either there is more tranint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * bpw;sfer requests in the current message or there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) *more messages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) schedule_work(&data->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) } else if (data->board_dat->suspend_sts ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) data->status == STATUS_EXITING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dev_dbg(&data->master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) "%s suspend/remove initiated, flushing queue\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) pmsg->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (pmsg->complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) pmsg->complete(pmsg->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* delete from queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) list_del_init(&pmsg->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static void pch_spi_set_ir(struct pch_spi_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* enable interrupts, set threshold, enable SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* set receive threshold to PCH_RX_THOLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) pch_spi_setclr_reg(data->master, PCH_SPCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PCH_RX_THOLD << SPCR_RFIC_FIELD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) SPCR_FIE_BIT | SPCR_RFIE_BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) SPCR_ORIE_BIT | SPCR_SPE_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) MASK_RFIC_SPCR_BITS | PCH_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* set receive threshold to maximum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) pch_spi_setclr_reg(data->master, PCH_SPCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) SPCR_FIE_BIT | SPCR_ORIE_BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) SPCR_SPE_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) MASK_RFIC_SPCR_BITS | PCH_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* Wait until the transfer completes; go to sleep after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) initiating the transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) dev_dbg(&data->master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) "%s:waiting for transfer to get over\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) wait_event_interruptible(data->wait, data->transfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* clear all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) pch_spi_writereg(data->master, PCH_SPSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) pch_spi_readreg(data->master, PCH_SPSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* Disable interrupts and SPI transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* clear FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) pch_spi_clear_fifo(data->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u8 *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u16 *rx_sbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* copy Rx Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (!data->cur_trans->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (bpw == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) rx_buf = data->cur_trans->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) for (j = 0; j < data->bpw_len; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) rx_sbuf = data->cur_trans->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) for (j = 0; j < data->bpw_len; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) *rx_sbuf++ = data->pkt_rx_buff[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u8 *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) u16 *rx_sbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) const u8 *rx_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) const u16 *rx_dma_sbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* copy Rx Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (!data->cur_trans->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (bpw == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) rx_buf = data->cur_trans->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) rx_dma_buf = data->dma.rx_buf_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) for (j = 0; j < data->bpw_len; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) *rx_buf++ = *rx_dma_buf++ & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) data->cur_trans->rx_buf = rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) rx_sbuf = data->cur_trans->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) rx_dma_sbuf = data->dma.rx_buf_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) for (j = 0; j < data->bpw_len; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) *rx_sbuf++ = *rx_dma_sbuf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) data->cur_trans->rx_buf = rx_sbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int pch_spi_start_transfer(struct pch_spi_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct pch_spi_dma_ctrl *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) int rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dma = &data->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) spin_lock_irqsave(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* disable interrupts, SPI set enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) spin_unlock_irqrestore(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* Wait until the transfer completes; go to sleep after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) initiating the transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dev_dbg(&data->master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) "%s:waiting for transfer to get over\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) rtn = wait_event_interruptible_timeout(data->wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) data->transfer_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) msecs_to_jiffies(2 * HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (!rtn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dev_err(&data->master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) "%s wait-event timeout\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) async_tx_ack(dma->desc_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) async_tx_ack(dma->desc_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) kfree(dma->sg_tx_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) kfree(dma->sg_rx_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) spin_lock_irqsave(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* clear fifo threshold, disable interrupts, disable SPI transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) SPCR_SPE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* clear all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) pch_spi_writereg(data->master, PCH_SPSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) pch_spi_readreg(data->master, PCH_SPSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* clear FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) pch_spi_clear_fifo(data->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) spin_unlock_irqrestore(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return rtn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static void pch_dma_rx_complete(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct pch_spi_data *data = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* transfer is completed;inform pch_spi_process_messages_dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) data->transfer_complete = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) wake_up_interruptible(&data->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static bool pch_spi_filter(struct dma_chan *chan, void *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct pch_dma_slave *param = slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if ((chan->chan_id == param->chan_id) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) (param->dma_dev == chan->device->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) chan->private = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct pci_dev *dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct pch_dma_slave *param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct pch_spi_dma_ctrl *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) unsigned int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (bpw == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) width = PCH_DMA_WIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) width = PCH_DMA_WIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) dma = &data->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) dma_cap_set(DMA_SLAVE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* Get DMA's dev information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dma_dev = pci_get_slot(data->board_dat->pdev->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) PCI_DEVFN(PCI_SLOT(data->board_dat->pdev->devfn), 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* Set Tx DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) param = &dma->param_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) param->dma_dev = &dma_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) param->chan_id = data->ch * 2; /* Tx = 0, 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) param->tx_reg = data->io_base_addr + PCH_SPDWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) param->width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) chan = dma_request_channel(mask, pch_spi_filter, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (!chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dev_err(&data->master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) "ERROR: dma_request_channel FAILS(Tx)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) data->use_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) dma->chan_tx = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* Set Rx DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) param = &dma->param_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) param->dma_dev = &dma_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) param->chan_id = data->ch * 2 + 1; /* Rx = Tx + 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) param->rx_reg = data->io_base_addr + PCH_SPDRR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) param->width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) chan = dma_request_channel(mask, pch_spi_filter, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (!chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dev_err(&data->master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) "ERROR: dma_request_channel FAILS(Rx)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) dma_release_channel(dma->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) dma->chan_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) data->use_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dma->chan_rx = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static void pch_spi_release_dma(struct pch_spi_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct pch_spi_dma_ctrl *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) dma = &data->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (dma->chan_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) dma_release_channel(dma->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) dma->chan_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (dma->chan_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) dma_release_channel(dma->chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) dma->chan_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) const u8 *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) const u16 *tx_sbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) u8 *tx_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) u16 *tx_dma_sbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct dma_async_tx_descriptor *desc_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct dma_async_tx_descriptor *desc_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) int rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) int head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct pch_spi_dma_ctrl *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) dma = &data->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* set baud rate if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (data->cur_trans->speed_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) spin_lock_irqsave(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) spin_unlock_irqrestore(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* set bits per word if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (data->cur_trans->bits_per_word &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) (data->current_msg->spi->bits_per_word !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) data->cur_trans->bits_per_word)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) spin_lock_irqsave(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) pch_spi_set_bits_per_word(data->master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) data->cur_trans->bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) spin_unlock_irqrestore(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) *bpw = data->cur_trans->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) *bpw = data->current_msg->spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) data->bpw_len = data->cur_trans->len / (*bpw / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (data->bpw_len > PCH_BUF_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) data->bpw_len = PCH_BUF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) data->cur_trans->len -= PCH_BUF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* copy Tx Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (data->cur_trans->tx_buf != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (*bpw == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) tx_buf = data->cur_trans->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) tx_dma_buf = dma->tx_buf_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) for (i = 0; i < data->bpw_len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) *tx_dma_buf++ = *tx_buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) tx_sbuf = data->cur_trans->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) tx_dma_sbuf = dma->tx_buf_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) for (i = 0; i < data->bpw_len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) *tx_dma_sbuf++ = *tx_sbuf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* Calculate Rx parameter for DMA transmitting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (data->bpw_len % PCH_DMA_TRANS_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) num = data->bpw_len / PCH_DMA_TRANS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) rem = PCH_DMA_TRANS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) size = PCH_DMA_TRANS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) size = data->bpw_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) rem = data->bpw_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) __func__, num, size, rem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) spin_lock_irqsave(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* set receive fifo threshold and transmit fifo threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) pch_spi_setclr_reg(data->master, PCH_SPCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ((size - 1) << SPCR_RFIC_FIELD) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) (PCH_TX_THOLD << SPCR_TFIC_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) spin_unlock_irqrestore(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) dma->sg_rx_p = kmalloc_array(num, sizeof(*dma->sg_rx_p), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (!dma->sg_rx_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* offset, length setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) sg = dma->sg_rx_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) for (i = 0; i < num; i++, sg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (i == (num - 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) sg->offset = size * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) sg->offset = sg->offset * (*bpw / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) sg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) sg_dma_len(sg) = rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) } else if (i == (num - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) sg->offset = size * (i - 1) + rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) sg->offset = sg->offset * (*bpw / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) sg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) sg_dma_len(sg) = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) sg->offset = size * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) sg->offset = sg->offset * (*bpw / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) sg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) sg_dma_len(sg) = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) sg = dma->sg_rx_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) num, DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (!desc_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) dev_err(&data->master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) "%s:dmaengine_prep_slave_sg Failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) desc_rx->callback = pch_dma_rx_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) desc_rx->callback_param = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) dma->nent = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) dma->desc_rx = desc_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* Calculate Tx parameter for DMA transmitting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (data->bpw_len > PCH_MAX_FIFO_DEPTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) num = data->bpw_len / PCH_DMA_TRANS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) rem = data->bpw_len % PCH_DMA_TRANS_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) PCH_DMA_TRANS_SIZE - head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) size = PCH_DMA_TRANS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) size = data->bpw_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) rem = data->bpw_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) dma->sg_tx_p = kmalloc_array(num, sizeof(*dma->sg_tx_p), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (!dma->sg_tx_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /* offset, length setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) sg = dma->sg_tx_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) for (i = 0; i < num; i++, sg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) sg->offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) sg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) sg_dma_len(sg) = size + head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) } else if (i == (num - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) sg->offset = head + size * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) sg->offset = sg->offset * (*bpw / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) sg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) sg_dma_len(sg) = rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) sg->offset = head + size * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) sg->offset = sg->offset * (*bpw / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) sg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) sg_dma_len(sg) = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) sg = dma->sg_tx_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) desc_tx = dmaengine_prep_slave_sg(dma->chan_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) sg, num, DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (!desc_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) dev_err(&data->master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) "%s:dmaengine_prep_slave_sg Failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) desc_tx->callback = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) desc_tx->callback_param = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) dma->nent = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) dma->desc_tx = desc_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) dev_dbg(&data->master->dev, "%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) spin_lock_irqsave(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) desc_rx->tx_submit(desc_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) desc_tx->tx_submit(desc_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) spin_unlock_irqrestore(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /* reset transfer complete flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) data->transfer_complete = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static void pch_spi_process_messages(struct work_struct *pwork)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct spi_message *pmsg, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct pch_spi_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) int bpw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) data = container_of(pwork, struct pch_spi_data, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) spin_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) /* check if suspend has been initiated;if yes flush queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) dev_dbg(&data->master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) "%s suspend/remove initiated, flushing queue\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) pmsg->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (pmsg->complete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) spin_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) pmsg->complete(pmsg->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) spin_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /* delete from queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) list_del_init(&pmsg->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) spin_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) data->bcurrent_msg_processing = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) dev_dbg(&data->master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) "%s Set data->bcurrent_msg_processing= true\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* Get the message from the queue and delete it from there. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) data->current_msg = list_entry(data->queue.next, struct spi_message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) list_del_init(&data->current_msg->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) data->current_msg->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) pch_spi_select_chip(data, data->current_msg->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) spin_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (data->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) pch_spi_request_dma(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) data->current_msg->spi->bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* If we are already processing a message get the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) transfer structure from the message otherwise retrieve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) the 1st transfer request from the message. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) spin_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (data->cur_trans == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) data->cur_trans =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) list_entry(data->current_msg->transfers.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct spi_transfer, transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) dev_dbg(&data->master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) "%s :Getting 1st transfer message\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) data->cur_trans =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) list_entry(data->cur_trans->transfer_list.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct spi_transfer, transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) dev_dbg(&data->master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) "%s :Getting next transfer message\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) spin_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (!data->cur_trans->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) data->save_total_len = data->cur_trans->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (data->use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) char *save_rx_buf = data->cur_trans->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) for (i = 0; i < cnt; i ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) pch_spi_handle_dma(data, &bpw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (!pch_spi_start_transfer(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) data->transfer_complete = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) data->current_msg->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) data->current_msg->complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) (data->current_msg->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) data->bcurrent_msg_processing = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) data->current_msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) data->cur_trans = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) pch_spi_copy_rx_data_for_dma(data, bpw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) data->cur_trans->rx_buf = save_rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) pch_spi_set_tx(data, &bpw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) pch_spi_set_ir(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) pch_spi_copy_rx_data(data, bpw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) kfree(data->pkt_rx_buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) data->pkt_rx_buff = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) kfree(data->pkt_tx_buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) data->pkt_tx_buff = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* increment message count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) data->cur_trans->len = data->save_total_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) data->current_msg->actual_length += data->cur_trans->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) dev_dbg(&data->master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) "%s:data->current_msg->actual_length=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) __func__, data->current_msg->actual_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) spi_transfer_delay_exec(data->cur_trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) spin_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /* No more transfer in this message. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if ((data->cur_trans->transfer_list.next) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) &(data->current_msg->transfers)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) pch_spi_nomore_transfer(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) spin_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) } while (data->cur_trans != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (data->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) pch_spi_release_dma(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct pch_spi_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) flush_work(&data->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct pch_spi_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) /* reset PCH SPI h/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) pch_spi_reset(data->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) dev_dbg(&board_dat->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) "%s pch_spi_reset invoked successfully\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) struct pch_spi_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) struct pch_spi_dma_ctrl *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) dma = &data->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (dma->tx_buf_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) dma->tx_buf_virt, dma->tx_buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (dma->rx_buf_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) dma->rx_buf_virt, dma->rx_buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static int pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) struct pch_spi_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) struct pch_spi_dma_ctrl *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) dma = &data->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* Get Consistent memory for Tx DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (!dma->tx_buf_virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /* Get Consistent memory for Rx DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (!dma->rx_buf_virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) static int pch_spi_pd_probe(struct platform_device *plat_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct pch_spi_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) master = spi_alloc_master(&board_dat->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) sizeof(struct pch_spi_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) plat_dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) data = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) data->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) platform_set_drvdata(plat_dev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) /* baseaddress + address offset) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) PCH_ADDRESS_SIZE * plat_dev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (!data->io_remap_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) goto err_pci_iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) data->io_remap_addr += PCH_ADDRESS_SIZE * plat_dev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) plat_dev->id, data->io_remap_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /* initialize members of SPI master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) master->num_chipselect = PCH_MAX_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) master->transfer = pch_spi_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) master->max_speed_hz = PCH_MAX_BAUDRATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) data->board_dat = board_dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) data->plat_dev = plat_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) data->n_curnt_chip = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) data->status = STATUS_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) data->ch = plat_dev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) data->use_dma = use_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) INIT_LIST_HEAD(&data->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) spin_lock_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) INIT_WORK(&data->work, pch_spi_process_messages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) init_waitqueue_head(&data->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) ret = pch_spi_get_resources(board_dat, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) goto err_spi_get_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) IRQF_SHARED, KBUILD_MODNAME, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) dev_err(&plat_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) "%s request_irq failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) goto err_request_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) data->irq_reg_sts = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) pch_spi_set_master_mode(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) ret = pch_alloc_dma_buf(board_dat, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) goto err_spi_register_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) ret = spi_register_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) dev_err(&plat_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) "%s spi_register_master FAILED\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) goto err_spi_register_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) err_spi_register_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) pch_free_dma_buf(board_dat, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) free_irq(board_dat->pdev->irq, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) err_request_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) pch_spi_free_resources(board_dat, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) err_spi_get_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) pci_iounmap(board_dat->pdev, data->io_remap_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) err_pci_iomap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) static int pch_spi_pd_remove(struct platform_device *plat_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) struct pch_spi_data *data = platform_get_drvdata(plat_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) __func__, plat_dev->id, board_dat->pdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) if (use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) pch_free_dma_buf(board_dat, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /* check for any pending messages; no action is taken if the queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) * is still full; but at least we tried. Unload anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) count = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) spin_lock_irqsave(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) data->status = STATUS_EXITING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) while ((list_empty(&data->queue) == 0) && --count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) spin_unlock_irqrestore(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) msleep(PCH_SLEEP_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) spin_lock_irqsave(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) spin_unlock_irqrestore(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) pch_spi_free_resources(board_dat, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /* disable interrupts & free IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (data->irq_reg_sts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) data->irq_reg_sts = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) free_irq(board_dat->pdev->irq, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) pci_iounmap(board_dat->pdev, data->io_remap_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) spi_unregister_master(data->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) static int pch_spi_pd_suspend(struct platform_device *pd_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) u8 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) struct pch_spi_data *data = platform_get_drvdata(pd_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (!board_dat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) dev_err(&pd_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) "%s pci_get_drvdata returned NULL\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) /* check if the current message is processed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) Only after thats done the transfer will be suspended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) count = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) while ((--count) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if (!(data->bcurrent_msg_processing))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) msleep(PCH_SLEEP_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) /* Free IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (data->irq_reg_sts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /* disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) pch_spi_reset(data->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) free_irq(board_dat->pdev->irq, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) data->irq_reg_sts = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) dev_dbg(&pd_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) "%s free_irq invoked successfully.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) static int pch_spi_pd_resume(struct platform_device *pd_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) struct pch_spi_data *data = platform_get_drvdata(pd_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (!board_dat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) dev_err(&pd_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) "%s pci_get_drvdata returned NULL\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) if (!data->irq_reg_sts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) /* register IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) IRQF_SHARED, KBUILD_MODNAME, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) dev_err(&pd_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) "%s request_irq failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* reset PCH SPI h/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) pch_spi_reset(data->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) pch_spi_set_master_mode(data->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) data->irq_reg_sts = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) #define pch_spi_pd_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) #define pch_spi_pd_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) static struct platform_driver pch_spi_pd_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .name = "pch-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .probe = pch_spi_pd_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .remove = pch_spi_pd_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .suspend = pch_spi_pd_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .resume = pch_spi_pd_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) struct pch_spi_board_data *board_dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) struct platform_device *pd_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) struct pch_pd_dev_save *pd_dev_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) pd_dev_save = kzalloc(sizeof(*pd_dev_save), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) if (!pd_dev_save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) board_dat = kzalloc(sizeof(*board_dat), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (!board_dat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) goto err_no_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) retval = pci_request_regions(pdev, KBUILD_MODNAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) dev_err(&pdev->dev, "%s request_region failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) goto pci_request_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) board_dat->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) board_dat->num = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) pd_dev_save->num = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) pd_dev_save->board_dat = board_dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) retval = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) goto pci_enable_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) for (i = 0; i < board_dat->num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) pd_dev = platform_device_alloc("pch-spi", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) if (!pd_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) dev_err(&pdev->dev, "platform_device_alloc failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) goto err_platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) pd_dev_save->pd_save[i] = pd_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) pd_dev->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) retval = platform_device_add_data(pd_dev, board_dat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) sizeof(*board_dat));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) "platform_device_add_data failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) platform_device_put(pd_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) goto err_platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) retval = platform_device_add(pd_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) dev_err(&pdev->dev, "platform_device_add failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) platform_device_put(pd_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) goto err_platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) pci_set_drvdata(pdev, pd_dev_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) err_platform_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) while (--i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) platform_device_unregister(pd_dev_save->pd_save[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) pci_enable_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) pci_request_regions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) kfree(board_dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) err_no_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) kfree(pd_dev_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) static void pch_spi_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) for (i = 0; i < pd_dev_save->num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) platform_device_unregister(pd_dev_save->pd_save[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) kfree(pd_dev_save->board_dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) kfree(pd_dev_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) static int __maybe_unused pch_spi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) struct pch_pd_dev_save *pd_dev_save = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) dev_dbg(dev, "%s ENTRY\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) pd_dev_save->board_dat->suspend_sts = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) static int __maybe_unused pch_spi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) struct pch_pd_dev_save *pd_dev_save = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) dev_dbg(dev, "%s ENTRY\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) /* set suspend status to false */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) pd_dev_save->board_dat->suspend_sts = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) static SIMPLE_DEV_PM_OPS(pch_spi_pm_ops, pch_spi_suspend, pch_spi_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) static struct pci_driver pch_spi_pcidev_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .name = "pch_spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .id_table = pch_spi_pcidev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .probe = pch_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .remove = pch_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .driver.pm = &pch_spi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) static int __init pch_spi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) ret = platform_driver_register(&pch_spi_pd_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) ret = pci_register_driver(&pch_spi_pcidev_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) platform_driver_unregister(&pch_spi_pd_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) module_init(pch_spi_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) static void __exit pch_spi_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) pci_unregister_driver(&pch_spi_pcidev_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) platform_driver_unregister(&pch_spi_pd_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) module_exit(pch_spi_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) module_param(use_dma, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) MODULE_PARM_DESC(use_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) "to use DMA for data transfers pass 1 else 0; default 1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) MODULE_DEVICE_TABLE(pci, pch_spi_pcidev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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