^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TI QSPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Sourav Poddar <sourav.poddar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/omap-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/spi/spi-mem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct ti_qspi_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 clkctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct ti_qspi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct completion transfer_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* list synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct mutex list_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __iomem *mmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) size_t mmap_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct regmap *ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct clk *fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct ti_qspi_regs ctx_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) dma_addr_t mmap_phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) dma_addr_t rx_bb_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) void *rx_bb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct dma_chan *rx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 spi_max_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) bool mmap_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int current_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define QSPI_PID (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define QSPI_SYSCONFIG (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define QSPI_SPI_DC_REG (0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define QSPI_SPI_CMD_REG (0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define QSPI_SPI_STATUS_REG (0x4c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define QSPI_SPI_DATA_REG (0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define QSPI_SPI_SETUP_REG(n) ((0x54 + 4 * n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define QSPI_SPI_SWITCH_REG (0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define QSPI_SPI_DATA_REG_1 (0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define QSPI_SPI_DATA_REG_2 (0x6c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define QSPI_SPI_DATA_REG_3 (0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Clock Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define QSPI_CLK_EN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define QSPI_CLK_DIV_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define QSPI_EN_CS(n) (n << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define QSPI_WLEN(n) ((n - 1) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define QSPI_3_PIN (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define QSPI_RD_SNGL (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define QSPI_WR_SNGL (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define QSPI_RD_DUAL (3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define QSPI_RD_QUAD (7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define QSPI_INVAL (4 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define QSPI_FLEN(n) ((n - 1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define QSPI_WLEN_MAX_BITS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define QSPI_WLEN_MAX_BYTES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* STATUS REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BUSY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define WC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Device Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define QSPI_DD(m, n) (m << (3 + n * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define QSPI_CKPHA(n) (1 << (2 + n * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define QSPI_CSPOL(n) (1 << (1 + n * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define QSPI_CKPOL(n) (1 << (n * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define QSPI_FRAME 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define QSPI_AUTOSUSPEND_TIMEOUT 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MEM_CS_EN(n) ((n + 1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MEM_CS_MASK (7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MM_SWITCH 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define QSPI_SETUP_RD_NORMAL (0x0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define QSPI_SETUP_RD_DUAL (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define QSPI_SETUP_RD_QUAD (0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define QSPI_SETUP_ADDR_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define QSPI_SETUP_DUMMY_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define QSPI_DMA_BUFFER_SIZE SZ_64K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return readl(qspi->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static inline void ti_qspi_write(struct ti_qspi *qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned long val, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) writel(val, qspi->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int ti_qspi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int clk_div = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 clk_ctrl_reg, clk_rate, clk_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (spi->master->busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dev_dbg(qspi->dev, "master busy doing other transfers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (!qspi->spi_max_frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_err(qspi->dev, "spi max frequency not defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) clk_rate = clk_get_rate(qspi->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (clk_div < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (clk_div > QSPI_CLK_DIV_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) qspi->spi_max_frequency, clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = pm_runtime_get_sync(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pm_runtime_put_noidle(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) clk_ctrl_reg &= ~QSPI_CLK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* disable SCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* enable SCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) clk_mask = QSPI_CLK_EN | clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ctx_reg->clkctrl = clk_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) pm_runtime_mark_last_busy(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = pm_runtime_put_autosuspend(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static inline u32 qspi_is_busy(struct ti_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) while ((stat & BUSY) && time_after(timeout, jiffies)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) WARN(stat & BUSY, "qspi busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return stat & BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (stat & WC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } while (time_after(timeout, jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (stat & WC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int wlen, xfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned int cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) const u8 *txbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) txbuf = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) cmd = qspi->cmd | QSPI_WR_SNGL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) wlen = t->bits_per_word >> 3; /* in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) xfer_len = wlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) while (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (qspi_is_busy(qspi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) switch (wlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) cmd, qspi->dc, *txbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (count >= QSPI_WLEN_MAX_BYTES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 *txp = (u32 *)txbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) data = cpu_to_be32(*txp++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) writel(data, qspi->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) QSPI_SPI_DATA_REG_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) data = cpu_to_be32(*txp++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) writel(data, qspi->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) QSPI_SPI_DATA_REG_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) data = cpu_to_be32(*txp++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) writel(data, qspi->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) QSPI_SPI_DATA_REG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) data = cpu_to_be32(*txp++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) writel(data, qspi->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) QSPI_SPI_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) xfer_len = QSPI_WLEN_MAX_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) cmd = qspi->cmd | QSPI_WR_SNGL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) xfer_len = wlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) cmd |= QSPI_WLEN(wlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) cmd, qspi->dc, *txbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) cmd, qspi->dc, *txbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ti_qspi_poll_wc(qspi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev_err(qspi->dev, "write timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) txbuf += xfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) count -= xfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int wlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned int cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u32 rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u8 rxlen, rx_wlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u8 *rxbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) rxbuf = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) cmd = qspi->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) switch (t->rx_nbits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case SPI_NBITS_DUAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) cmd |= QSPI_RD_DUAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case SPI_NBITS_QUAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) cmd |= QSPI_RD_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) cmd |= QSPI_RD_SNGL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) wlen = t->bits_per_word >> 3; /* in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) rx_wlen = wlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) while (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (qspi_is_busy(qspi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) switch (wlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * Optimize the 8-bit words transfers, as used by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * the SPI flash devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (count >= QSPI_WLEN_MAX_BYTES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) rxlen = QSPI_WLEN_MAX_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) rxlen = min(count, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) rx_wlen = rxlen << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) cmd &= ~QSPI_WLEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) cmd |= QSPI_WLEN(rx_wlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) rxlen = wlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (ti_qspi_poll_wc(qspi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev_err(qspi->dev, "read timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) switch (wlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * Optimize the 8-bit words transfers, as used by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * the SPI flash devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (count >= QSPI_WLEN_MAX_BYTES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u32 *rxp = (u32 *) rxbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) rx = readl(qspi->base + QSPI_SPI_DATA_REG_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) *rxp++ = be32_to_cpu(rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) rx = readl(qspi->base + QSPI_SPI_DATA_REG_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) *rxp++ = be32_to_cpu(rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) rx = readl(qspi->base + QSPI_SPI_DATA_REG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) *rxp++ = be32_to_cpu(rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) rx = readl(qspi->base + QSPI_SPI_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) *rxp++ = be32_to_cpu(rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u8 *rxp = rxbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) rx = readl(qspi->base + QSPI_SPI_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (rx_wlen >= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) *rxp++ = rx >> (rx_wlen - 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (rx_wlen >= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) *rxp++ = rx >> (rx_wlen - 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (rx_wlen >= 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) *rxp++ = rx >> (rx_wlen - 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (rx_wlen >= 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) *rxp++ = rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) rxbuf += rxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) count -= rxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (t->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ret = qspi_write_msg(qspi, t, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_dbg(qspi->dev, "Error while writing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (t->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ret = qspi_read_msg(qspi, t, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev_dbg(qspi->dev, "Error while reading\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static void ti_qspi_dma_callback(void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct ti_qspi *qspi = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) complete(&qspi->transfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dma_addr_t dma_src, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct dma_chan *chan = qspi->rx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct dma_async_tx_descriptor *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) tx->callback = ti_qspi_dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) tx->callback_param = qspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) cookie = tx->tx_submit(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) reinit_completion(&qspi->transfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = dma_submit_error(cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dma_async_issue_pending(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = wait_for_completion_timeout(&qspi->transfer_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) msecs_to_jiffies(len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (ret <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dmaengine_terminate_sync(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) void *to, size_t readsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dma_addr_t dma_src = qspi->mmap_phys_base + offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * Use bounce buffer as FS like jffs2, ubifs may pass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * buffers that does not belong to kernel lowmem region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) while (readsize != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) size_t xfer_len = min_t(size_t, QSPI_DMA_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) readsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dma_src, xfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) memcpy(to, qspi->rx_bb_addr, xfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) readsize -= xfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dma_src += xfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) to += xfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) loff_t from)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dma_addr_t dma_src = qspi->mmap_phys_base + from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dma_addr_t dma_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int i, len, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dma_dst = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dma_src += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static void ti_qspi_enable_memory_map(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (qspi->ctrl_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MEM_CS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MEM_CS_EN(spi->chip_select));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) qspi->mmap_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) qspi->current_cs = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static void ti_qspi_disable_memory_map(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (qspi->ctrl_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MEM_CS_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) qspi->mmap_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) qspi->current_cs = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static void ti_qspi_setup_mmap_read(struct spi_device *spi, u8 opcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u8 data_nbits, u8 addr_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u8 dummy_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u32 memval = opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) switch (data_nbits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case SPI_NBITS_QUAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) memval |= QSPI_SETUP_RD_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case SPI_NBITS_DUAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) memval |= QSPI_SETUP_RD_DUAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) memval |= QSPI_SETUP_RD_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) memval |= ((addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ti_qspi_write(qspi, memval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) QSPI_SPI_SETUP_REG(spi->chip_select));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int ti_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) size_t max_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (op->data.dir == SPI_MEM_DATA_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (op->addr.val < qspi->mmap_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Limit MMIO to the mmaped region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (op->addr.val + op->data.nbytes > qspi->mmap_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) max_len = qspi->mmap_size - op->addr.val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) op->data.nbytes = min((size_t) op->data.nbytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) max_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * Use fallback mode (SW generated transfers) above the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * mmaped region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * Adjust size to comply with the QSPI max frame length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) max_len = QSPI_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) max_len -= 1 + op->addr.nbytes + op->dummy.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) op->data.nbytes = min((size_t) op->data.nbytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) max_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int ti_qspi_exec_mem_op(struct spi_mem *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct ti_qspi *qspi = spi_master_get_devdata(mem->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u32 from = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* Only optimize read path. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) !op->addr.nbytes || op->addr.nbytes > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Address exceeds MMIO window size, fall back to regular mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) from = op->addr.val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (from + op->data.nbytes > qspi->mmap_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) mutex_lock(&qspi->list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (!qspi->mmap_enabled || qspi->current_cs != mem->spi->chip_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ti_qspi_enable_memory_map(mem->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) op->addr.nbytes, op->dummy.nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (qspi->rx_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct sg_table sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (virt_addr_valid(op->data.buf.in) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) !spi_controller_dma_map_mem_op_data(mem->spi->master, op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) &sgt)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ret = ti_qspi_dma_xfer_sg(qspi, sgt, from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) spi_controller_dma_unmap_mem_op_data(mem->spi->master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) op, &sgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ret = ti_qspi_dma_bounce_buffer(qspi, from,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) op->data.buf.in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) op->data.nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) memcpy_fromio(op->data.buf.in, qspi->mmap_base + from,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) op->data.nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) mutex_unlock(&qspi->list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .exec_op = ti_qspi_exec_mem_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .adjust_op_size = ti_qspi_adjust_op_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int ti_qspi_start_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct spi_message *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct ti_qspi *qspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct spi_device *spi = m->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct spi_transfer *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int status = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) unsigned int frame_len_words, transfer_len_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) int wlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* setup device control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) qspi->dc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) qspi->dc |= QSPI_CKPHA(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) qspi->dc |= QSPI_CKPOL(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (spi->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) qspi->dc |= QSPI_CSPOL(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) frame_len_words = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) list_for_each_entry(t, &m->transfers, transfer_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) frame_len_words += t->len / (t->bits_per_word >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* setup command reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) qspi->cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) qspi->cmd |= QSPI_EN_CS(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) qspi->cmd |= QSPI_FLEN(frame_len_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) mutex_lock(&qspi->list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (qspi->mmap_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ti_qspi_disable_memory_map(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) list_for_each_entry(t, &m->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) QSPI_WLEN(t->bits_per_word));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) wlen = t->bits_per_word >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) transfer_len_words = min(t->len / wlen, frame_len_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dev_dbg(qspi->dev, "transfer message failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) mutex_unlock(&qspi->list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) m->actual_length += transfer_len_words * wlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) frame_len_words -= transfer_len_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (frame_len_words == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) mutex_unlock(&qspi->list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) m->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) spi_finalize_current_message(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static int ti_qspi_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct ti_qspi *qspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) qspi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ti_qspi_restore_ctx(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static void ti_qspi_dma_cleanup(struct ti_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (qspi->rx_bb_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) qspi->rx_bb_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) qspi->rx_bb_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (qspi->rx_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dma_release_channel(qspi->rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static const struct of_device_id ti_qspi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {.compatible = "ti,dra7xxx-qspi" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {.compatible = "ti,am4372-qspi" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) MODULE_DEVICE_TABLE(of, ti_qspi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static int ti_qspi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct ti_qspi *qspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct resource *r, *res_mmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u32 max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int ret = 0, num_cs, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) master->flags = SPI_MASTER_HALF_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) master->setup = ti_qspi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) master->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) master->transfer_one_message = ti_qspi_start_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) master->mem_ops = &ti_qspi_mem_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (!of_property_read_u32(np, "num-cs", &num_cs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) master->num_chipselect = num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) qspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) qspi->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) qspi->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) platform_set_drvdata(pdev, qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (r == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (r == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dev_err(&pdev->dev, "missing platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) res_mmap = platform_get_resource_byname(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) IORESOURCE_MEM, "qspi_mmap");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (res_mmap == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (res_mmap == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) "memory mapped resource not required\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (res_mmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) qspi->mmap_size = resource_size(res_mmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) mutex_init(&qspi->list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) qspi->base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (IS_ERR(qspi->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ret = PTR_ERR(qspi->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (of_property_read_bool(np, "syscon-chipselects")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) qspi->ctrl_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) syscon_regmap_lookup_by_phandle(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) "syscon-chipselects");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (IS_ERR(qspi->ctrl_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ret = PTR_ERR(qspi->ctrl_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ret = of_property_read_u32_index(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) "syscon-chipselects",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) 1, &qspi->ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) "couldn't get ctrl_mod reg index\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) qspi->fclk = devm_clk_get(&pdev->dev, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (IS_ERR(qspi->fclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ret = PTR_ERR(qspi->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) dev_err(&pdev->dev, "could not get clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) qspi->spi_max_frequency = max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) dma_cap_set(DMA_MEMCPY, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) qspi->rx_chan = dma_request_chan_by_mask(&mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (IS_ERR(qspi->rx_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) dev_err(qspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) "No Rx DMA available, trying mmap mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) qspi->rx_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) goto no_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) QSPI_DMA_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) &qspi->rx_bb_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) GFP_KERNEL | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (!qspi->rx_bb_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) dev_err(qspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) "dma_alloc_coherent failed, using PIO mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) dma_release_channel(qspi->rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) goto no_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) master->dma_rx = qspi->rx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) init_completion(&qspi->transfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (res_mmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) no_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (!qspi->rx_chan && res_mmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (IS_ERR(qspi->mmap_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) "mmap failed with error %ld using PIO mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) PTR_ERR(qspi->mmap_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) qspi->mmap_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) master->mem_ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) qspi->mmap_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) qspi->current_cs = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ret = devm_spi_register_master(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ti_qspi_dma_cleanup(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) free_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static int ti_qspi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct ti_qspi *qspi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) rc = spi_master_suspend(qspi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) ti_qspi_dma_cleanup(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static const struct dev_pm_ops ti_qspi_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .runtime_resume = ti_qspi_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static struct platform_driver ti_qspi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .probe = ti_qspi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .remove = ti_qspi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .name = "ti-qspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .pm = &ti_qspi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .of_match_table = ti_qspi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) module_platform_driver(ti_qspi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) MODULE_DESCRIPTION("TI QSPI controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) MODULE_ALIAS("platform:ti-qspi");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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