^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SLINK_COMMAND 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SLINK_BOTH_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SLINK_CS_SW (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SLINK_CS_VALUE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SLINK_CS_POLARITY (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SLINK_IDLE_SDA_PULL_LOW (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SLINK_IDLE_SDA_MASK (3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SLINK_CS_POLARITY1 (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SLINK_CK_SDA (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SLINK_CS_POLARITY2 (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SLINK_CS_POLARITY3 (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SLINK_IDLE_SCLK_MASK (3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SLINK_M_S (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SLINK_WAIT (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SLINK_GO (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SLINK_ENB (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SLINK_COMMAND2 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SLINK_LSBFE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SLINK_SSOE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SLINK_SPIE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SLINK_BIDIROE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SLINK_MODFEN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SLINK_CS_ACTIVE_BETWEEN (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SLINK_FIFO_REFILLS_0 (0 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SLINK_FIFO_REFILLS_1 (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SLINK_FIFO_REFILLS_2 (2 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SLINK_FIFO_REFILLS_3 (3 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SLINK_FIFO_REFILLS_MASK (3 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SLINK_SPC0 (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SLINK_TXEN (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SLINK_RXEN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SLINK_STATUS 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SLINK_COUNT(val) (((val) >> 0) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SLINK_WORD(val) (((val) >> 5) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SLINK_MODF (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SLINK_RX_UNF (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SLINK_TX_OVF (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SLINK_TX_FULL (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SLINK_TX_EMPTY (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SLINK_RX_FULL (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SLINK_RX_EMPTY (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SLINK_TX_UNF (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SLINK_RX_OVF (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SLINK_TX_FLUSH (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SLINK_RX_FLUSH (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SLINK_SCLK (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SLINK_ERR (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SLINK_RDY (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SLINK_BSY (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) SLINK_TX_UNF | SLINK_RX_OVF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SLINK_MAS_DATA 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SLINK_SLAVE_DATA 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SLINK_DMA_CTL 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SLINK_TX_TRIG_1 (0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SLINK_TX_TRIG_4 (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SLINK_TX_TRIG_8 (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SLINK_TX_TRIG_16 (3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SLINK_TX_TRIG_MASK (3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SLINK_RX_TRIG_1 (0 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SLINK_RX_TRIG_4 (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SLINK_RX_TRIG_8 (2 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SLINK_RX_TRIG_16 (3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SLINK_RX_TRIG_MASK (3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SLINK_PACKED (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SLINK_PACK_SIZE_4 (0 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SLINK_PACK_SIZE_8 (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SLINK_PACK_SIZE_16 (2 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SLINK_PACK_SIZE_32 (3 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SLINK_PACK_SIZE_MASK (3 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SLINK_IE_TXC (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SLINK_IE_RXC (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SLINK_DMA_EN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SLINK_STATUS2 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SLINK_TX_FIFO 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SLINK_RX_FIFO 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DATA_DIR_TX (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DATA_DIR_RX (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SLINK_STATUS2_RESET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MAX_CHIP_SELECT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SLINK_FIFO_DEPTH 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct tegra_slink_chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bool cs_hold_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct tegra_slink_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const struct tegra_slink_chip_data *chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) phys_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 cur_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct spi_device *cur_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned cur_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned cur_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned words_per_32bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned curr_dma_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned cur_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned cur_rx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned cur_tx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned dma_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned max_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) bool is_curr_dma_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct completion rx_dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct completion tx_dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 rx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) bool is_packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 packed_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 command_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 command2_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 dma_control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 def_command_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 def_command2_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct completion xfer_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct spi_transfer *curr_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct dma_chan *rx_dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 *rx_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dma_addr_t rx_dma_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct dma_async_tx_descriptor *rx_dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct dma_chan *tx_dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 *tx_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dma_addr_t tx_dma_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct dma_async_tx_descriptor *tx_dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int tegra_slink_runtime_suspend(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int tegra_slink_runtime_resume(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return readl(tspi->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static inline void tegra_slink_writel(struct tegra_slink_data *tspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 val, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writel(val, tspi->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Read back register to make sure that register writes completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (reg != SLINK_TX_FIFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) readl(tspi->base + SLINK_MAS_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void tegra_slink_clear_status(struct tegra_slink_data *tspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 val_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) tegra_slink_readl(tspi, SLINK_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Write 1 to clear status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) val_write = SLINK_RDY | SLINK_FIFO_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) tegra_slink_writel(tspi, val_write, SLINK_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static u32 tegra_slink_get_packed_size(struct tegra_slink_data *tspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) switch (tspi->bytes_per_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return SLINK_PACK_SIZE_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return SLINK_PACK_SIZE_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return SLINK_PACK_SIZE_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return SLINK_PACK_SIZE_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static unsigned tegra_slink_calculate_curr_xfer_param(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct spi_device *spi, struct tegra_slink_data *tspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned remain_len = t->len - tspi->cur_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned max_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned max_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned total_fifo_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) bits_per_word = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (bits_per_word == 8 || bits_per_word == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) tspi->is_packed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) tspi->words_per_32bit = 32/bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) tspi->is_packed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) tspi->words_per_32bit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) tspi->packed_size = tegra_slink_get_packed_size(tspi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (tspi->is_packed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) max_len = min(remain_len, tspi->max_buf_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) tspi->curr_dma_words = max_len/tspi->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) total_fifo_words = max_len/4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) max_word = min(max_word, tspi->max_buf_size/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) tspi->curr_dma_words = max_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) total_fifo_words = max_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return total_fifo_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct tegra_slink_data *tspi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned tx_empty_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 fifo_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned max_n_32bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned i, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned int written_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned fifo_words_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (tspi->is_packed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) fifo_words_left = tx_empty_count * tspi->words_per_32bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) written_words = min(fifo_words_left, tspi->curr_dma_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) nbytes = written_words * tspi->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) max_n_32bit = DIV_ROUND_UP(nbytes, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) for (count = 0; count < max_n_32bit; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 x = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) for (i = 0; (i < 4) && nbytes; i++, nbytes--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) x |= (u32)(*tx_buf++) << (i * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) max_n_32bit = min(tspi->curr_dma_words, tx_empty_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) written_words = max_n_32bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) nbytes = written_words * tspi->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) for (count = 0; count < max_n_32bit; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 x = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) for (i = 0; nbytes && (i < tspi->bytes_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) i++, nbytes--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) x |= (u32)(*tx_buf++) << (i * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return written_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct tegra_slink_data *tspi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned rx_full_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 fifo_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned i, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int read_words = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (tspi->is_packed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) len = tspi->curr_dma_words * tspi->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) for (count = 0; count < rx_full_count; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) for (i = 0; len && (i < 4); i++, len--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *rx_buf++ = (x >> i*8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) read_words += tspi->curr_dma_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) for (count = 0; count < rx_full_count; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) for (i = 0; (i < tspi->bytes_per_word); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) *rx_buf++ = (x >> (i*8)) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) read_words += rx_full_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return read_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static void tegra_slink_copy_client_txbuf_to_spi_txbuf(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct tegra_slink_data *tspi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Make the dma buffer to read by cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) tspi->dma_buf_size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (tspi->is_packed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) for (count = 0; count < tspi->curr_dma_words; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u32 x = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) for (i = 0; consume && (i < tspi->bytes_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) i++, consume--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) x |= (u32)(*tx_buf++) << (i * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) tspi->tx_dma_buf[count] = x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Make the dma buffer to read by dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) tspi->dma_buf_size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct tegra_slink_data *tspi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Make the dma buffer to read by cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) tspi->dma_buf_size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (tspi->is_packed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) len = tspi->curr_dma_words * tspi->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) for (count = 0; count < tspi->curr_dma_words; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u32 x = tspi->rx_dma_buf[count] & rx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) for (i = 0; (i < tspi->bytes_per_word); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) *rx_buf++ = (x >> (i*8)) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Make the dma buffer to read by dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) tspi->dma_buf_size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static void tegra_slink_dma_complete(void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct completion *dma_complete = args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) complete(dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) reinit_completion(&tspi->tx_dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!tspi->tx_dma_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_err(tspi->dev, "Not able to get desc for Tx\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) tspi->tx_dma_desc->callback = tegra_slink_dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dmaengine_submit(tspi->tx_dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dma_async_issue_pending(tspi->tx_dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) reinit_completion(&tspi->rx_dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (!tspi->rx_dma_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dev_err(tspi->dev, "Not able to get desc for Rx\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) tspi->rx_dma_desc->callback = tegra_slink_dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dmaengine_submit(tspi->rx_dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dma_async_issue_pending(tspi->rx_dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static int tegra_slink_start_dma_based_transfer(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct tegra_slink_data *tspi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* Make sure that Rx and Tx fifo are empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) status = tegra_slink_readl(tspi, SLINK_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) (unsigned)status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) val |= tspi->packed_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (tspi->is_packed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 4) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) len = tspi->curr_dma_words * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Set attention level based on length of transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (len & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) else if (((len) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (tspi->cur_direction & DATA_DIR_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) val |= SLINK_IE_TXC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (tspi->cur_direction & DATA_DIR_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) val |= SLINK_IE_RXC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) tspi->dma_control_reg = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (tspi->cur_direction & DATA_DIR_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = tegra_slink_start_tx_dma(tspi, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dev_err(tspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) "Starting tx dma failed, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* Wait for tx fifo to be fill before starting slink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) status = tegra_slink_readl(tspi, SLINK_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) while (!(status & SLINK_TX_FULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) status = tegra_slink_readl(tspi, SLINK_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (tspi->cur_direction & DATA_DIR_RX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Make the dma buffer to read by dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) tspi->dma_buf_size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ret = tegra_slink_start_rx_dma(tspi, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dev_err(tspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) "Starting rx dma failed, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (tspi->cur_direction & DATA_DIR_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dmaengine_terminate_all(tspi->tx_dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) tspi->is_curr_dma_xfer = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (tspi->is_packed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) val |= SLINK_PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* HW need small delay after settign Packed mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) tspi->dma_control_reg = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) val |= SLINK_DMA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static int tegra_slink_start_cpu_based_transfer(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct tegra_slink_data *tspi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned cur_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) val = tspi->packed_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (tspi->cur_direction & DATA_DIR_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) val |= SLINK_IE_TXC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (tspi->cur_direction & DATA_DIR_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) val |= SLINK_IE_RXC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) tspi->dma_control_reg = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (tspi->cur_direction & DATA_DIR_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) cur_words = tspi->curr_dma_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) tspi->dma_control_reg = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) tspi->is_curr_dma_xfer = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (tspi->is_packed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) val |= SLINK_PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) tspi->dma_control_reg = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) val |= SLINK_DMA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) bool dma_to_memory)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct dma_chan *dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u32 *dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dma_addr_t dma_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct dma_slave_config dma_sconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (IS_ERR(dma_chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return dev_err_probe(tspi->dev, PTR_ERR(dma_chan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) "Dma channel is not available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) &dma_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (!dma_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dma_release_channel(dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (dma_to_memory) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dma_sconfig.src_maxburst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dma_sconfig.dst_maxburst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) goto scrub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (dma_to_memory) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) tspi->rx_dma_chan = dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) tspi->rx_dma_buf = dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) tspi->rx_dma_phys = dma_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) tspi->tx_dma_chan = dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) tspi->tx_dma_buf = dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) tspi->tx_dma_phys = dma_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) scrub:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dma_release_channel(dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) bool dma_to_memory)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u32 *dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) dma_addr_t dma_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct dma_chan *dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (dma_to_memory) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) dma_buf = tspi->rx_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dma_chan = tspi->rx_dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dma_phys = tspi->rx_dma_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) tspi->rx_dma_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) tspi->rx_dma_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dma_buf = tspi->tx_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dma_chan = tspi->tx_dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dma_phys = tspi->tx_dma_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) tspi->tx_dma_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) tspi->tx_dma_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (!dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dma_release_channel(dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static int tegra_slink_start_transfer_one(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u32 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u8 bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) unsigned total_fifo_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) u32 command2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) bits_per_word = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) speed = t->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (speed != tspi->cur_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) clk_set_rate(tspi->clk, speed * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) tspi->cur_speed = speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) tspi->cur_spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) tspi->cur_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) tspi->cur_rx_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) tspi->cur_tx_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) tspi->curr_xfer = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) command = tspi->command_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) command &= ~SLINK_BIT_LENGTH(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) command |= SLINK_BIT_LENGTH(bits_per_word - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) command2 = tspi->command2_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) command2 &= ~(SLINK_RXEN | SLINK_TXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) tspi->cur_direction = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (t->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) command2 |= SLINK_RXEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) tspi->cur_direction |= DATA_DIR_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (t->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) command2 |= SLINK_TXEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) tspi->cur_direction |= DATA_DIR_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * Writing to the command2 register bevore the command register prevents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * a spike in chip_select line 0. This selects the chip_select line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * before changing the chip_select value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) tegra_slink_writel(tspi, command2, SLINK_COMMAND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) tspi->command2_reg = command2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) tegra_slink_writel(tspi, command, SLINK_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) tspi->command_reg = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (total_fifo_words > SLINK_FIFO_DEPTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ret = tegra_slink_start_dma_based_transfer(tspi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret = tegra_slink_start_cpu_based_transfer(tspi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static int tegra_slink_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static const u32 cs_pol_bit[MAX_CHIP_SELECT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) SLINK_CS_POLARITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) SLINK_CS_POLARITY1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) SLINK_CS_POLARITY2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) SLINK_CS_POLARITY3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) spi->bits_per_word,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) spi->mode & SPI_CPOL ? "" : "~",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) spi->mode & SPI_CPHA ? "" : "~",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) spi->max_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ret = pm_runtime_get_sync(tspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) pm_runtime_put_noidle(tspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) spin_lock_irqsave(&tspi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) val = tspi->def_command_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (spi->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) val |= cs_pol_bit[spi->chip_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) val &= ~cs_pol_bit[spi->chip_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) tspi->def_command_reg = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) spin_unlock_irqrestore(&tspi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) pm_runtime_put(tspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static int tegra_slink_prepare_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct tegra_slink_data *tspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct spi_device *spi = msg->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) tegra_slink_clear_status(tspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) tspi->command_reg = tspi->def_command_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) tspi->command2_reg = tspi->def_command2_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) tspi->command2_reg |= SLINK_SS_EN_CS(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) tspi->command_reg &= ~SLINK_MODES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) tspi->command_reg |= SLINK_CK_SDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int tegra_slink_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct tegra_slink_data *tspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) reinit_completion(&tspi->xfer_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ret = tegra_slink_start_transfer_one(spi, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) dev_err(tspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) "spi can not start transfer, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ret = wait_for_completion_timeout(&tspi->xfer_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) SLINK_DMA_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (WARN_ON(ret == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) dev_err(tspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) "spi transfer timeout, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (tspi->tx_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return tspi->tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (tspi->rx_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return tspi->rx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static int tegra_slink_unprepare_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct tegra_slink_data *tspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct spi_transfer *t = tspi->curr_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) spin_lock_irqsave(&tspi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (tspi->tx_status || tspi->rx_status ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) (tspi->status_reg & SLINK_BSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dev_err(tspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dev_err(tspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) tspi->command2_reg, tspi->dma_control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) reset_control_assert(tspi->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) reset_control_deassert(tspi->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) complete(&tspi->xfer_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (tspi->cur_direction & DATA_DIR_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (tspi->cur_direction & DATA_DIR_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) tspi->cur_pos = tspi->cur_tx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) tspi->cur_pos = tspi->cur_rx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (tspi->cur_pos == t->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) complete(&tspi->xfer_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) tegra_slink_start_cpu_based_transfer(tspi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) spin_unlock_irqrestore(&tspi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct spi_transfer *t = tspi->curr_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) long wait_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) unsigned total_fifo_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* Abort dmas if any error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (tspi->cur_direction & DATA_DIR_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (tspi->tx_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dmaengine_terminate_all(tspi->tx_dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) err += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) wait_status = wait_for_completion_interruptible_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (wait_status <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dmaengine_terminate_all(tspi->tx_dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dev_err(tspi->dev, "TxDma Xfer failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) err += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (tspi->cur_direction & DATA_DIR_RX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (tspi->rx_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dmaengine_terminate_all(tspi->rx_dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) err += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) wait_status = wait_for_completion_interruptible_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (wait_status <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) dmaengine_terminate_all(tspi->rx_dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dev_err(tspi->dev, "RxDma Xfer failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) err += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) spin_lock_irqsave(&tspi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) dev_err(tspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) dev_err(tspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) tspi->command2_reg, tspi->dma_control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) reset_control_assert(tspi->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) reset_control_assert(tspi->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) complete(&tspi->xfer_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) spin_unlock_irqrestore(&tspi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (tspi->cur_direction & DATA_DIR_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (tspi->cur_direction & DATA_DIR_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) tspi->cur_pos = tspi->cur_tx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) tspi->cur_pos = tspi->cur_rx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (tspi->cur_pos == t->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) complete(&tspi->xfer_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* Continue transfer in current message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) tspi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (total_fifo_words > SLINK_FIFO_DEPTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) err = tegra_slink_start_dma_based_transfer(tspi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) err = tegra_slink_start_cpu_based_transfer(tspi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) spin_unlock_irqrestore(&tspi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct tegra_slink_data *tspi = context_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (!tspi->is_curr_dma_xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return handle_cpu_based_xfer(tspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return handle_dma_based_xfer(tspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static irqreturn_t tegra_slink_isr(int irq, void *context_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct tegra_slink_data *tspi = context_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (tspi->cur_direction & DATA_DIR_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) tspi->tx_status = tspi->status_reg &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) (SLINK_TX_OVF | SLINK_TX_UNF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (tspi->cur_direction & DATA_DIR_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) tspi->rx_status = tspi->status_reg &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) (SLINK_RX_OVF | SLINK_RX_UNF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) tegra_slink_clear_status(tspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static const struct tegra_slink_chip_data tegra30_spi_cdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .cs_hold_time = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static const struct tegra_slink_chip_data tegra20_spi_cdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .cs_hold_time = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static const struct of_device_id tegra_slink_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) MODULE_DEVICE_TABLE(of, tegra_slink_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static int tegra_slink_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct tegra_slink_data *tspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) int ret, spi_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) const struct tegra_slink_chip_data *cdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) cdata = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) dev_err(&pdev->dev, "master allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* the spi->mode bits understood by this driver: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) master->setup = tegra_slink_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) master->prepare_message = tegra_slink_prepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) master->transfer_one = tegra_slink_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) master->unprepare_message = tegra_slink_unprepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) master->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) master->num_chipselect = MAX_CHIP_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) tspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) tspi->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) tspi->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) tspi->chip_data = cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) spin_lock_init(&tspi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (of_property_read_u32(tspi->dev->of_node, "spi-max-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) &master->max_speed_hz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) master->max_speed_hz = 25000000; /* 25MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (!r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) dev_err(&pdev->dev, "No IO memory resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) goto exit_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) tspi->phys = r->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) tspi->base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (IS_ERR(tspi->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ret = PTR_ERR(tspi->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) goto exit_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* disabled clock may cause interrupt storm upon request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) tspi->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (IS_ERR(tspi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ret = PTR_ERR(tspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dev_err(&pdev->dev, "Can not get clock %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) goto exit_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ret = clk_prepare(tspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) dev_err(&pdev->dev, "Clock prepare failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) goto exit_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ret = clk_enable(tspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) dev_err(&pdev->dev, "Clock enable failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) goto exit_clk_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) spi_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) tspi->irq = spi_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ret = request_threaded_irq(tspi->irq, tegra_slink_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) tegra_slink_isr_thread, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) dev_name(&pdev->dev), tspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) tspi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) goto exit_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (IS_ERR(tspi->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) dev_err(&pdev->dev, "can not get reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ret = PTR_ERR(tspi->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) goto exit_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ret = tegra_slink_init_dma_param(tspi, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) goto exit_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ret = tegra_slink_init_dma_param(tspi, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) goto exit_rx_dma_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) tspi->max_buf_size = tspi->dma_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) init_completion(&tspi->tx_dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) init_completion(&tspi->rx_dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) init_completion(&tspi->xfer_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (!pm_runtime_enabled(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ret = tegra_slink_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) goto exit_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret = pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) goto exit_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) tspi->def_command_reg = SLINK_M_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) ret = devm_spi_register_master(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) dev_err(&pdev->dev, "can not register to master err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) goto exit_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) exit_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) tegra_slink_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) tegra_slink_deinit_dma_param(tspi, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) exit_rx_dma_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) tegra_slink_deinit_dma_param(tspi, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) exit_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) free_irq(spi_irq, tspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) exit_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) clk_disable(tspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) exit_clk_unprepare:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) clk_unprepare(tspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) exit_free_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static int tegra_slink_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct tegra_slink_data *tspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) free_irq(tspi->irq, tspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) clk_disable(tspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) clk_unprepare(tspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (tspi->tx_dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) tegra_slink_deinit_dma_param(tspi, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (tspi->rx_dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) tegra_slink_deinit_dma_param(tspi, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) tegra_slink_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static int tegra_slink_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return spi_master_suspend(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) static int tegra_slink_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct tegra_slink_data *tspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) dev_err(dev, "pm runtime failed, e = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return spi_master_resume(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static int __maybe_unused tegra_slink_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct tegra_slink_data *tspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /* Flush all write which are in PPSB queue by reading back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) tegra_slink_readl(tspi, SLINK_MAS_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) clk_disable_unprepare(tspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static int __maybe_unused tegra_slink_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct tegra_slink_data *tspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) ret = clk_prepare_enable(tspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) static const struct dev_pm_ops slink_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) tegra_slink_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static struct platform_driver tegra_slink_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .name = "spi-tegra-slink",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .pm = &slink_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .of_match_table = tegra_slink_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .probe = tegra_slink_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .remove = tegra_slink_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) module_platform_driver(tegra_slink_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) MODULE_ALIAS("platform:spi-tegra-slink");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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