^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SPI driver for Nvidia's Tegra20 Serial Flash Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Laxman Dewangan <ldewangan@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPI_COMMAND 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPI_GO BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPI_M_S BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPI_ACTIVE_SCLK_MASK (0x3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPI_ACTIVE_SCLK_DRIVE_LOW (0 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPI_ACTIVE_SCLK_DRIVE_HIGH (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPI_ACTIVE_SCLK_PULL_LOW (2 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPI_ACTIVE_SCLK_PULL_HIGH (3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPI_CK_SDA_FALLING (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPI_CK_SDA_RISING (0 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPI_CK_SDA_MASK (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPI_ACTIVE_SDA (0x3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPI_ACTIVE_SDA_DRIVE_LOW (0 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPI_ACTIVE_SDA_DRIVE_HIGH (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPI_ACTIVE_SDA_PULL_LOW (2 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPI_ACTIVE_SDA_PULL_HIGH (3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPI_CS_POL_INVERT BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPI_TX_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPI_RX_EN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPI_CS_VAL_HIGH BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPI_CS_VAL_LOW 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPI_CS_SW BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPI_CS_HW 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPI_CS_DELAY_MASK (7 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPI_CS3_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPI_CS2_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPI_CS1_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPI_CS0_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPI_CS_MASK (SPI_CS3_EN | SPI_CS2_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) SPI_CS1_EN | SPI_CS0_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPI_BIT_LENGTH(x) (((x) & 0x1f) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SPI_MODES (SPI_ACTIVE_SCLK_MASK | SPI_CK_SDA_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SPI_STATUS 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPI_BSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPI_RDY BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SPI_TXF_FLUSH BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPI_RXF_FLUSH BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SPI_RX_UNF BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SPI_TX_OVF BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SPI_RXF_EMPTY BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SPI_RXF_FULL BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SPI_TXF_EMPTY BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SPI_TXF_FULL BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SPI_BLK_CNT(count) (((count) & 0xffff) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SPI_FIFO_ERROR (SPI_RX_UNF | SPI_TX_OVF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SPI_FIFO_EMPTY (SPI_TX_EMPTY | SPI_RX_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SPI_RX_CMP 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SPI_DMA_CTL 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SPI_DMA_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SPI_IE_RXC BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SPI_IE_TXC BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SPI_PACKED BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SPI_RX_TRIG_MASK (0x3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SPI_RX_TRIG_1W (0x0 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SPI_RX_TRIG_4W (0x1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SPI_TX_TRIG_MASK (0x3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SPI_TX_TRIG_1W (0x0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SPI_TX_TRIG_4W (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SPI_DMA_BLK_COUNT(count) (((count) - 1) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SPI_TX_FIFO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SPI_RX_FIFO 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DATA_DIR_TX (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DATA_DIR_RX (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MAX_CHIP_SELECT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SPI_FIFO_DEPTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct tegra_sflash_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 cur_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct spi_device *cur_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned cur_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned cur_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned cur_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned curr_xfer_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned cur_rx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned cur_tx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 rx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 def_command_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 command_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 dma_control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct completion xfer_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct spi_transfer *curr_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int tegra_sflash_runtime_suspend(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int tegra_sflash_runtime_resume(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static inline u32 tegra_sflash_readl(struct tegra_sflash_data *tsd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return readl(tsd->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static inline void tegra_sflash_writel(struct tegra_sflash_data *tsd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 val, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) writel(val, tsd->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void tegra_sflash_clear_status(struct tegra_sflash_data *tsd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Write 1 to clear status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) tegra_sflash_writel(tsd, SPI_RDY | SPI_FIFO_ERROR, SPI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static unsigned tegra_sflash_calculate_curr_xfer_param(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct spi_device *spi, struct tegra_sflash_data *tsd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned remain_len = t->len - tsd->cur_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned max_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) tsd->bytes_per_word = DIV_ROUND_UP(t->bits_per_word, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) max_word = remain_len / tsd->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (max_word > SPI_FIFO_DEPTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) max_word = SPI_FIFO_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) tsd->curr_xfer_words = max_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return max_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static unsigned tegra_sflash_fill_tx_fifo_from_client_txbuf(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct tegra_sflash_data *tsd, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned max_n_32bit = tsd->curr_xfer_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 *tx_buf = (u8 *)t->tx_buf + tsd->cur_tx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (max_n_32bit > SPI_FIFO_DEPTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) max_n_32bit = SPI_FIFO_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) nbytes = max_n_32bit * tsd->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) status = tegra_sflash_readl(tsd, SPI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) while (!(status & SPI_TXF_FULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 x = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) for (i = 0; nbytes && (i < tsd->bytes_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) i++, nbytes--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) x |= (u32)(*tx_buf++) << (i * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) tegra_sflash_writel(tsd, x, SPI_TX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) status = tegra_sflash_readl(tsd, SPI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) tsd->cur_tx_pos += max_n_32bit * tsd->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return max_n_32bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int tegra_sflash_read_rx_fifo_to_client_rxbuf(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct tegra_sflash_data *tsd, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned int read_words = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 *rx_buf = (u8 *)t->rx_buf + tsd->cur_rx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) status = tegra_sflash_readl(tsd, SPI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) while (!(status & SPI_RXF_EMPTY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 x = tegra_sflash_readl(tsd, SPI_RX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) for (i = 0; (i < tsd->bytes_per_word); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *rx_buf++ = (x >> (i*8)) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) read_words++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) status = tegra_sflash_readl(tsd, SPI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tsd->cur_rx_pos += read_words * tsd->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int tegra_sflash_start_cpu_based_transfer(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct tegra_sflash_data *tsd, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned cur_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (tsd->cur_direction & DATA_DIR_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) val |= SPI_IE_TXC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (tsd->cur_direction & DATA_DIR_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) val |= SPI_IE_RXC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) tsd->dma_control_reg = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (tsd->cur_direction & DATA_DIR_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) cur_words = tegra_sflash_fill_tx_fifo_from_client_txbuf(tsd, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) cur_words = tsd->curr_xfer_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) val |= SPI_DMA_BLK_COUNT(cur_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) tsd->dma_control_reg = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) val |= SPI_DMA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int tegra_sflash_start_transfer_one(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct spi_transfer *t, bool is_first_of_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) bool is_single_xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) speed = t->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (speed != tsd->cur_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) clk_set_rate(tsd->clk, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) tsd->cur_speed = speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) tsd->cur_spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) tsd->cur_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) tsd->cur_rx_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) tsd->cur_tx_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) tsd->curr_xfer = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) tegra_sflash_calculate_curr_xfer_param(spi, tsd, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (is_first_of_msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) command = tsd->def_command_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) command |= SPI_BIT_LENGTH(t->bits_per_word - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) command |= SPI_CS_VAL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) command &= ~SPI_MODES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) command |= SPI_CK_SDA_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) command |= SPI_ACTIVE_SCLK_DRIVE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) command |= SPI_ACTIVE_SCLK_DRIVE_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) command |= SPI_CS0_EN << spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) command = tsd->command_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) command &= ~SPI_BIT_LENGTH(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) command |= SPI_BIT_LENGTH(t->bits_per_word - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) command &= ~(SPI_RX_EN | SPI_TX_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) tsd->cur_direction = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (t->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) command |= SPI_RX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) tsd->cur_direction |= DATA_DIR_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (t->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) command |= SPI_TX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) tsd->cur_direction |= DATA_DIR_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) tegra_sflash_writel(tsd, command, SPI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) tsd->command_reg = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return tegra_sflash_start_cpu_based_transfer(tsd, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int tegra_sflash_transfer_one_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) bool is_first_msg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int single_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct spi_transfer *xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct spi_device *spi = msg->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) msg->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) msg->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) single_xfer = list_is_singular(&msg->transfers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) list_for_each_entry(xfer, &msg->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) reinit_completion(&tsd->xfer_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = tegra_sflash_start_transfer_one(spi, xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) is_first_msg, single_xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_err(tsd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "spi can not start transfer, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) is_first_msg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = wait_for_completion_timeout(&tsd->xfer_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) SPI_DMA_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (WARN_ON(ret == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_err(tsd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "spi transfer timeout, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (tsd->tx_status || tsd->rx_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_err(tsd->dev, "Error in Transfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) msg->actual_length += xfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (xfer->cs_change &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) (xfer->delay_usecs || xfer->delay.value)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) tegra_sflash_writel(tsd, tsd->def_command_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) SPI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) spi_transfer_delay_exec(xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) msg->status = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) spi_finalize_current_message(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct spi_transfer *t = tsd->curr_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) spin_lock(&tsd->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (tsd->tx_status || tsd->rx_status || (tsd->status_reg & SPI_BSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev_err(tsd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) "CpuXfer ERROR bit set 0x%x\n", tsd->status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev_err(tsd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "CpuXfer 0x%08x:0x%08x\n", tsd->command_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) tsd->dma_control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) reset_control_assert(tsd->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) reset_control_deassert(tsd->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) complete(&tsd->xfer_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (tsd->cur_direction & DATA_DIR_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) tegra_sflash_read_rx_fifo_to_client_rxbuf(tsd, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (tsd->cur_direction & DATA_DIR_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) tsd->cur_pos = tsd->cur_tx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) tsd->cur_pos = tsd->cur_rx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (tsd->cur_pos == t->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) complete(&tsd->xfer_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) tegra_sflash_calculate_curr_xfer_param(tsd->cur_spi, tsd, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) tegra_sflash_start_cpu_based_transfer(tsd, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) spin_unlock(&tsd->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static irqreturn_t tegra_sflash_isr(int irq, void *context_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct tegra_sflash_data *tsd = context_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) tsd->status_reg = tegra_sflash_readl(tsd, SPI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (tsd->cur_direction & DATA_DIR_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) tsd->tx_status = tsd->status_reg & SPI_TX_OVF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (tsd->cur_direction & DATA_DIR_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) tsd->rx_status = tsd->status_reg & SPI_RX_UNF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) tegra_sflash_clear_status(tsd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return handle_cpu_based_xfer(tsd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const struct of_device_id tegra_sflash_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { .compatible = "nvidia,tegra20-sflash", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MODULE_DEVICE_TABLE(of, tegra_sflash_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int tegra_sflash_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct tegra_sflash_data *tsd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) match = of_match_device(tegra_sflash_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_err(&pdev->dev, "Error: No device match found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) master = spi_alloc_master(&pdev->dev, sizeof(*tsd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dev_err(&pdev->dev, "master allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* the spi->mode bits understood by this driver: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) master->mode_bits = SPI_CPOL | SPI_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) master->transfer_one_message = tegra_sflash_transfer_one_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) master->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) master->num_chipselect = MAX_CHIP_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) tsd = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) tsd->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) tsd->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) spin_lock_init(&tsd->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (of_property_read_u32(tsd->dev->of_node, "spi-max-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) &master->max_speed_hz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) master->max_speed_hz = 25000000; /* 25MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) tsd->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (IS_ERR(tsd->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ret = PTR_ERR(tsd->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) goto exit_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) tsd->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ret = request_irq(tsd->irq, tegra_sflash_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_name(&pdev->dev), tsd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) tsd->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) goto exit_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) tsd->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (IS_ERR(tsd->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_err(&pdev->dev, "can not get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret = PTR_ERR(tsd->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) goto exit_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) tsd->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (IS_ERR(tsd->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(&pdev->dev, "can not get reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ret = PTR_ERR(tsd->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) goto exit_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) init_completion(&tsd->xfer_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (!pm_runtime_enabled(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ret = tegra_sflash_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) goto exit_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) goto exit_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Reset controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) reset_control_assert(tsd->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) reset_control_deassert(tsd->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) tsd->def_command_reg = SPI_M_S | SPI_CS_SW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ret = devm_spi_register_master(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_err(&pdev->dev, "can not register to master err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) goto exit_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) exit_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) tegra_sflash_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) exit_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) free_irq(tsd->irq, tsd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) exit_free_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static int tegra_sflash_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) free_irq(tsd->irq, tsd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) tegra_sflash_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int tegra_sflash_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return spi_master_suspend(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int tegra_sflash_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dev_err(dev, "pm runtime failed, e = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) tegra_sflash_writel(tsd, tsd->command_reg, SPI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return spi_master_resume(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static int tegra_sflash_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Flush all write which are in PPSB queue by reading back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) tegra_sflash_readl(tsd, SPI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) clk_disable_unprepare(tsd->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int tegra_sflash_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = clk_prepare_enable(tsd->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dev_err(tsd->dev, "clk_prepare failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static const struct dev_pm_ops slink_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) SET_RUNTIME_PM_OPS(tegra_sflash_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) tegra_sflash_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) SET_SYSTEM_SLEEP_PM_OPS(tegra_sflash_suspend, tegra_sflash_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static struct platform_driver tegra_sflash_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .name = "spi-tegra-sflash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .pm = &slink_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .of_match_table = tegra_sflash_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .probe = tegra_sflash_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .remove = tegra_sflash_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) module_platform_driver(tegra_sflash_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) MODULE_ALIAS("platform:spi-tegra-sflash");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) MODULE_DESCRIPTION("NVIDIA Tegra20 Serial Flash Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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