^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2012 - 2014 Allwinner Tech
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Pan Nan <pannan@allwinnertech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2014 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SUN6I_FIFO_DEPTH 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SUN8I_FIFO_DEPTH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SUN6I_GBL_CTL_REG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SUN6I_GBL_CTL_MASTER BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SUN6I_GBL_CTL_TP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SUN6I_GBL_CTL_RST BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SUN6I_TFR_CTL_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SUN6I_TFR_CTL_CPHA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SUN6I_TFR_CTL_CPOL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SUN6I_TFR_CTL_SPOL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SUN6I_TFR_CTL_CS_MASK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SUN6I_TFR_CTL_DHB BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SUN6I_TFR_CTL_FBS BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SUN6I_TFR_CTL_XCH BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SUN6I_INT_CTL_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SUN6I_INT_CTL_RF_RDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SUN6I_INT_CTL_TF_ERQ BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SUN6I_INT_CTL_RF_OVF BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SUN6I_INT_CTL_TC BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SUN6I_INT_STA_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SUN6I_FIFO_CTL_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SUN6I_FIFO_CTL_RF_RST BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SUN6I_FIFO_CTL_TF_RST BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SUN6I_FIFO_STA_REG 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SUN6I_FIFO_STA_RF_CNT_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SUN6I_CLK_CTL_REG 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SUN6I_CLK_CTL_CDR2_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SUN6I_CLK_CTL_CDR1_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SUN6I_CLK_CTL_DRS BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SUN6I_MAX_XFER_SIZE 0xffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SUN6I_BURST_CNT_REG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SUN6I_XMIT_CNT_REG 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SUN6I_BURST_CTL_CNT_REG 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SUN6I_TXDATA_REG 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SUN6I_RXDATA_REG 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct sun6i_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void __iomem *base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct clk *hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk *mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const u8 *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return readl(sspi->base_addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writel(value, sspi->base_addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) reg &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* See how much data is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) len = sun6i_spi_get_rx_fifo_count(sspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) while (len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (sspi->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *sspi->rx_buf++ = byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u8 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* See how much data we can fit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) len = min((int)cnt, sspi->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) while (len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) sspi->len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) reg &= ~SUN6I_TFR_CTL_CS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) reg |= SUN6I_TFR_CTL_CS_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return SUN6I_MAX_XFER_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int sun6i_spi_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct spi_transfer *tfr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct sun6i_spi *sspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int start, end, tx_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int trig_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int tx_len = 0, rx_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (tfr->len > SUN6I_MAX_XFER_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) reinit_completion(&sspi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) sspi->tx_buf = tfr->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) sspi->rx_buf = tfr->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) sspi->len = tfr->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Clear pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Reset FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Setup FIFO interrupt trigger level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Here we choose 3/4 of the full fifo depth, as it's the hardcoded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * value used in old generation of Allwinner SPI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * (See spi-sun4i.c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) trig_level = sspi->fifo_depth / 4 * 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * Setup the transfer control register: Chip Select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * polarities, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) reg |= SUN6I_TFR_CTL_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) reg &= ~SUN6I_TFR_CTL_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) reg |= SUN6I_TFR_CTL_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) reg &= ~SUN6I_TFR_CTL_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (spi->mode & SPI_LSB_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) reg |= SUN6I_TFR_CTL_FBS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) reg &= ~SUN6I_TFR_CTL_FBS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * If it's a TX only transfer, we don't want to fill the RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * FIFO with bogus data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (sspi->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) reg &= ~SUN6I_TFR_CTL_DHB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) rx_len = tfr->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) reg |= SUN6I_TFR_CTL_DHB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* We want to control the chip select manually */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) reg |= SUN6I_TFR_CTL_CS_MANUAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Ensure that we have a parent clock fast enough */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mclk_rate = clk_get_rate(sspi->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (mclk_rate < (2 * tfr->speed_hz)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mclk_rate = clk_get_rate(sspi->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * Setup clock divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * We have two choices there. Either we can use the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * divide rate 1, which is calculated thanks to this formula:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * SPI_CLK = MOD_CLK / (2 ^ cdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * Or we can use CDR2, which is calculated with the formula:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * Wether we use the former or the latter is set through the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * DRS bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * First try CDR2, and if we can't reach the expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * frequency, fall back to CDR1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) reg = SUN6I_CLK_CTL_CDR1(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) tfr->effective_speed_hz = mclk_rate / (1 << div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Finally enable the bus - doing so before might raise SCK to HIGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) reg |= SUN6I_GBL_CTL_BUS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Setup the transfer now... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (sspi->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) tx_len = tfr->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Setup the counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Fill the TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) sun6i_spi_fill_fifo(sspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Enable the interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) reg = SUN6I_INT_CTL_TC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (rx_len > sspi->fifo_depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) reg |= SUN6I_INT_CTL_RF_RDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (tx_len > sspi->fifo_depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) reg |= SUN6I_INT_CTL_TF_ERQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Start the transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) start = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) timeout = wait_for_completion_timeout(&sspi->done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) msecs_to_jiffies(tx_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) end = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev_warn(&master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_name(&spi->dev), tfr->len, tfr->speed_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) jiffies_to_msecs(end - start), tx_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct sun6i_spi *sspi = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Transfer complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (status & SUN6I_INT_CTL_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) sun6i_spi_drain_fifo(sspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) complete(&sspi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* Receive FIFO 3/4 full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (status & SUN6I_INT_CTL_RF_RDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) sun6i_spi_drain_fifo(sspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Only clear the interrupt _after_ draining the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Transmit FIFO 3/4 empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (status & SUN6I_INT_CTL_TF_ERQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) sun6i_spi_fill_fifo(sspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (!sspi->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* nothing left to transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Only clear the interrupt _after_ re-seeding the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int sun6i_spi_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct sun6i_spi *sspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = clk_prepare_enable(sspi->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dev_err(dev, "Couldn't enable AHB clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = clk_prepare_enable(sspi->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_err(dev, "Couldn't enable module clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ret = reset_control_deassert(sspi->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev_err(dev, "Couldn't deassert the device from reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) clk_disable_unprepare(sspi->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) clk_disable_unprepare(sspi->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int sun6i_spi_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct sun6i_spi *sspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) reset_control_assert(sspi->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) clk_disable_unprepare(sspi->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) clk_disable_unprepare(sspi->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static int sun6i_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct sun6i_spi *sspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int ret = 0, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) sspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) sspi->base_addr = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (IS_ERR(sspi->base_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = PTR_ERR(sspi->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) goto err_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) goto err_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 0, "sun6i-spi", sspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dev_err(&pdev->dev, "Cannot request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) goto err_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) sspi->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) master->max_speed_hz = 100 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) master->min_speed_hz = 3 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) master->use_gpio_descriptors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) master->set_cs = sun6i_spi_set_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) master->transfer_one = sun6i_spi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) master->num_chipselect = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) master->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) master->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) master->max_transfer_size = sun6i_spi_max_transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (IS_ERR(sspi->hclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret = PTR_ERR(sspi->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) goto err_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) sspi->mclk = devm_clk_get(&pdev->dev, "mod");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (IS_ERR(sspi->mclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) dev_err(&pdev->dev, "Unable to acquire module clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = PTR_ERR(sspi->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) goto err_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) init_completion(&sspi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (IS_ERR(sspi->rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dev_err(&pdev->dev, "Couldn't get reset controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ret = PTR_ERR(sspi->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) goto err_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * This wake-up/shutdown pattern is to be able to have the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * device woken up, even if runtime_pm is disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret = sun6i_spi_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_err(&pdev->dev, "Couldn't resume the device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) goto err_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) pm_runtime_idle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = devm_spi_register_master(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dev_err(&pdev->dev, "cannot register SPI master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) sun6i_spi_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) err_free_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static int sun6i_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) pm_runtime_force_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static const struct of_device_id sun6i_spi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) MODULE_DEVICE_TABLE(of, sun6i_spi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static const struct dev_pm_ops sun6i_spi_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .runtime_resume = sun6i_spi_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .runtime_suspend = sun6i_spi_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static struct platform_driver sun6i_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .probe = sun6i_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .remove = sun6i_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .name = "sun6i-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .of_match_table = sun6i_spi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .pm = &sun6i_spi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) module_platform_driver(sun6i_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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