^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2012 - 2014 Allwinner Tech
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Pan Nan <pannan@allwinnertech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2014 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SUN4I_FIFO_DEPTH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SUN4I_RXDATA_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SUN4I_TXDATA_REG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SUN4I_CTL_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SUN4I_CTL_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SUN4I_CTL_MASTER BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SUN4I_CTL_CPHA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SUN4I_CTL_CPOL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SUN4I_CTL_CS_ACTIVE_LOW BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SUN4I_CTL_LMTF BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SUN4I_CTL_TF_RST BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SUN4I_CTL_RF_RST BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SUN4I_CTL_XCH BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SUN4I_CTL_CS_MASK 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SUN4I_CTL_DHB BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SUN4I_CTL_CS_MANUAL BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SUN4I_CTL_CS_LEVEL BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SUN4I_CTL_TP BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SUN4I_INT_CTL_REG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SUN4I_INT_CTL_RF_F34 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SUN4I_INT_CTL_TF_E34 BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SUN4I_INT_CTL_TC BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SUN4I_INT_STA_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SUN4I_DMA_CTL_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SUN4I_WAIT_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SUN4I_CLK_CTL_REG 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SUN4I_CLK_CTL_CDR2_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SUN4I_CLK_CTL_CDR1_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SUN4I_CLK_CTL_DRS BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SUN4I_MAX_XFER_SIZE 0xffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SUN4I_BURST_CNT_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SUN4I_XMIT_CNT_REG 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SUN4I_FIFO_STA_REG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SUN4I_FIFO_STA_RF_CNT_BITS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SUN4I_FIFO_STA_TF_CNT_BITS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct sun4i_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void __iomem *base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct clk *hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct clk *mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) const u8 *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return readl(sspi->base_addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) writel(value, sspi->base_addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static inline u32 sun4i_spi_get_tx_fifo_count(struct sun4i_spi *sspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) reg >>= SUN4I_FIFO_STA_TF_CNT_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return reg & SUN4I_FIFO_STA_TF_CNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static inline void sun4i_spi_enable_interrupt(struct sun4i_spi *sspi, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) reg |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static inline void sun4i_spi_disable_interrupt(struct sun4i_spi *sspi, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) reg &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 reg, cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* See how much data is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (len > cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) len = cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) while (len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) byte = readb(sspi->base_addr + SUN4I_RXDATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (sspi->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *sspi->rx_buf++ = byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* See how much data we can fit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) len = min3(len, (int)cnt, sspi->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) while (len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) sspi->len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void sun4i_spi_set_cs(struct spi_device *spi, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct sun4i_spi *sspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) reg &= ~SUN4I_CTL_CS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) reg |= SUN4I_CTL_CS(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* We want to control the chip select manually */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) reg |= SUN4I_CTL_CS_MANUAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) reg |= SUN4I_CTL_CS_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) reg &= ~SUN4I_CTL_CS_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Even though this looks irrelevant since we are supposed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * be controlling the chip select manually, this bit also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * controls the levels of the chip select for inactive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * If we don't set it, the chip select level will go low by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * default when the device is idle, which is not really
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * expected in the common case where the chip select is active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (spi->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) reg &= ~SUN4I_CTL_CS_ACTIVE_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) reg |= SUN4I_CTL_CS_ACTIVE_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static size_t sun4i_spi_max_transfer_size(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return SUN4I_MAX_XFER_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int sun4i_spi_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct spi_transfer *tfr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct sun4i_spi *sspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int mclk_rate, div, timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned int start, end, tx_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int tx_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* We don't support transfer larger than the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (tfr->len > SUN4I_MAX_XFER_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return -EMSGSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (tfr->tx_buf && tfr->len >= SUN4I_MAX_XFER_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return -EMSGSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) reinit_completion(&sspi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) sspi->tx_buf = tfr->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) sspi->rx_buf = tfr->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) sspi->len = tfr->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Clear pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Reset FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) sun4i_spi_write(sspi, SUN4I_CTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Setup the transfer control register: Chip Select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * polarities, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) reg |= SUN4I_CTL_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) reg &= ~SUN4I_CTL_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) reg |= SUN4I_CTL_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) reg &= ~SUN4I_CTL_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (spi->mode & SPI_LSB_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) reg |= SUN4I_CTL_LMTF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) reg &= ~SUN4I_CTL_LMTF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * If it's a TX only transfer, we don't want to fill the RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * FIFO with bogus data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (sspi->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) reg &= ~SUN4I_CTL_DHB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) reg |= SUN4I_CTL_DHB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Ensure that we have a parent clock fast enough */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) mclk_rate = clk_get_rate(sspi->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (mclk_rate < (2 * tfr->speed_hz)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) mclk_rate = clk_get_rate(sspi->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * Setup clock divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * We have two choices there. Either we can use the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * divide rate 1, which is calculated thanks to this formula:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * Or we can use CDR2, which is calculated with the formula:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * Wether we use the former or the latter is set through the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * DRS bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * First try CDR2, and if we can't reach the expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * frequency, fall back to CDR1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) div = mclk_rate / (2 * tfr->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (div > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) div--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) reg = SUN4I_CLK_CTL_CDR1(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Setup the transfer now... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (sspi->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) tx_len = tfr->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Setup the counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * Fill the TX FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * Filling the FIFO fully causes timeout for some reason
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * at least on spi2 on A10s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Enable the interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) SUN4I_INT_CTL_RF_F34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Only enable Tx FIFO interrupt if we really need it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (tx_len > SUN4I_FIFO_DEPTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Start the transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) start = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) timeout = wait_for_completion_timeout(&sspi->done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) msecs_to_jiffies(tx_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) end = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_warn(&master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dev_name(&spi->dev), tfr->len, tfr->speed_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) jiffies_to_msecs(end - start), tx_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static irqreturn_t sun4i_spi_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct sun4i_spi *sspi = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 status = sun4i_spi_read(sspi, SUN4I_INT_STA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Transfer complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (status & SUN4I_INT_CTL_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) complete(&sspi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Receive FIFO 3/4 full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (status & SUN4I_INT_CTL_RF_F34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Only clear the interrupt _after_ draining the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_RF_F34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Transmit FIFO 3/4 empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (status & SUN4I_INT_CTL_TF_E34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (!sspi->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* nothing left to transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) sun4i_spi_disable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* Only clear the interrupt _after_ re-seeding the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TF_E34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int sun4i_spi_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct sun4i_spi *sspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret = clk_prepare_enable(sspi->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_err(dev, "Couldn't enable AHB clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ret = clk_prepare_enable(sspi->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_err(dev, "Couldn't enable module clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) sun4i_spi_write(sspi, SUN4I_CTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) clk_disable_unprepare(sspi->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int sun4i_spi_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct sun4i_spi *sspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) clk_disable_unprepare(sspi->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) clk_disable_unprepare(sspi->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int sun4i_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct sun4i_spi *sspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int ret = 0, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) master = spi_alloc_master(&pdev->dev, sizeof(struct sun4i_spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) sspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) sspi->base_addr = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (IS_ERR(sspi->base_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = PTR_ERR(sspi->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) goto err_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) goto err_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ret = devm_request_irq(&pdev->dev, irq, sun4i_spi_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 0, "sun4i-spi", sspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dev_err(&pdev->dev, "Cannot request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) goto err_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) sspi->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) master->max_speed_hz = 100 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) master->min_speed_hz = 3 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) master->set_cs = sun4i_spi_set_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) master->transfer_one = sun4i_spi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) master->num_chipselect = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) master->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) master->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) master->max_transfer_size = sun4i_spi_max_transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (IS_ERR(sspi->hclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ret = PTR_ERR(sspi->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) goto err_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) sspi->mclk = devm_clk_get(&pdev->dev, "mod");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (IS_ERR(sspi->mclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dev_err(&pdev->dev, "Unable to acquire module clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = PTR_ERR(sspi->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) goto err_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) init_completion(&sspi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * This wake-up/shutdown pattern is to be able to have the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * device woken up, even if runtime_pm is disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = sun4i_spi_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dev_err(&pdev->dev, "Couldn't resume the device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) goto err_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pm_runtime_idle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ret = devm_spi_register_master(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev_err(&pdev->dev, "cannot register SPI master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) sun4i_spi_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) err_free_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int sun4i_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) pm_runtime_force_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static const struct of_device_id sun4i_spi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) { .compatible = "allwinner,sun4i-a10-spi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) MODULE_DEVICE_TABLE(of, sun4i_spi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const struct dev_pm_ops sun4i_spi_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .runtime_resume = sun4i_spi_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .runtime_suspend = sun4i_spi_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static struct platform_driver sun4i_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .probe = sun4i_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .remove = sun4i_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .name = "sun4i-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .of_match_table = sun4i_spi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .pm = &sun4i_spi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) module_platform_driver(sun4i_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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