^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // STMicroelectronics STM32 SPI Controller driver (master mode only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DRIVER_NAME "spi_stm32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* STM32F4 SPI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STM32F4_SPI_CR1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STM32F4_SPI_CR2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define STM32F4_SPI_SR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define STM32F4_SPI_DR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define STM32F4_SPI_I2SCFGR 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* STM32F4_SPI_CR1 bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define STM32F4_SPI_CR1_CPHA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define STM32F4_SPI_CR1_CPOL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define STM32F4_SPI_CR1_MSTR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define STM32F4_SPI_CR1_BR_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define STM32F4_SPI_CR1_BR GENMASK(5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define STM32F4_SPI_CR1_SPE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define STM32F4_SPI_CR1_LSBFRST BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define STM32F4_SPI_CR1_SSI BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define STM32F4_SPI_CR1_SSM BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define STM32F4_SPI_CR1_RXONLY BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define STM32F4_SPI_CR1_DFF BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define STM32F4_SPI_CR1_CRCNEXT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define STM32F4_SPI_CR1_CRCEN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define STM32F4_SPI_CR1_BIDIOE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STM32F4_SPI_CR1_BIDIMODE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define STM32F4_SPI_CR1_BR_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* STM32F4_SPI_CR2 bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define STM32F4_SPI_CR2_RXDMAEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define STM32F4_SPI_CR2_TXDMAEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define STM32F4_SPI_CR2_SSOE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STM32F4_SPI_CR2_FRF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define STM32F4_SPI_CR2_ERRIE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define STM32F4_SPI_CR2_RXNEIE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define STM32F4_SPI_CR2_TXEIE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* STM32F4_SPI_SR bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STM32F4_SPI_SR_RXNE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define STM32F4_SPI_SR_TXE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define STM32F4_SPI_SR_CHSIDE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define STM32F4_SPI_SR_UDR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define STM32F4_SPI_SR_CRCERR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define STM32F4_SPI_SR_MODF BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define STM32F4_SPI_SR_OVR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define STM32F4_SPI_SR_BSY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define STM32F4_SPI_SR_FRE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* STM32F4_SPI_I2SCFGR bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* STM32F4 SPI Baud Rate min/max divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* STM32H7 SPI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define STM32H7_SPI_CR1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define STM32H7_SPI_CR2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define STM32H7_SPI_CFG1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define STM32H7_SPI_CFG2 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define STM32H7_SPI_IER 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define STM32H7_SPI_SR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define STM32H7_SPI_IFCR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define STM32H7_SPI_TXDR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define STM32H7_SPI_RXDR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define STM32H7_SPI_I2SCFGR 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* STM32H7_SPI_CR1 bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define STM32H7_SPI_CR1_SPE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define STM32H7_SPI_CR1_MASRX BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define STM32H7_SPI_CR1_CSTART BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define STM32H7_SPI_CR1_CSUSP BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define STM32H7_SPI_CR1_HDDIR BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define STM32H7_SPI_CR1_SSI BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* STM32H7_SPI_CR2 bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define STM32H7_SPI_CR2_TSIZE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* STM32H7_SPI_CFG1 bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define STM32H7_SPI_CFG1_DSIZE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define STM32H7_SPI_CFG1_FTHLV_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define STM32H7_SPI_CFG1_MBR_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define STM32H7_SPI_CFG1_MBR_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* STM32H7_SPI_CFG2 bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define STM32H7_SPI_CFG2_MIDI_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define STM32H7_SPI_CFG2_COMM_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define STM32H7_SPI_CFG2_SP_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define STM32H7_SPI_CFG2_MASTER BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define STM32H7_SPI_CFG2_LSBFRST BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define STM32H7_SPI_CFG2_CPHA BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define STM32H7_SPI_CFG2_CPOL BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define STM32H7_SPI_CFG2_SSM BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define STM32H7_SPI_CFG2_AFCNTR BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* STM32H7_SPI_IER bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define STM32H7_SPI_IER_RXPIE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define STM32H7_SPI_IER_TXPIE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define STM32H7_SPI_IER_DXPIE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define STM32H7_SPI_IER_EOTIE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define STM32H7_SPI_IER_TXTFIE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define STM32H7_SPI_IER_OVRIE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define STM32H7_SPI_IER_MODFIE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define STM32H7_SPI_IER_ALL GENMASK(10, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* STM32H7_SPI_SR bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define STM32H7_SPI_SR_RXP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define STM32H7_SPI_SR_TXP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define STM32H7_SPI_SR_EOT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define STM32H7_SPI_SR_OVR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define STM32H7_SPI_SR_MODF BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define STM32H7_SPI_SR_SUSP BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define STM32H7_SPI_SR_RXPLVL_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define STM32H7_SPI_SR_RXWNE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* STM32H7_SPI_IFCR bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define STM32H7_SPI_IFCR_ALL GENMASK(11, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* STM32H7_SPI_I2SCFGR bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* STM32H7 SPI Master Baud Rate min/max divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* STM32H7 SPI Communication mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define STM32H7_SPI_FULL_DUPLEX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define STM32H7_SPI_SIMPLEX_TX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define STM32H7_SPI_SIMPLEX_RX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define STM32H7_SPI_HALF_DUPLEX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* SPI Communication type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SPI_FULL_DUPLEX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SPI_SIMPLEX_TX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SPI_SIMPLEX_RX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SPI_3WIRE_TX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SPI_3WIRE_RX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SPI_1HZ_NS 1000000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * without fifo buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SPI_DMA_MIN_BYTES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * struct stm32_spi_reg - stm32 SPI register & bitfield desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @reg: register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @mask: bitfield mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @shift: left shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct stm32_spi_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @en: enable register and SPI enable bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @cpol: clock polarity register and polarity bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @cpha: clock phase register and phase bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * @lsb_first: LSB transmitted first register and bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * @br: baud rate register and bitfields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * @rx: SPI RX data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * @tx: SPI TX data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct stm32_spi_regspec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) const struct stm32_spi_reg en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) const struct stm32_spi_reg dma_rx_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) const struct stm32_spi_reg dma_tx_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) const struct stm32_spi_reg cpol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) const struct stm32_spi_reg cpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) const struct stm32_spi_reg lsb_first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) const struct stm32_spi_reg br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) const struct stm32_spi_reg rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) const struct stm32_spi_reg tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct stm32_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * struct stm32_spi_cfg - stm32 compatible configuration data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @regs: registers descriptions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @get_fifo_size: routine to get fifo size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @get_bpw_mask: routine to get bits per word mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @disable: routine to disable controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @config: routine to configure controller as SPI Master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @set_bpw: routine to configure registers to for bits per word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @set_mode: routine to configure registers to desired mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @set_data_idleness: optional routine to configure registers to desired idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * time between frames (if driver has this functionality)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * @set_number_of_data: optional routine to configure registers to desired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * number of data (if driver has this functionality)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * @can_dma: routine to determine if the transfer is eligible for DMA use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @transfer_one_dma_start: routine to start transfer a single spi_transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * using DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @dma_rx_cb: routine to call after DMA RX channel operation is complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @dma_tx_cb: routine to call after DMA TX channel operation is complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @transfer_one_irq: routine to configure interrupts for driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @irq_handler_event: Interrupt handler for SPI controller events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @irq_handler_thread: thread of interrupt handler for SPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @baud_rate_div_min: minimum baud rate divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * @baud_rate_div_max: maximum baud rate divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * @has_fifo: boolean to know if fifo is used for driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * @has_startbit: boolean to know if start bit is used to start transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct stm32_spi_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) const struct stm32_spi_regspec *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int (*get_fifo_size)(struct stm32_spi *spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int (*get_bpw_mask)(struct stm32_spi *spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) void (*disable)(struct stm32_spi *spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int (*config)(struct stm32_spi *spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void (*set_bpw)(struct stm32_spi *spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) void (*transfer_one_dma_start)(struct stm32_spi *spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) void (*dma_rx_cb)(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) void (*dma_tx_cb)(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int (*transfer_one_irq)(struct stm32_spi *spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) irqreturn_t (*irq_handler_event)(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) irqreturn_t (*irq_handler_thread)(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned int baud_rate_div_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned int baud_rate_div_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) bool has_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * struct stm32_spi - private data of the SPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * @dev: driver model representation of the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * @master: controller master interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * @cfg: compatible configuration data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * @base: virtual memory area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * @clk: hw kernel clock feeding the SPI clock generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * @rst: SPI controller reset line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * @lock: prevent I/O concurrent access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * @irq: SPI controller interrupt line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * @fifo_size: size of the embedded fifo in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * @cur_midi: master inter-data idleness in ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * @cur_speed: speed configured in Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * @cur_bpw: number of bits in a single SPI data frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * @cur_fthlv: fifo threshold level (data frames in a single data packet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * @cur_comm: SPI communication mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * @cur_xferlen: current transfer length in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * @cur_usedma: boolean to know if dma is used in current transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * @tx_buf: data to be written, or NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * @rx_buf: data to be read, or NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * @tx_len: number of data to be written in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * @rx_len: number of data to be read in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * @dma_tx: dma channel for TX transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * @dma_rx: dma channel for RX transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * @phys_addr: SPI registers physical base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct stm32_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) const struct stm32_spi_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) spinlock_t lock; /* prevent I/O concurrent access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned int cur_midi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int cur_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned int cur_bpw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned int cur_fthlv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned int cur_comm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned int cur_xferlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) bool cur_usedma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) const void *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) void *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int tx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct dma_chan *dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct dma_chan *dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dma_addr_t phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const struct stm32_spi_regspec stm32f4_spi_regspec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .rx = { STM32F4_SPI_DR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .tx = { STM32F4_SPI_DR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static const struct stm32_spi_regspec stm32h7_spi_regspec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* SPI data transfer is enabled but spi_ker_ck is idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * CFG1 and CFG2 registers are write protected when SPE is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) STM32H7_SPI_CFG1_MBR_SHIFT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .rx = { STM32H7_SPI_RXDR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .tx = { STM32H7_SPI_TXDR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static inline void stm32_spi_set_bits(struct stm32_spi *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 offset, u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) writel_relaxed(readl_relaxed(spi->base + offset) | bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) spi->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 offset, u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) spi->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * stm32h7_spi_get_fifo_size - Return fifo size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u32 count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) spin_lock_irqsave(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) spin_unlock_irqrestore(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * stm32f4_spi_get_bpw_mask - Return bits per word mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * stm32h7_spi_get_bpw_mask - Return bits per word mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 cfg1, max_bpw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) spin_lock_irqsave(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * The most significant bit at DSIZE bit field is reserved when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * maximum data size of periperal instances is limited to 16-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) STM32H7_SPI_CFG1_DSIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) max_bpw += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) spin_unlock_irqrestore(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return SPI_BPW_RANGE_MASK(4, max_bpw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * stm32_spi_prepare_mbr - Determine baud rate divisor value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * @speed_hz: requested speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * @min_div: minimum baud rate divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * @max_div: maximum baud rate divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * Return baud rate divisor value in case of success or -EINVAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u32 min_div, u32 max_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u32 div, mbrdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Ensure spi->clk_rate is even */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * SPI framework set xfer->speed_hz to master->max_speed_hz if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * xfer->speed_hz is greater than master->max_speed_hz, and it returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * an error when xfer->speed_hz is lower than master->min_speed_hz, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * no need to check it there.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * However, we need to ensure the following calculations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if ((div < min_div) || (div > max_div))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Determine the first power of 2 greater than or equal to div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (div & (div - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) mbrdiv = fls(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) mbrdiv = fls(div) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return mbrdiv - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * @xfer_len: length of the message to be transferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u32 fthlv, half_fifo, packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* data packet should not exceed 1/2 of fifo space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) half_fifo = (spi->fifo_size / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* data_packet should not exceed transfer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (half_fifo > xfer_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) packet = xfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) packet = half_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (spi->cur_bpw <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) fthlv = packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) else if (spi->cur_bpw <= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) fthlv = packet / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) fthlv = packet / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* align packet size with data registers access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (spi->cur_bpw > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) fthlv += (fthlv % 2) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) fthlv += (fthlv % 4) ? (4 - (fthlv % 4)) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (!fthlv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) fthlv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return fthlv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * Read from tx_buf depends on remaining bytes to avoid to read beyond
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * tx_buf end.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static void stm32f4_spi_write_tx(struct stm32_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) STM32F4_SPI_SR_TXE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u32 offs = spi->cur_xferlen - spi->tx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (spi->cur_bpw == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) spi->tx_len -= sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) spi->tx_len -= sizeof(u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * Read from tx_buf depends on remaining bytes to avoid to read beyond
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * tx_buf end.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) while ((spi->tx_len > 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) (readl_relaxed(spi->base + STM32H7_SPI_SR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) STM32H7_SPI_SR_TXP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u32 offs = spi->cur_xferlen - spi->tx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (spi->tx_len >= sizeof(u32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) spi->tx_len -= sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) } else if (spi->tx_len >= sizeof(u16)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) spi->tx_len -= sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) spi->tx_len -= sizeof(u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * stm32f4_spi_read_rx - Read bytes from Receive Data Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * Write in rx_buf depends on remaining bytes to avoid to write beyond
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * rx_buf end.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static void stm32f4_spi_read_rx(struct stm32_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) STM32F4_SPI_SR_RXNE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u32 offs = spi->cur_xferlen - spi->rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (spi->cur_bpw == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) spi->rx_len -= sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) spi->rx_len -= sizeof(u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * @flush: boolean indicating that FIFO should be flushed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * Write in rx_buf depends on remaining bytes to avoid to write beyond
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * rx_buf end.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) STM32H7_SPI_SR_RXPLVL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) while ((spi->rx_len > 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ((sr & STM32H7_SPI_SR_RXP) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) (flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u32 offs = spi->cur_xferlen - spi->rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if ((spi->rx_len >= sizeof(u32)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) (flush && (sr & STM32H7_SPI_SR_RXWNE))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) spi->rx_len -= sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) } else if ((spi->rx_len >= sizeof(u16)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) spi->rx_len -= sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) spi->rx_len -= sizeof(u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) STM32H7_SPI_SR_RXPLVL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) flush ? "(flush)" : "", spi->rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * stm32_spi_enable - Enable SPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static void stm32_spi_enable(struct stm32_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dev_dbg(spi->dev, "enable controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) spi->cfg->regs->en.mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * stm32f4_spi_disable - Disable SPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static void stm32f4_spi_disable(struct stm32_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u32 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dev_dbg(spi->dev, "disable controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) spin_lock_irqsave(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) STM32F4_SPI_CR1_SPE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) spin_unlock_irqrestore(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) STM32F4_SPI_CR2_RXNEIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) STM32F4_SPI_CR2_ERRIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Wait until BSY = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) sr, !(sr & STM32F4_SPI_SR_BSY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 10, 100000) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_warn(spi->dev, "disabling condition timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (spi->cur_usedma && spi->dma_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dmaengine_terminate_all(spi->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (spi->cur_usedma && spi->dma_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dmaengine_terminate_all(spi->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) STM32F4_SPI_CR2_RXDMAEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Sequence to clear OVR flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) readl_relaxed(spi->base + STM32F4_SPI_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) readl_relaxed(spi->base + STM32F4_SPI_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) spin_unlock_irqrestore(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * stm32h7_spi_disable - Disable SPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * RX-Fifo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * Normally, if TSIZE has been configured, we should relax the hardware at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * reception of the EOT interrupt. But in case of error, EOT will not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * raised. So the subsystem unprepare_message call allows us to properly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * complete the transfer from an hardware point of view.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static void stm32h7_spi_disable(struct stm32_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) u32 cr1, sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dev_dbg(spi->dev, "disable controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) spin_lock_irqsave(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) spin_unlock_irqrestore(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* Wait on EOT or suspend the flow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) sr, !(sr & STM32H7_SPI_SR_EOT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 10, 100000) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (cr1 & STM32H7_SPI_CR1_CSTART) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) spi->base + STM32H7_SPI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (readl_relaxed_poll_timeout_atomic(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) spi->base + STM32H7_SPI_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) sr, !(sr & STM32H7_SPI_SR_SUSP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 10, 100000) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_warn(spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) "Suspend request timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) stm32h7_spi_read_rxfifo(spi, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (spi->cur_usedma && spi->dma_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dmaengine_terminate_all(spi->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (spi->cur_usedma && spi->dma_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) dmaengine_terminate_all(spi->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) STM32H7_SPI_CFG1_RXDMAEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* Disable interrupts and clear status flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) writel_relaxed(0, spi->base + STM32H7_SPI_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) spin_unlock_irqrestore(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * @master: controller master interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * @spi_dev: pointer to the spi device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * @transfer: pointer to spi transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * If driver has fifo and the current transfer size is greater than fifo size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static bool stm32_spi_can_dma(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct spi_device *spi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct spi_transfer *transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) unsigned int dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct stm32_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (spi->cfg->has_fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dma_size = spi->fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dma_size = SPI_DMA_MIN_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dev_dbg(spi->dev, "%s: %s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) (transfer->len > dma_size) ? "true" : "false");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return (transfer->len > dma_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * @irq: interrupt line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * @dev_id: SPI controller master interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct spi_master *master = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct stm32_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u32 sr, mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) bool end = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) spin_lock(&spi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) sr = readl_relaxed(spi->base + STM32F4_SPI_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * BSY flag is not handled in interrupt but it is normal behavior when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * this flag is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) sr &= ~STM32F4_SPI_SR_BSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) spi->cur_comm == SPI_3WIRE_TX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* OVR flag shouldn't be handled for TX only mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) sr &= ~STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) mask |= STM32F4_SPI_SR_TXE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) spi->cur_comm == SPI_SIMPLEX_RX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) spi->cur_comm == SPI_3WIRE_RX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* TXE flag is set and is handled when RXNE flag occurs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) sr &= ~STM32F4_SPI_SR_TXE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (!(sr & mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) spin_unlock(&spi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (sr & STM32F4_SPI_SR_OVR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dev_warn(spi->dev, "Overrun: received value discarded\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* Sequence to clear OVR flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) readl_relaxed(spi->base + STM32F4_SPI_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) readl_relaxed(spi->base + STM32F4_SPI_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * If overrun is detected, it means that something went wrong,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * so stop the current transfer. Transfer can wait for next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * RXNE but DR is already read and end never happens.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) end = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) goto end_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (sr & STM32F4_SPI_SR_TXE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (spi->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) stm32f4_spi_write_tx(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (spi->tx_len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) end = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (sr & STM32F4_SPI_SR_RXNE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) stm32f4_spi_read_rx(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (spi->rx_len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) end = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) else if (spi->tx_buf)/* Load data for discontinuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) stm32f4_spi_write_tx(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) end_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* Immediately disable interrupts to do not generate new one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) stm32_spi_clr_bits(spi, STM32F4_SPI_CR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) STM32F4_SPI_CR2_TXEIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) STM32F4_SPI_CR2_RXNEIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) STM32F4_SPI_CR2_ERRIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) spin_unlock(&spi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) spin_unlock(&spi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * @irq: interrupt line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * @dev_id: SPI controller master interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct spi_master *master = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct stm32_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) spi_finalize_current_transfer(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) stm32f4_spi_disable(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * @irq: interrupt line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * @dev_id: SPI controller master interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct spi_master *master = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct stm32_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) u32 sr, ier, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) bool end = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) spin_lock_irqsave(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) mask = ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * EOTIE enables irq from EOT, SUSP and TXC events. We need to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * SUSP to acknowledge it later. TXC is automatically cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) mask |= STM32H7_SPI_SR_SUSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * are set. So in case of Full-Duplex, need to poll TXP and RXP event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) mask |= STM32H7_SPI_SR_TXP | STM32H7_SPI_SR_RXP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (!(sr & mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) sr, ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) spin_unlock_irqrestore(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (sr & STM32H7_SPI_SR_SUSP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static DEFINE_RATELIMIT_STATE(rs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) DEFAULT_RATELIMIT_INTERVAL * 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (__ratelimit(&rs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) stm32h7_spi_read_rxfifo(spi, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * If communication is suspended while using DMA, it means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * that something went wrong, so stop the current transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (spi->cur_usedma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) end = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (sr & STM32H7_SPI_SR_MODF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) dev_warn(spi->dev, "Mode fault: transfer aborted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) end = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (sr & STM32H7_SPI_SR_OVR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) dev_err(spi->dev, "Overrun: RX data lost\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) end = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (sr & STM32H7_SPI_SR_EOT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) stm32h7_spi_read_rxfifo(spi, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) end = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (sr & STM32H7_SPI_SR_TXP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) stm32h7_spi_write_txfifo(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (sr & STM32H7_SPI_SR_RXP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) stm32h7_spi_read_rxfifo(spi, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) spin_unlock_irqrestore(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) stm32h7_spi_disable(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) spi_finalize_current_transfer(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * stm32_spi_prepare_msg - set up the controller to transfer a single message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * @master: controller master interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * @msg: pointer to spi message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static int stm32_spi_prepare_msg(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct stm32_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct spi_device *spi_dev = msg->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct device_node *np = spi_dev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) u32 clrb = 0, setb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* SPI slave device may need time between data frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) spi->cur_midi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (spi_dev->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) setb |= spi->cfg->regs->cpol.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) clrb |= spi->cfg->regs->cpol.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (spi_dev->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) setb |= spi->cfg->regs->cpha.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) clrb |= spi->cfg->regs->cpha.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (spi_dev->mode & SPI_LSB_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) setb |= spi->cfg->regs->lsb_first.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) clrb |= spi->cfg->regs->lsb_first.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) spi_dev->mode & SPI_CPOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) spi_dev->mode & SPI_CPHA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) spi_dev->mode & SPI_LSB_FIRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) spi_dev->mode & SPI_CS_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) spin_lock_irqsave(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* CPOL, CPHA and LSB FIRST bits have common register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (clrb || setb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) writel_relaxed(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ~clrb) | setb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) spi->base + spi->cfg->regs->cpol.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) spin_unlock_irqrestore(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * stm32f4_spi_dma_tx_cb - dma callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * @data: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * DMA callback is called when the transfer is complete for DMA TX channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static void stm32f4_spi_dma_tx_cb(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct stm32_spi *spi = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) spi_finalize_current_transfer(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) stm32f4_spi_disable(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * stm32f4_spi_dma_rx_cb - dma callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * @data: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * DMA callback is called when the transfer is complete for DMA RX channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static void stm32f4_spi_dma_rx_cb(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct stm32_spi *spi = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) spi_finalize_current_transfer(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) stm32f4_spi_disable(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * stm32h7_spi_dma_cb - dma callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * @data: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * DMA callback is called when the transfer is complete or when an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * occurs. If the transfer is complete, EOT flag is raised.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static void stm32h7_spi_dma_cb(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct stm32_spi *spi = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) u32 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) spin_lock_irqsave(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) spin_unlock_irqrestore(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (!(sr & STM32H7_SPI_SR_EOT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* Now wait for EOT, or SUSP or OVR in case of error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * stm32_spi_dma_config - configure dma slave channel depending on current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) * transfer bits_per_word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * @dma_conf: pointer to the dma_slave_config structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * @dir: direction of the dma transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static void stm32_spi_dma_config(struct stm32_spi *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) struct dma_slave_config *dma_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) enum dma_transfer_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) enum dma_slave_buswidth buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) u32 maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (spi->cur_bpw <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) else if (spi->cur_bpw <= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (spi->cfg->has_fifo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* Valid for DMA Half or Full Fifo threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (spi->cur_fthlv == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) maxburst = spi->cur_fthlv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) memset(dma_conf, 0, sizeof(struct dma_slave_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) dma_conf->direction = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) dma_conf->src_addr_width = buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) dma_conf->src_maxburst = maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) buswidth, maxburst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) dma_conf->dst_addr_width = buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) dma_conf->dst_maxburst = maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) buswidth, maxburst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * It must returns 0 if the transfer is finished or 1 if the transfer is still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * in progress.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) u32 cr2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /* Enable the interrupts relative to the current communication mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) cr2 |= STM32F4_SPI_CR2_TXEIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) } else if (spi->cur_comm == SPI_FULL_DUPLEX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) spi->cur_comm == SPI_SIMPLEX_RX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) spi->cur_comm == SPI_3WIRE_RX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) /* In transmit-only mode, the OVR flag is set in the SR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * since the received data are never read. Therefore set OVR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * interrupt only when rx buffer is available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) cr2 |= STM32F4_SPI_CR2_RXNEIE | STM32F4_SPI_CR2_ERRIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) spin_lock_irqsave(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) stm32_spi_enable(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* starting data transfer when buffer is loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (spi->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) stm32f4_spi_write_tx(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) spin_unlock_irqrestore(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) * interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * It must returns 0 if the transfer is finished or 1 if the transfer is still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * in progress.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) u32 ier = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /* Enable the interrupts relative to the current communication mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ier |= STM32H7_SPI_IER_DXPIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) ier |= STM32H7_SPI_IER_TXPIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) ier |= STM32H7_SPI_IER_RXPIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /* Enable the interrupts relative to the end of transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) spin_lock_irqsave(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) stm32_spi_enable(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /* Be sure to have data in fifo before starting data transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (spi->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) stm32h7_spi_write_txfifo(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) spin_unlock_irqrestore(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * transfer using DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* In DMA mode end of transfer is handled by DMA TX or RX callback. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) spi->cur_comm == SPI_FULL_DUPLEX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) * In transmit-only mode, the OVR flag is set in the SR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) * since the received data are never read. Therefore set OVR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * interrupt only when rx buffer is available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) stm32_spi_enable(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * transfer using DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /* Enable the interrupts relative to the end of transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) stm32_spi_set_bits(spi, STM32H7_SPI_IER, STM32H7_SPI_IER_EOTIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) STM32H7_SPI_IER_TXTFIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) STM32H7_SPI_IER_OVRIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) STM32H7_SPI_IER_MODFIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) stm32_spi_enable(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) * @xfer: pointer to the spi_transfer structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) * It must returns 0 if the transfer is finished or 1 if the transfer is still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * in progress.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) struct dma_slave_config tx_dma_conf, rx_dma_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) spin_lock_irqsave(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) rx_dma_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (spi->rx_buf && spi->dma_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /* Enable Rx DMA request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) spi->cfg->regs->dma_rx_en.mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) rx_dma_desc = dmaengine_prep_slave_sg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) spi->dma_rx, xfer->rx_sg.sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) xfer->rx_sg.nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) rx_dma_conf.direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) DMA_PREP_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) tx_dma_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (spi->tx_buf && spi->dma_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) tx_dma_desc = dmaengine_prep_slave_sg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) spi->dma_tx, xfer->tx_sg.sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) xfer->tx_sg.nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) tx_dma_conf.direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) DMA_PREP_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) (spi->rx_buf && spi->dma_rx && !rx_dma_desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) goto dma_desc_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) goto dma_desc_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (rx_dma_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) rx_dma_desc->callback = spi->cfg->dma_rx_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) rx_dma_desc->callback_param = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) dev_err(spi->dev, "Rx DMA submit failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) goto dma_desc_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* Enable Rx DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) dma_async_issue_pending(spi->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (tx_dma_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (spi->cur_comm == SPI_SIMPLEX_TX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) spi->cur_comm == SPI_3WIRE_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) tx_dma_desc->callback = spi->cfg->dma_tx_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) tx_dma_desc->callback_param = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) dev_err(spi->dev, "Tx DMA submit failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) goto dma_submit_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /* Enable Tx DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) dma_async_issue_pending(spi->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) /* Enable Tx DMA request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) spi->cfg->regs->dma_tx_en.mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) spi->cfg->transfer_one_dma_start(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) spin_unlock_irqrestore(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) dma_submit_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (spi->dma_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) dmaengine_terminate_all(spi->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) dma_desc_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) spi->cfg->regs->dma_rx_en.mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) spin_unlock_irqrestore(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) spi->cur_usedma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) return spi->cfg->transfer_one_irq(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) * stm32f4_spi_set_bpw - Configure bits per word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (spi->cur_bpw == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * stm32h7_spi_set_bpw - configure bits per word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) u32 bpw, fthlv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) u32 cfg1_clrb = 0, cfg1_setb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) bpw = spi->cur_bpw - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) STM32H7_SPI_CFG1_DSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) fthlv = spi->cur_fthlv - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) STM32H7_SPI_CFG1_FTHLV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) writel_relaxed(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) (readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) ~cfg1_clrb) | cfg1_setb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) spi->base + STM32H7_SPI_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) * stm32_spi_set_mbr - Configure baud rate divisor in master mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) * @mbrdiv: baud rate divisor value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) u32 clrb = 0, setb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) clrb |= spi->cfg->regs->br.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) spi->cfg->regs->br.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) ~clrb) | setb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) spi->base + spi->cfg->regs->br.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) * stm32_spi_communication_type - return transfer communication type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) * @spi_dev: pointer to the spi device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * @transfer: pointer to spi transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) struct spi_transfer *transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) unsigned int type = SPI_FULL_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) * is forbidden and unvalidated by SPI subsystem so depending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) * on the valid buffer, we can determine the direction of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) * transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (!transfer->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) type = SPI_3WIRE_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) type = SPI_3WIRE_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (!transfer->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) type = SPI_SIMPLEX_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) else if (!transfer->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) type = SPI_SIMPLEX_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) return type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * stm32f4_spi_set_mode - configure communication mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) * @comm_type: type of communication to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) STM32F4_SPI_CR1_BIDIMODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) STM32F4_SPI_CR1_BIDIOE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) } else if (comm_type == SPI_FULL_DUPLEX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) comm_type == SPI_SIMPLEX_RX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) STM32F4_SPI_CR1_BIDIMODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) STM32F4_SPI_CR1_BIDIOE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) } else if (comm_type == SPI_3WIRE_RX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) STM32F4_SPI_CR1_BIDIMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) STM32F4_SPI_CR1_BIDIOE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) * stm32h7_spi_set_mode - configure communication mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) * @comm_type: type of communication to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) u32 cfg2_clrb = 0, cfg2_setb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) if (comm_type == SPI_3WIRE_RX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) mode = STM32H7_SPI_HALF_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) } else if (comm_type == SPI_3WIRE_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) mode = STM32H7_SPI_HALF_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) } else if (comm_type == SPI_SIMPLEX_RX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) mode = STM32H7_SPI_SIMPLEX_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) } else if (comm_type == SPI_SIMPLEX_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) mode = STM32H7_SPI_SIMPLEX_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) mode = STM32H7_SPI_FULL_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) STM32H7_SPI_CFG2_COMM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) writel_relaxed(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) (readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) ~cfg2_clrb) | cfg2_setb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) spi->base + STM32H7_SPI_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) * consecutive data frames in master mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) * @len: transfer len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) u32 cfg2_clrb = 0, cfg2_setb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if ((len > 1) && (spi->cur_midi > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) (u32)STM32H7_SPI_CFG2_MIDI >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) STM32H7_SPI_CFG2_MIDI_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) sck_period_ns, midi, midi * sck_period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) STM32H7_SPI_CFG2_MIDI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) ~cfg2_clrb) | cfg2_setb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) spi->base + STM32H7_SPI_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) * stm32h7_spi_number_of_data - configure number of data at current transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * @nb_words: transfer length (in words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) u32 cr2_clrb = 0, cr2_setb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) if (nb_words <= (STM32H7_SPI_CR2_TSIZE >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) STM32H7_SPI_CR2_TSIZE_SHIFT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) cr2_clrb |= STM32H7_SPI_CR2_TSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) cr2_setb = nb_words << STM32H7_SPI_CR2_TSIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) ~cr2_clrb) | cr2_setb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) spi->base + STM32H7_SPI_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) return -EMSGSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) * stm32_spi_transfer_one_setup - common setup to transfer a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) * spi_transfer either using DMA or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) * @spi_dev: pointer to the spi device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) * @transfer: pointer to spi transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) struct spi_device *spi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) struct spi_transfer *transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) unsigned int comm_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) int nb_words, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) int mbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) spin_lock_irqsave(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) spi->cur_xferlen = transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) spi->cur_bpw = transfer->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) spi->cfg->set_bpw(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) /* Update spi->cur_speed with real clock speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) spi->cfg->baud_rate_div_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) spi->cfg->baud_rate_div_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) if (mbr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) ret = mbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) transfer->speed_hz = spi->cur_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) stm32_spi_set_mbr(spi, mbr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) comm_type = stm32_spi_communication_type(spi_dev, transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) ret = spi->cfg->set_mode(spi, comm_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) spi->cur_comm = comm_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (spi->cfg->set_data_idleness)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) spi->cfg->set_data_idleness(spi, transfer->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) if (spi->cur_bpw <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) nb_words = transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) else if (spi->cur_bpw <= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (spi->cfg->set_number_of_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) ret = spi->cfg->set_number_of_data(spi, nb_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) dev_dbg(spi->dev, "transfer communication mode set to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) spi->cur_comm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) dev_dbg(spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) "data frame of %d-bit, data packet of %d data frames\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) spi->cur_bpw, spi->cur_fthlv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) spi->cur_xferlen, nb_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) dev_dbg(spi->dev, "dma %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) (spi->cur_usedma) ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) spin_unlock_irqrestore(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) * stm32_spi_transfer_one - transfer a single spi_transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) * @master: controller master interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) * @spi_dev: pointer to the spi device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) * @transfer: pointer to spi transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) * It must return 0 if the transfer is finished or 1 if the transfer is still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) * in progress.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) static int stm32_spi_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) struct spi_device *spi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) struct spi_transfer *transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) struct stm32_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) /* Don't do anything on 0 bytes transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (transfer->len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) spi->tx_buf = transfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) spi->rx_buf = transfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) spi->tx_len = spi->tx_buf ? transfer->len : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) spi->rx_len = spi->rx_buf ? transfer->len : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) spi->cur_usedma = (master->can_dma &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) master->can_dma(master, spi_dev, transfer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) dev_err(spi->dev, "SPI transfer setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) if (spi->cur_usedma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) return stm32_spi_transfer_one_dma(spi, transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) return spi->cfg->transfer_one_irq(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) * stm32_spi_unprepare_msg - relax the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) * @master: controller master interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) * @msg: pointer to the spi message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) static int stm32_spi_unprepare_msg(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) struct stm32_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) spi->cfg->disable(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) * stm32f4_spi_config - Configure SPI controller as SPI master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) static int stm32f4_spi_config(struct stm32_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) spin_lock_irqsave(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) /* Ensure I2SMOD bit is kept cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) STM32F4_SPI_I2SCFGR_I2SMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) * - SS input value high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) * - transmitter half duplex direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) * - Set the master mode (default Motorola mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) * - Consider 1 master/n slaves configuration and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) * SS input value is determined by the SSI bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) STM32F4_SPI_CR1_BIDIOE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) STM32F4_SPI_CR1_MSTR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) STM32F4_SPI_CR1_SSM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) spin_unlock_irqrestore(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) * stm32h7_spi_config - Configure SPI controller as SPI master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) * @spi: pointer to the spi controller data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) static int stm32h7_spi_config(struct stm32_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) spin_lock_irqsave(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) /* Ensure I2SMOD bit is kept cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) STM32H7_SPI_I2SCFGR_I2SMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) * - SS input value high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) * - transmitter half duplex direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) * - automatic communication suspend when RX-Fifo is full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) STM32H7_SPI_CR1_HDDIR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) STM32H7_SPI_CR1_MASRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) * - Set the master mode (default Motorola mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) * - Consider 1 master/n slaves configuration and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) * SS input value is determined by the SSI bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) * - keep control of all associated GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) STM32H7_SPI_CFG2_SSM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) STM32H7_SPI_CFG2_AFCNTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) spin_unlock_irqrestore(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) static const struct stm32_spi_cfg stm32f4_spi_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .regs = &stm32f4_spi_regspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .get_bpw_mask = stm32f4_spi_get_bpw_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .disable = stm32f4_spi_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .config = stm32f4_spi_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .set_bpw = stm32f4_spi_set_bpw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .set_mode = stm32f4_spi_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .dma_tx_cb = stm32f4_spi_dma_tx_cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .dma_rx_cb = stm32f4_spi_dma_rx_cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .transfer_one_irq = stm32f4_spi_transfer_one_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .irq_handler_event = stm32f4_spi_irq_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .irq_handler_thread = stm32f4_spi_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .has_fifo = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) static const struct stm32_spi_cfg stm32h7_spi_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .regs = &stm32h7_spi_regspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .get_fifo_size = stm32h7_spi_get_fifo_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .get_bpw_mask = stm32h7_spi_get_bpw_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .disable = stm32h7_spi_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .config = stm32h7_spi_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .set_bpw = stm32h7_spi_set_bpw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .set_mode = stm32h7_spi_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .set_data_idleness = stm32h7_spi_data_idleness,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .set_number_of_data = stm32h7_spi_number_of_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .dma_rx_cb = stm32h7_spi_dma_cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .dma_tx_cb = stm32h7_spi_dma_cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .transfer_one_irq = stm32h7_spi_transfer_one_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .irq_handler_thread = stm32h7_spi_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .has_fifo = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) static const struct of_device_id stm32_spi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) static int stm32_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) struct stm32_spi *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) master = devm_spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) dev_err(&pdev->dev, "spi master allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) spi->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) spi->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) spin_lock_init(&spi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) spi->cfg = (const struct stm32_spi_cfg *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) of_match_device(pdev->dev.driver->of_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) &pdev->dev)->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) spi->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) if (IS_ERR(spi->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) return PTR_ERR(spi->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) spi->phys_addr = (dma_addr_t)res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) spi->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (spi->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) return dev_err_probe(&pdev->dev, spi->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) "failed to get irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) spi->cfg->irq_handler_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) spi->cfg->irq_handler_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) IRQF_ONESHOT, pdev->name, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) spi->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (IS_ERR(spi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) ret = PTR_ERR(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) dev_err(&pdev->dev, "clk get failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) ret = clk_prepare_enable(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) spi->clk_rate = clk_get_rate(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) if (!spi->clk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) dev_err(&pdev->dev, "clk rate = 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) if (!IS_ERR(spi->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) reset_control_assert(spi->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) reset_control_deassert(spi->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) if (spi->cfg->has_fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) spi->fifo_size = spi->cfg->get_fifo_size(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) ret = spi->cfg->config(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) dev_err(&pdev->dev, "controller configuration failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) master->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) master->bus_num = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) SPI_3WIRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) master->use_gpio_descriptors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) master->prepare_message = stm32_spi_prepare_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) master->transfer_one = stm32_spi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) master->unprepare_message = stm32_spi_unprepare_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) master->flags = SPI_MASTER_MUST_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) spi->dma_tx = dma_request_chan(spi->dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) if (IS_ERR(spi->dma_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) ret = PTR_ERR(spi->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) spi->dma_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) dev_warn(&pdev->dev, "failed to request tx dma channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) master->dma_tx = spi->dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) spi->dma_rx = dma_request_chan(spi->dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) if (IS_ERR(spi->dma_rx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) ret = PTR_ERR(spi->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) spi->dma_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) goto err_dma_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) dev_warn(&pdev->dev, "failed to request rx dma channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) master->dma_rx = spi->dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (spi->dma_tx || spi->dma_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) master->can_dma = stm32_spi_can_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) pm_runtime_get_noresume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) ret = spi_register_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) dev_err(&pdev->dev, "spi master registration failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (!master->cs_gpiods) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) dev_err(&pdev->dev, "no CS gpios available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) dev_info(&pdev->dev, "driver initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) err_dma_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) if (spi->dma_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) dma_release_channel(spi->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) if (spi->dma_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) dma_release_channel(spi->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) clk_disable_unprepare(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) static int stm32_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) struct stm32_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) spi_unregister_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) spi->cfg->disable(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) if (master->dma_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) dma_release_channel(master->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) if (master->dma_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) dma_release_channel(master->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) clk_disable_unprepare(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) pinctrl_pm_select_sleep_state(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) static int stm32_spi_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) struct stm32_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) clk_disable_unprepare(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) return pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) static int stm32_spi_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) struct stm32_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) ret = pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) return clk_prepare_enable(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) static int stm32_spi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) ret = spi_master_suspend(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) return pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) static int stm32_spi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) struct stm32_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) ret = pm_runtime_force_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) ret = spi_master_resume(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) clk_disable_unprepare(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) dev_err(dev, "Unable to power device:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) spi->cfg->config(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) pm_runtime_mark_last_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) pm_runtime_put_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) static const struct dev_pm_ops stm32_spi_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) stm32_spi_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) static struct platform_driver stm32_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .probe = stm32_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .remove = stm32_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .pm = &stm32_spi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .of_match_table = stm32_spi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) module_platform_driver(stm32_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) MODULE_ALIAS("platform:" DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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