Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/spi/spi-mem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define QSPI_CR			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CR_EN			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CR_ABORT		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CR_DMAEN		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CR_TCEN			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CR_SSHIFT		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CR_DFM			BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CR_FSEL			BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CR_FTHRES_SHIFT		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CR_TEIE			BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CR_TCIE			BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CR_FTIE			BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CR_SMIE			BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CR_TOIE			BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CR_PRESC_MASK		GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define QSPI_DCR		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define DCR_FSIZE_MASK		GENMASK(20, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define QSPI_SR			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SR_TEF			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SR_TCF			BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SR_FTF			BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SR_SMF			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SR_TOF			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SR_BUSY			BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SR_FLEVEL_MASK		GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define QSPI_FCR		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define FCR_CTEF		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define FCR_CTCF		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define QSPI_DLR		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define QSPI_CCR		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CCR_INST_MASK		GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CCR_IMODE_MASK		GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CCR_ADMODE_MASK		GENMASK(11, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CCR_ADSIZE_MASK		GENMASK(13, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CCR_DCYC_MASK		GENMASK(22, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CCR_DMODE_MASK		GENMASK(25, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CCR_FMODE_MASK		GENMASK(27, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CCR_FMODE_INDW		(0U << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CCR_FMODE_INDR		(1U << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CCR_FMODE_APM		(2U << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CCR_FMODE_MM		(3U << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CCR_BUSWIDTH_0		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CCR_BUSWIDTH_1		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CCR_BUSWIDTH_2		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CCR_BUSWIDTH_4		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define QSPI_AR			0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define QSPI_ABR		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define QSPI_DR			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define QSPI_PSMKR		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define QSPI_PSMAR		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define QSPI_PIR		0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define QSPI_LPTR		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define STM32_QSPI_MAX_MMAP_SZ	SZ_256M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define STM32_QSPI_MAX_NORCHIP	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define STM32_FIFO_TIMEOUT_US 30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define STM32_BUSY_TIMEOUT_US 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define STM32_ABT_TIMEOUT_US 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define STM32_COMP_TIMEOUT_MS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define STM32_AUTOSUSPEND_DELAY -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) struct stm32_qspi_flash {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct stm32_qspi *qspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u32 cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u32 presc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) struct stm32_qspi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct spi_controller *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	phys_addr_t phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	void __iomem *mm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	resource_size_t mm_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	u32 clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct completion data_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	u32 fmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct dma_chan *dma_chtx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct dma_chan *dma_chrx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct completion dma_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u32 cr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u32 dcr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 * to protect device configuration, could be different between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 * 2 flash access (bk1, bk2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u32 cr, sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	sr = readl_relaxed(qspi->io_base + QSPI_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (sr & (SR_TEF | SR_TCF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		/* disable irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		cr = readl_relaxed(qspi->io_base + QSPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		cr &= ~CR_TCIE & ~CR_TEIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		writel_relaxed(cr, qspi->io_base + QSPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		complete(&qspi->data_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	*val = readb_relaxed(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	writeb_relaxed(*val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			      const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	void (*tx_fifo)(u8 *val, void __iomem *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	u32 len = op->data.nbytes, sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (op->data.dir == SPI_MEM_DATA_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		tx_fifo = stm32_qspi_read_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		buf = op->data.buf.in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		tx_fifo = stm32_qspi_write_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		buf = (u8 *)op->data.buf.out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	while (len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 							sr, (sr & SR_FTF), 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 							STM32_FIFO_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				len, sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		tx_fifo(buf++, qspi->io_base + QSPI_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			    const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		      op->data.nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void stm32_qspi_dma_callback(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct completion *dma_completion = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	complete(dma_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int stm32_qspi_tx_dma(struct stm32_qspi *qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			     const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	enum dma_transfer_direction dma_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct dma_chan *dma_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct sg_table sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	u32 cr, t_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (op->data.dir == SPI_MEM_DATA_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		dma_dir = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		dma_ch = qspi->dma_chrx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		dma_dir = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		dma_ch = qspi->dma_chtx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 * spi_map_buf return -EINVAL if the buffer is not DMA-able
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	 * (DMA-able: in vmalloc | kmap | virt_addr_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	err = spi_controller_dma_map_mem_op_data(qspi->ctrl, op, &sgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	desc = dmaengine_prep_slave_sg(dma_ch, sgt.sgl, sgt.nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 				       dma_dir, DMA_PREP_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	cr = readl_relaxed(qspi->io_base + QSPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	reinit_completion(&qspi->dma_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	desc->callback = stm32_qspi_dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	desc->callback_param = &qspi->dma_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	cookie = dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	err = dma_submit_error(cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	dma_async_issue_pending(dma_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	t_out = sgt.nents * STM32_COMP_TIMEOUT_MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (!wait_for_completion_timeout(&qspi->dma_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 					 msecs_to_jiffies(t_out)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		dmaengine_terminate_all(dma_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	spi_controller_dma_unmap_mem_op_data(qspi->ctrl, op, &sgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int stm32_qspi_tx(struct stm32_qspi *qspi, const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (!op->data.nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (qspi->fmode == CCR_FMODE_MM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		return stm32_qspi_tx_mm(qspi, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	else if ((op->data.dir == SPI_MEM_DATA_IN && qspi->dma_chrx) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		 (op->data.dir == SPI_MEM_DATA_OUT && qspi->dma_chtx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		if (!stm32_qspi_tx_dma(qspi, op))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	return stm32_qspi_tx_poll(qspi, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	u32 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 						 !(sr & SR_BUSY), 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 						 STM32_BUSY_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			       const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	u32 cr, sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	if (!op->data.nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		goto wait_nobusy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	reinit_completion(&qspi->data_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	cr = readl_relaxed(qspi->io_base + QSPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (!wait_for_completion_timeout(&qspi->data_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 				msecs_to_jiffies(STM32_COMP_TIMEOUT_MS))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		sr = readl_relaxed(qspi->io_base + QSPI_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		if (sr & SR_TEF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	/* clear flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) wait_nobusy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		err = stm32_qspi_wait_nobusy(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int stm32_qspi_get_mode(struct stm32_qspi *qspi, u8 buswidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	if (buswidth == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		return CCR_BUSWIDTH_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	return buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	u32 ccr, cr, addr_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	int timeout, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		op->dummy.buswidth, op->data.buswidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		op->addr.val, op->data.nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	err = stm32_qspi_wait_nobusy(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	addr_max = op->addr.val + op->data.nbytes + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	if (op->data.dir == SPI_MEM_DATA_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		if (addr_max < qspi->mm_size &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		    op->addr.buswidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			qspi->fmode = CCR_FMODE_MM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 			qspi->fmode = CCR_FMODE_INDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		qspi->fmode = CCR_FMODE_INDW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	cr = readl_relaxed(qspi->io_base + QSPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	cr &= ~CR_PRESC_MASK & ~CR_FSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	cr |= FIELD_PREP(CR_FSEL, flash->cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	writel_relaxed(cr, qspi->io_base + QSPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	if (op->data.nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		writel_relaxed(op->data.nbytes - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 			       qspi->io_base + QSPI_DLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		qspi->fmode = CCR_FMODE_INDW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	ccr = qspi->fmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	ccr |= FIELD_PREP(CCR_IMODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			  stm32_qspi_get_mode(qspi, op->cmd.buswidth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	if (op->addr.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		ccr |= FIELD_PREP(CCR_ADMODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 				  stm32_qspi_get_mode(qspi, op->addr.buswidth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	if (op->dummy.buswidth && op->dummy.nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		ccr |= FIELD_PREP(CCR_DCYC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 				  op->dummy.nbytes * 8 / op->dummy.buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	if (op->data.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		ccr |= FIELD_PREP(CCR_DMODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 				  stm32_qspi_get_mode(qspi, op->data.buswidth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	writel_relaxed(ccr, qspi->io_base + QSPI_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	err = stm32_qspi_tx(qspi, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	 * Abort in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	 * -error case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	 * -read memory map: prefetching must be stopped if we read the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	 *  byte of device (device size - fifo size). like device size is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	 *  knows, the prefetching is always stop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	if (err || qspi->fmode == CCR_FMODE_MM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	/* wait end of tx in indirect mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	err = stm32_qspi_wait_cmd(qspi, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) abort:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	writel_relaxed(cr, qspi->io_base + QSPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	/* wait clear of abort bit by hw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 						    cr, !(cr & CR_ABORT), 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 						    STM32_ABT_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	writel_relaxed(FCR_CTCF, qspi->io_base + QSPI_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	if (err || timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		dev_err(qspi->dev, "%s err:%d abort timeout:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 			__func__, err, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	ret = pm_runtime_get_sync(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		pm_runtime_put_noidle(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	mutex_lock(&qspi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	ret = stm32_qspi_send(mem, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	mutex_unlock(&qspi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	pm_runtime_mark_last_busy(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	pm_runtime_put_autosuspend(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int stm32_qspi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	struct spi_controller *ctrl = spi->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	struct stm32_qspi_flash *flash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	u32 presc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	if (ctrl->busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	if (!spi->max_speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	ret = pm_runtime_get_sync(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		pm_runtime_put_noidle(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	flash = &qspi->flash[spi->chip_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	flash->qspi = qspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	flash->cs = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	flash->presc = presc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	mutex_lock(&qspi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	qspi->cr_reg = 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	/* set dcr fsize to max address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	qspi->dcr_reg = DCR_FSIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	mutex_unlock(&qspi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	pm_runtime_mark_last_busy(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	pm_runtime_put_autosuspend(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int stm32_qspi_dma_setup(struct stm32_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	struct dma_slave_config dma_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	struct device *dev = qspi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	memset(&dma_cfg, 0, sizeof(dma_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	dma_cfg.src_addr = qspi->phys_base + QSPI_DR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	dma_cfg.dst_addr = qspi->phys_base + QSPI_DR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	dma_cfg.src_maxburst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	dma_cfg.dst_maxburst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	qspi->dma_chrx = dma_request_chan(dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	if (IS_ERR(qspi->dma_chrx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 		ret = PTR_ERR(qspi->dma_chrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 		qspi->dma_chrx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 		if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 		if (dmaengine_slave_config(qspi->dma_chrx, &dma_cfg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 			dev_err(dev, "dma rx config failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 			dma_release_channel(qspi->dma_chrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 			qspi->dma_chrx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	qspi->dma_chtx = dma_request_chan(dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	if (IS_ERR(qspi->dma_chtx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 		ret = PTR_ERR(qspi->dma_chtx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 		qspi->dma_chtx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 		if (dmaengine_slave_config(qspi->dma_chtx, &dma_cfg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 			dev_err(dev, "dma tx config failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 			dma_release_channel(qspi->dma_chtx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 			qspi->dma_chtx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	init_completion(&qspi->dma_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 		ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static void stm32_qspi_dma_free(struct stm32_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	if (qspi->dma_chtx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 		dma_release_channel(qspi->dma_chtx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	if (qspi->dma_chrx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 		dma_release_channel(qspi->dma_chrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)  * no special host constraint, so use default spi_mem_default_supports_op
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)  * to check supported mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	.exec_op = stm32_qspi_exec_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int stm32_qspi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	struct spi_controller *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	struct stm32_qspi *qspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 	int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	ctrl = spi_alloc_master(dev, sizeof(*qspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	if (!ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	qspi = spi_controller_get_devdata(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	qspi->ctrl = ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	qspi->io_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	if (IS_ERR(qspi->io_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 		ret = PTR_ERR(qspi->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 		goto err_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	qspi->phys_base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	qspi->mm_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	if (IS_ERR(qspi->mm_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 		ret = PTR_ERR(qspi->mm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 		goto err_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	qspi->mm_size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 		goto err_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 	if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 		ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 		goto err_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 	ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 			       dev_name(dev), qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 		dev_err(dev, "failed to request irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 		goto err_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	init_completion(&qspi->data_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	qspi->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	if (IS_ERR(qspi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 		ret = PTR_ERR(qspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 		goto err_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 	qspi->clk_rate = clk_get_rate(qspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	if (!qspi->clk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 		goto err_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 	ret = clk_prepare_enable(qspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 		dev_err(dev, "can not enable the clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 		goto err_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 	rstc = devm_reset_control_get_exclusive(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 	if (IS_ERR(rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 		ret = PTR_ERR(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 		if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 			goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 		reset_control_assert(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 		udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 		reset_control_deassert(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 	qspi->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 	platform_set_drvdata(pdev, qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 	ret = stm32_qspi_dma_setup(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 		goto err_dma_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 	mutex_init(&qspi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 	ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 		| SPI_TX_DUAL | SPI_TX_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 	ctrl->setup = stm32_qspi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 	ctrl->bus_num = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 	ctrl->mem_ops = &stm32_qspi_mem_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 	ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 	ctrl->dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 	pm_runtime_set_autosuspend_delay(dev, STM32_AUTOSUSPEND_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 	pm_runtime_use_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 	pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 	pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 	pm_runtime_get_noresume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 	ret = devm_spi_register_master(dev, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 		goto err_pm_runtime_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 	pm_runtime_mark_last_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 	pm_runtime_put_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) err_pm_runtime_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 	pm_runtime_get_sync(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 	/* disable qspi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 	writel_relaxed(0, qspi->io_base + QSPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 	mutex_destroy(&qspi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 	pm_runtime_put_noidle(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 	pm_runtime_disable(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 	pm_runtime_set_suspended(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 	pm_runtime_dont_use_autosuspend(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) err_dma_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 	stm32_qspi_dma_free(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 	clk_disable_unprepare(qspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) err_master_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 	spi_master_put(qspi->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static int stm32_qspi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 	struct stm32_qspi *qspi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 	pm_runtime_get_sync(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 	/* disable qspi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 	writel_relaxed(0, qspi->io_base + QSPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 	stm32_qspi_dma_free(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 	mutex_destroy(&qspi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 	pm_runtime_put_noidle(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 	pm_runtime_disable(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 	pm_runtime_set_suspended(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 	pm_runtime_dont_use_autosuspend(qspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 	clk_disable_unprepare(qspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int __maybe_unused stm32_qspi_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 	struct stm32_qspi *qspi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 	clk_disable_unprepare(qspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int __maybe_unused stm32_qspi_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 	struct stm32_qspi *qspi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 	return clk_prepare_enable(qspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static int __maybe_unused stm32_qspi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 	pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 	return pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static int __maybe_unused stm32_qspi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 	struct stm32_qspi *qspi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 	ret = pm_runtime_force_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 	pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 	ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 		pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 	writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 	writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) 	pm_runtime_mark_last_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 	pm_runtime_put_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const struct dev_pm_ops stm32_qspi_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) 	SET_RUNTIME_PM_OPS(stm32_qspi_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 			   stm32_qspi_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) 	SET_SYSTEM_SLEEP_PM_OPS(stm32_qspi_suspend, stm32_qspi_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const struct of_device_id stm32_qspi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) 	{.compatible = "st,stm32f469-qspi"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) MODULE_DEVICE_TABLE(of, stm32_qspi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static struct platform_driver stm32_qspi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) 	.probe	= stm32_qspi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 	.remove	= stm32_qspi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) 		.name = "stm32-qspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) 		.of_match_table = stm32_qspi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 		.pm = &stm32_qspi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) module_platform_driver(stm32_qspi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) MODULE_LICENSE("GPL v2");