^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2017 Spreadtrum Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/hwspinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Registers definitions for ADI controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define REG_ADI_CTRL0 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define REG_ADI_CHN_PRIL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define REG_ADI_CHN_PRIH 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_ADI_INT_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_ADI_INT_RAW 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REG_ADI_INT_MASK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REG_ADI_INT_CLR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_ADI_GSSI_CFG0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REG_ADI_GSSI_CFG1 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_ADI_RD_CMD 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REG_ADI_RD_DATA 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_ADI_ARM_FIFO_STS 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_ADI_STS 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_ADI_EVT_FIFO_STS 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_ADI_ARM_CMD_STS 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_ADI_CHN_EN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_ADI_CHN_ADDR(id) (0x44 + (id - 2) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REG_ADI_CHN_EN1 0x20c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Bits definitions for register REG_ADI_GSSI_CFG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BIT_CLK_ALL_ON BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Bits definitions for register REG_ADI_RD_DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BIT_RD_CMD_BUSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RD_ADDR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RD_VALUE_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RD_ADDR_MASK GENMASK(30, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Bits definitions for register REG_ADI_ARM_FIFO_STS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BIT_FIFO_FULL BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BIT_FIFO_EMPTY BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * The slave devices address offset is always 0x8000 and size is 4K.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ADI_SLAVE_ADDR_SIZE SZ_4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ADI_SLAVE_OFFSET 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Timeout (ms) for the trylock of hardware spinlocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ADI_HWSPINLOCK_TIMEOUT 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * ADI controller has 50 channels including 2 software channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * and 48 hardware channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ADI_HW_CHNS 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ADI_FIFO_DRAIN_TIMEOUT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ADI_READ_TIMEOUT 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define REG_ADDR_LOW_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Registers definitions for PMIC watchdog controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define REG_WDG_LOAD_LOW 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define REG_WDG_LOAD_HIGH 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REG_WDG_CTRL 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define REG_WDG_LOCK 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Bits definitions for register REG_WDG_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BIT_WDG_RUN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BIT_WDG_NEW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BIT_WDG_RST BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Registers definitions for PMIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PMIC_RST_STATUS 0xee8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PMIC_MODULE_EN 0xc08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PMIC_CLK_EN 0xc18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BIT_WDG_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Definition of PMIC reset status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HWRST_STATUS_SECURITY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HWRST_STATUS_RECOVERY 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HWRST_STATUS_NORMAL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HWRST_STATUS_ALARM 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HWRST_STATUS_SLEEP 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HWRST_STATUS_FASTBOOT 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HWRST_STATUS_SPECIAL 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HWRST_STATUS_PANIC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HWRST_STATUS_CFTREBOOT 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define HWRST_STATUS_AUTODLOADER 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HWRST_STATUS_IQMODE 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HWRST_STATUS_SPRDISK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HWRST_STATUS_FACTORYTEST 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HWRST_STATUS_WATCHDOG 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Use default timeout 50 ms that converts to watchdog values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define WDG_LOAD_VAL ((50 * 32768) / 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define WDG_LOAD_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define WDG_UNLOCK_KEY 0xe551
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct sprd_adi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct hwspinlock *hwlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned long slave_vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long slave_pbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct notifier_block restart_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int sprd_adi_check_paddr(struct sprd_adi *sadi, u32 paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (paddr < sadi->slave_pbase || paddr >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) (sadi->slave_pbase + ADI_SLAVE_ADDR_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dev_err(sadi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "slave physical address is incorrect, addr = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static unsigned long sprd_adi_to_vaddr(struct sprd_adi *sadi, u32 paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return (paddr - sadi->slave_pbase + sadi->slave_vbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int sprd_adi_drain_fifo(struct sprd_adi *sadi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (sts & BIT_FIFO_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev_err(sadi->dev, "drain write fifo timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int sprd_adi_fifo_is_full(struct sprd_adi *sadi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int sprd_adi_read(struct sprd_adi *sadi, u32 reg_paddr, u32 *read_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int read_timeout = ADI_READ_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 val, rd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (sadi->hwlock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ADI_HWSPINLOCK_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) &flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_err(sadi->dev, "get the hw lock failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Set the physical register address need to read into RD_CMD register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * then ADI controller will start to transfer automatically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) writel_relaxed(reg_paddr, sadi->base + REG_ADI_RD_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Wait read operation complete, the BIT_RD_CMD_BUSY will be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * simultaneously when writing read command to register, and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * BIT_RD_CMD_BUSY will be cleared after the read operation is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) val = readl_relaxed(sadi->base + REG_ADI_RD_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!(val & BIT_RD_CMD_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) } while (--read_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (read_timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_err(sadi->dev, "ADI read timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * The return value includes data and read register address, from bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * to bit 15 are data, and from bit 16 to bit 30 are read register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * address. Then we can check the returned register address to validate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) rd_addr = (val & RD_ADDR_MASK ) >> RD_ADDR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (rd_addr != (reg_paddr & REG_ADDR_LOW_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dev_err(sadi->dev, "read error, reg addr = 0x%x, val = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) reg_paddr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *read_val = val & RD_VALUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (sadi->hwlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) hwspin_unlock_irqrestore(sadi->hwlock, &flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int sprd_adi_write(struct sprd_adi *sadi, u32 reg_paddr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned long reg = sprd_adi_to_vaddr(sadi, reg_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (sadi->hwlock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ADI_HWSPINLOCK_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) &flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_err(sadi->dev, "get the hw lock failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ret = sprd_adi_drain_fifo(sadi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * we should wait for write fifo is empty before writing data to PMIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!sprd_adi_fifo_is_full(sadi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) writel_relaxed(val, (void __iomem *)reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev_err(sadi->dev, "write fifo is full\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (sadi->hwlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) hwspin_unlock_irqrestore(sadi->hwlock, &flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int sprd_adi_transfer_one(struct spi_controller *ctlr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct spi_device *spi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 phy_reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (t->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) phy_reg = *(u32 *)t->rx_buf + sadi->slave_pbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ret = sprd_adi_check_paddr(sadi, phy_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret = sprd_adi_read(sadi, phy_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) *(u32 *)t->rx_buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } else if (t->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 *p = (u32 *)t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * Get the physical register address need to write and convert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * the physical address to virtual address. Since we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * virtual register address to write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) phy_reg = *p++ + sadi->slave_pbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ret = sprd_adi_check_paddr(sadi, phy_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) val = *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = sprd_adi_write(sadi, phy_reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev_err(sadi->dev, "no buffer for transfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void sprd_adi_set_wdt_rst_mode(struct sprd_adi *sadi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #if IS_ENABLED(CONFIG_SPRD_WATCHDOG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Set default watchdog reboot mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) val |= HWRST_STATUS_WATCHDOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int sprd_adi_restart_handler(struct notifier_block *this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned long mode, void *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct sprd_adi *sadi = container_of(this, struct sprd_adi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) restart_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 val, reboot_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (!cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) reboot_mode = HWRST_STATUS_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) else if (!strncmp(cmd, "recovery", 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) reboot_mode = HWRST_STATUS_RECOVERY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) else if (!strncmp(cmd, "alarm", 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) reboot_mode = HWRST_STATUS_ALARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) else if (!strncmp(cmd, "fastsleep", 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) reboot_mode = HWRST_STATUS_SLEEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) else if (!strncmp(cmd, "bootloader", 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) reboot_mode = HWRST_STATUS_FASTBOOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) else if (!strncmp(cmd, "panic", 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) reboot_mode = HWRST_STATUS_PANIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) else if (!strncmp(cmd, "special", 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) reboot_mode = HWRST_STATUS_SPECIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) else if (!strncmp(cmd, "cftreboot", 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) reboot_mode = HWRST_STATUS_CFTREBOOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) else if (!strncmp(cmd, "autodloader", 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) reboot_mode = HWRST_STATUS_AUTODLOADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) else if (!strncmp(cmd, "iqmode", 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) reboot_mode = HWRST_STATUS_IQMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) else if (!strncmp(cmd, "sprdisk", 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) reboot_mode = HWRST_STATUS_SPRDISK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) else if (!strncmp(cmd, "tospanic", 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) reboot_mode = HWRST_STATUS_SECURITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) else if (!strncmp(cmd, "factorytest", 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) reboot_mode = HWRST_STATUS_FACTORYTEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) reboot_mode = HWRST_STATUS_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Record the reboot mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) val &= ~HWRST_STATUS_WATCHDOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) val |= reboot_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Enable the interface clock of the watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) sprd_adi_read(sadi, sadi->slave_pbase + PMIC_MODULE_EN, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) val |= BIT_WDG_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) sprd_adi_write(sadi, sadi->slave_pbase + PMIC_MODULE_EN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Enable the work clock of the watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) sprd_adi_read(sadi, sadi->slave_pbase + PMIC_CLK_EN, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) val |= BIT_WDG_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) sprd_adi_write(sadi, sadi->slave_pbase + PMIC_CLK_EN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Unlock the watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, WDG_UNLOCK_KEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) val |= BIT_WDG_NEW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Load the watchdog timeout value, 50ms is always enough. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_HIGH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) WDG_LOAD_VAL & WDG_LOAD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Start the watchdog to reset system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) val |= BIT_WDG_RUN | BIT_WDG_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Lock the watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, ~WDG_UNLOCK_KEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) mdelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dev_emerg(sadi->dev, "Unable to restart system\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static void sprd_adi_hw_init(struct sprd_adi *sadi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct device_node *np = sadi->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int i, size, chn_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) const __be32 *list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Set all channels as default priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Set clock auto gate mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) tmp &= ~BIT_CLK_ALL_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Set hardware channels setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) list = of_get_property(np, "sprd,hw-channels", &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (!list || !size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev_info(sadi->dev, "no hw channels setting in node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) chn_cnt = size / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) for (i = 0; i < chn_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 chn_id = be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 chn_config = be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Channel 0 and 1 are software channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (chn_id < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) writel_relaxed(chn_config, sadi->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) REG_ADI_CHN_ADDR(chn_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (chn_id < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) value = readl_relaxed(sadi->base + REG_ADI_CHN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) value |= BIT(chn_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) writel_relaxed(value, sadi->base + REG_ADI_CHN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) } else if (chn_id < ADI_HW_CHNS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) value |= BIT(chn_id - 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int sprd_adi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct sprd_adi *sadi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u32 num_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dev_err(&pdev->dev, "can not find the adi bus node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) pdev->id = of_alias_get_id(np, "spi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) num_chipselect = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ctlr = spi_alloc_master(&pdev->dev, sizeof(struct sprd_adi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!ctlr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dev_set_drvdata(&pdev->dev, ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) sadi = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) sadi->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (IS_ERR(sadi->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ret = PTR_ERR(sadi->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) goto put_ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) sadi->slave_vbase = (unsigned long)sadi->base + ADI_SLAVE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) sadi->ctlr = ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) sadi->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = of_hwspin_lock_get_id(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (ret > 0 || (IS_ENABLED(CONFIG_HWSPINLOCK) && ret == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) sadi->hwlock =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) devm_hwspin_lock_request_specific(&pdev->dev, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (!sadi->hwlock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) goto put_ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) switch (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) case -ENOENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dev_info(&pdev->dev, "no hardware spinlock supplied\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_err_probe(&pdev->dev, ret, "failed to find hwlock id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) goto put_ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) sprd_adi_hw_init(sadi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) sprd_adi_set_wdt_rst_mode(sadi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ctlr->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ctlr->bus_num = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ctlr->num_chipselect = num_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ctlr->flags = SPI_MASTER_HALF_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ctlr->bits_per_word_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ctlr->transfer_one = sprd_adi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ret = devm_spi_register_controller(&pdev->dev, ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dev_err(&pdev->dev, "failed to register SPI controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) goto put_ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) sadi->restart_handler.notifier_call = sprd_adi_restart_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) sadi->restart_handler.priority = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ret = register_restart_handler(&sadi->restart_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dev_err(&pdev->dev, "can not register restart handler\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) goto put_ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) put_ctlr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) spi_controller_put(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int sprd_adi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unregister_restart_handler(&sadi->restart_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static const struct of_device_id sprd_adi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .compatible = "sprd,sc9860-adi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) MODULE_DEVICE_TABLE(of, sprd_adi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static struct platform_driver sprd_adi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .name = "sprd-adi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .of_match_table = sprd_adi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .probe = sprd_adi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .remove = sprd_adi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) module_platform_driver(sprd_adi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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