^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SPI bus driver for CSR SiRFprimaII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spi/spi_bitbang.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/dma-direction.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRIVER_NAME "sirfsoc_spi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* SPI CTRL register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SIRFSOC_SPI_SLV_MODE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SIRFSOC_SPI_CMD_MODE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SIRFSOC_SPI_CS_IO_OUT BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SIRFSOC_SPI_CS_IO_MODE BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SIRFSOC_SPI_CLK_IDLE_STAT BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SIRFSOC_SPI_CS_IDLE_STAT BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SIRFSOC_SPI_TRAN_MSB BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SIRFSOC_SPI_DRV_POS_EDGE BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SIRFSOC_SPI_CS_HOLD_TIME BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SIRFSOC_SPI_CLK_SAMPLE_MODE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SIRFSOC_SPI_TRAN_DAT_FORMAT_8 (0 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SIRFSOC_SPI_TRAN_DAT_FORMAT_12 (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SIRFSOC_SPI_TRAN_DAT_FORMAT_16 (2 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SIRFSOC_SPI_TRAN_DAT_FORMAT_32 (3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SIRFSOC_SPI_CMD_BYTE_NUM(x) ((x & 3) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SIRFSOC_SPI_ENA_AUTO_CLR BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SIRFSOC_SPI_MUL_DAT_MODE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SIRFSOC_SPI_RX_DONE_INT_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SIRFSOC_SPI_TX_DONE_INT_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SIRFSOC_SPI_RX_OFLOW_INT_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SIRFSOC_SPI_TX_UFLOW_INT_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SIRFSOC_SPI_RX_IO_DMA_INT_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SIRFSOC_SPI_TX_IO_DMA_INT_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SIRFSOC_SPI_RXFIFO_FULL_INT_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SIRFSOC_SPI_RXFIFO_THD_INT_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SIRFSOC_SPI_TXFIFO_THD_INT_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SIRFSOC_SPI_FRM_END_INT_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SIRFSOC_SPI_RX_DONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SIRFSOC_SPI_TX_DONE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SIRFSOC_SPI_RX_OFLOW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SIRFSOC_SPI_TX_UFLOW BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SIRFSOC_SPI_RX_IO_DMA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SIRFSOC_SPI_RX_FIFO_FULL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SIRFSOC_SPI_TXFIFO_EMPTY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SIRFSOC_SPI_RXFIFO_THD_REACH BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SIRFSOC_SPI_TXFIFO_THD_REACH BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SIRFSOC_SPI_FRM_END BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* TX RX enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SIRFSOC_SPI_RX_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SIRFSOC_SPI_TX_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SIRFSOC_SPI_CMD_TX_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SIRFSOC_SPI_IO_MODE_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SIRFSOC_SPI_RX_DMA_FLUSH BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* FIFO OPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SIRFSOC_SPI_FIFO_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SIRFSOC_SPI_FIFO_START BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* FIFO CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SIRFSOC_SPI_FIFO_WIDTH_BYTE (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SIRFSOC_SPI_FIFO_WIDTH_WORD (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SIRFSOC_SPI_FIFO_WIDTH_DWORD (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* USP related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SIRFSOC_USP_SYNC_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SIRFSOC_USP_SLV_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SIRFSOC_USP_LSB BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SIRFSOC_USP_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SIRFSOC_USP_RXD_FALLING_EDGE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SIRFSOC_USP_TXD_FALLING_EDGE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SIRFSOC_USP_CS_HIGH_VALID BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SIRFSOC_USP_SCLK_IDLE_STAT BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SIRFSOC_USP_TFS_IO_MODE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SIRFSOC_USP_TFS_IO_INPUT BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SIRFSOC_USP_RXD_DELAY_LEN_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SIRFSOC_USP_TXD_DELAY_LEN_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SIRFSOC_USP_RXD_DELAY_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SIRFSOC_USP_TXD_DELAY_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SIRFSOC_USP_RXD_DELAY_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SIRFSOC_USP_TXD_DELAY_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SIRFSOC_USP_CLK_DIVISOR_OFFSET 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SIRFSOC_USP_CLK_DIVISOR_MASK 0x3FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SIRFSOC_USP_CLK_10_11_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SIRFSOC_USP_CLK_10_11_OFFSET 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SIRFSOC_USP_CLK_12_15_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SIRFSOC_USP_CLK_12_15_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SIRFSOC_USP_TX_DATA_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SIRFSOC_USP_TX_SYNC_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SIRFSOC_USP_TX_FRAME_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SIRFSOC_USP_TX_SHIFTER_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SIRFSOC_USP_TX_DATA_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SIRFSOC_USP_TX_SYNC_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SIRFSOC_USP_TX_FRAME_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SIRFSOC_USP_TX_SHIFTER_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SIRFSOC_USP_RX_DATA_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SIRFSOC_USP_RX_FRAME_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SIRFSOC_USP_RX_SHIFTER_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SIRFSOC_USP_RX_DATA_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SIRFSOC_USP_RX_FRAME_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SIRFSOC_USP_RX_SHIFTER_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SIRFSOC_USP_CS_HIGH_VALUE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SIRFSOC_SPI_FIFO_SC_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SIRFSOC_SPI_FIFO_LC_OFFSET 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SIRFSOC_SPI_FIFO_HC_OFFSET 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SIRFSOC_SPI_FIFO_FULL_MASK(s) (1 << ((s)->fifo_full_offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SIRFSOC_SPI_FIFO_EMPTY_MASK(s) (1 << ((s)->fifo_full_offset + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SIRFSOC_SPI_FIFO_THD_MASK(s) ((s)->fifo_size - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SIRFSOC_SPI_FIFO_THD_OFFSET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(s, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ((val) & (s)->fifo_level_chk_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) enum sirf_spi_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) SIRF_REAL_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) SIRF_USP_SPI_P2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) SIRF_USP_SPI_A7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * due to the limitation of dma controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ALIGNED(x) (!((u32)x & 0x3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SIRFSOC_MAX_CMD_BYTES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SIRFSOC_SPI_DEFAULT_FRQ 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct sirf_spi_register {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*SPI and USP-SPI common*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 tx_rx_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 int_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 int_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 tx_dma_io_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 tx_dma_io_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 txfifo_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 txfifo_level_chk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 txfifo_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 txfifo_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 txfifo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 rx_dma_io_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 rx_dma_io_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 rxfifo_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 rxfifo_level_chk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 rxfifo_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 rxfifo_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 rxfifo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*SPI self*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 spi_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 spi_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 spi_dummy_delay_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*USP-SPI self*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 usp_mode1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 usp_mode2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 usp_tx_frame_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 usp_rx_frame_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 usp_pin_io_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 usp_risc_dsp_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 usp_async_param_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 usp_irda_x_mode_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 usp_sm_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 usp_int_en_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const struct sirf_spi_register real_spi_register = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .tx_rx_en = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .int_en = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .int_st = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .tx_dma_io_ctrl = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .tx_dma_io_len = 0x104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .txfifo_ctrl = 0x108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .txfifo_level_chk = 0x10c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .txfifo_op = 0x110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .txfifo_st = 0x114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .txfifo_data = 0x118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .rx_dma_io_ctrl = 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .rx_dma_io_len = 0x124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .rxfifo_ctrl = 0x128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .rxfifo_level_chk = 0x12c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .rxfifo_op = 0x130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .rxfifo_st = 0x134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .rxfifo_data = 0x138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .spi_ctrl = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .spi_cmd = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .spi_dummy_delay_ctrl = 0x144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const struct sirf_spi_register usp_spi_register = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .tx_rx_en = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .int_en = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .int_st = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .tx_dma_io_ctrl = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .tx_dma_io_len = 0x104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .txfifo_ctrl = 0x108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .txfifo_level_chk = 0x10c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .txfifo_op = 0x110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .txfifo_st = 0x114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .txfifo_data = 0x118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .rx_dma_io_ctrl = 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .rx_dma_io_len = 0x124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .rxfifo_ctrl = 0x128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .rxfifo_level_chk = 0x12c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .rxfifo_op = 0x130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .rxfifo_st = 0x134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .rxfifo_data = 0x138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .usp_mode1 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .usp_mode2 = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .usp_tx_frame_ctrl = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .usp_rx_frame_ctrl = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .usp_pin_io_data = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .usp_risc_dsp_mode = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .usp_async_param_reg = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .usp_irda_x_mode_div = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .usp_sm_cfg = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .usp_int_en_clr = 0x140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct sirfsoc_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct spi_bitbang bitbang;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct completion rx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct completion tx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 ctrl_freq; /* SPI controller clock speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* rx & tx bufs from the spi_transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) const void *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) void *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* place received word into rx buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) void (*rx_word) (struct sirfsoc_spi *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* get word from tx buffer for sending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) void (*tx_word) (struct sirfsoc_spi *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* number of words left to be tranmitted/received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned int left_tx_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned int left_rx_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* rx & tx DMA channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct dma_chan *rx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct dma_chan *tx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dma_addr_t src_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dma_addr_t dst_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int word_width; /* in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * if tx size is not more than 4 and rx size is NULL, use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * command model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) bool tx_by_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) bool hw_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) enum sirf_spi_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) const struct sirf_spi_register *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned int fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* fifo empty offset is (fifo full offset + 1)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned int fifo_full_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* fifo_level_chk_mask is (fifo_size/4 - 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned int fifo_level_chk_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned int dat_max_frm_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct sirf_spi_comp_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) const struct sirf_spi_register *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) enum sirf_spi_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int dat_max_frm_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned int fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) void (*hwinit)(struct sirfsoc_spi *sspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static void sirfsoc_usp_hwinit(struct sirfsoc_spi *sspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* reset USP and let USP can operate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) writel(readl(sspi->base + sspi->regs->usp_mode1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ~SIRFSOC_USP_EN, sspi->base + sspi->regs->usp_mode1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) writel(readl(sspi->base + sspi->regs->usp_mode1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) SIRFSOC_USP_EN, sspi->base + sspi->regs->usp_mode1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u8 *rx = sspi->rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) data = readl(sspi->base + sspi->regs->rxfifo_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) *rx++ = (u8) data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) sspi->rx = rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) sspi->left_rx_word--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) const u8 *tx = sspi->tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) data = *tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) sspi->tx = tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) writel(data, sspi->base + sspi->regs->txfifo_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) sspi->left_tx_word--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u16 *rx = sspi->rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) data = readl(sspi->base + sspi->regs->rxfifo_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *rx++ = (u16) data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) sspi->rx = rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) sspi->left_rx_word--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) const u16 *tx = sspi->tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) data = *tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) sspi->tx = tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) writel(data, sspi->base + sspi->regs->txfifo_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) sspi->left_tx_word--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u32 *rx = sspi->rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) data = readl(sspi->base + sspi->regs->rxfifo_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *rx++ = (u32) data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) sspi->rx = rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) sspi->left_rx_word--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) const u32 *tx = sspi->tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) data = *tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) sspi->tx = tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) writel(data, sspi->base + sspi->regs->txfifo_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) sspi->left_tx_word--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct sirfsoc_spi *sspi = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u32 spi_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) spi_stat = readl(sspi->base + sspi->regs->int_st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (sspi->tx_by_cmd && sspi->type == SIRF_REAL_SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) && (spi_stat & SIRFSOC_SPI_FRM_END)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) complete(&sspi->tx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) writel(0x0, sspi->base + sspi->regs->int_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) writel(readl(sspi->base + sspi->regs->int_st),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) sspi->base + sspi->regs->int_st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Error Conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) spi_stat & SIRFSOC_SPI_TX_UFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) complete(&sspi->tx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) complete(&sspi->rx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) switch (sspi->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case SIRF_REAL_SPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) case SIRF_USP_SPI_P2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) writel(0x0, sspi->base + sspi->regs->int_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case SIRF_USP_SPI_A7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) writel(readl(sspi->base + sspi->regs->int_st),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) sspi->base + sspi->regs->int_st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (spi_stat & SIRFSOC_SPI_TXFIFO_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) complete(&sspi->tx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) while (!(readl(sspi->base + sspi->regs->int_st) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) SIRFSOC_SPI_RX_IO_DMA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) complete(&sspi->rx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) switch (sspi->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case SIRF_REAL_SPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case SIRF_USP_SPI_P2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) writel(0x0, sspi->base + sspi->regs->int_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case SIRF_USP_SPI_A7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) writel(readl(sspi->base + sspi->regs->int_st),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) sspi->base + sspi->regs->int_st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static void spi_sirfsoc_dma_fini_callback(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct completion *dma_complete = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) complete(dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static void spi_sirfsoc_cmd_transfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct sirfsoc_spi *sspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int timeout = t->len * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) sspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) memcpy(&cmd, sspi->tx, t->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) cmd = cpu_to_be32(cmd) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ((SIRFSOC_MAX_CMD_BYTES - t->len) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (sspi->word_width == 2 && t->len == 4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) (!(spi->mode & SPI_LSB_FIRST)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) cmd = ((cmd & 0xffff) << 16) | (cmd >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) writel(cmd, sspi->base + sspi->regs->spi_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) writel(SIRFSOC_SPI_FRM_END_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) sspi->base + sspi->regs->int_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) writel(SIRFSOC_SPI_CMD_TX_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) sspi->base + sspi->regs->tx_rx_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dev_err(&spi->dev, "cmd transfer timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) sspi->left_rx_word -= t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static void spi_sirfsoc_dma_transfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct sirfsoc_spi *sspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct dma_async_tx_descriptor *rx_desc, *tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int timeout = t->len * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) sspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) switch (sspi->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) case SIRF_REAL_SPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) writel(SIRFSOC_SPI_FIFO_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) sspi->base + sspi->regs->rxfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) writel(SIRFSOC_SPI_FIFO_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) sspi->base + sspi->regs->txfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) writel(0, sspi->base + sspi->regs->int_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) case SIRF_USP_SPI_P2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) writel(0x0, sspi->base + sspi->regs->rxfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) writel(0x0, sspi->base + sspi->regs->txfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) writel(0, sspi->base + sspi->regs->int_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) case SIRF_USP_SPI_A7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) writel(0x0, sspi->base + sspi->regs->rxfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) writel(0x0, sspi->base + sspi->regs->txfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) writel(readl(sspi->base + sspi->regs->int_st),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) sspi->base + sspi->regs->int_st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (sspi->left_tx_word < sspi->dat_max_frm_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) switch (sspi->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) case SIRF_REAL_SPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) writel(readl(sspi->base + sspi->regs->spi_ctrl) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) SIRFSOC_SPI_ENA_AUTO_CLR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) SIRFSOC_SPI_MUL_DAT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) sspi->base + sspi->regs->spi_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) writel(sspi->left_tx_word - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) sspi->base + sspi->regs->tx_dma_io_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) writel(sspi->left_tx_word - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) sspi->base + sspi->regs->rx_dma_io_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case SIRF_USP_SPI_P2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case SIRF_USP_SPI_A7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /*USP simulate SPI, tx/rx_dma_io_len indicates bytes*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) writel(sspi->left_tx_word * sspi->word_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) sspi->base + sspi->regs->tx_dma_io_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) writel(sspi->left_tx_word * sspi->word_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) sspi->base + sspi->regs->rx_dma_io_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (sspi->type == SIRF_REAL_SPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) writel(readl(sspi->base + sspi->regs->spi_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) sspi->base + sspi->regs->spi_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) writel(0, sspi->base + sspi->regs->tx_dma_io_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) writel(0, sspi->base + sspi->regs->rx_dma_io_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) (t->tx_buf != t->rx_buf) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) DMA_FROM_DEVICE : DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) rx_desc = dmaengine_prep_slave_single(sspi->rx_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) sspi->dst_start, t->len, DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) rx_desc->callback = spi_sirfsoc_dma_fini_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) rx_desc->callback_param = &sspi->rx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) (t->tx_buf != t->rx_buf) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) DMA_TO_DEVICE : DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) tx_desc = dmaengine_prep_slave_single(sspi->tx_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) sspi->src_start, t->len, DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) tx_desc->callback = spi_sirfsoc_dma_fini_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) tx_desc->callback_param = &sspi->tx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dmaengine_submit(tx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dmaengine_submit(rx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dma_async_issue_pending(sspi->tx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dma_async_issue_pending(sspi->rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) sspi->base + sspi->regs->tx_rx_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (sspi->type == SIRF_USP_SPI_P2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) sspi->type == SIRF_USP_SPI_A7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) writel(SIRFSOC_SPI_FIFO_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) sspi->base + sspi->regs->rxfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) writel(SIRFSOC_SPI_FIFO_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) sspi->base + sspi->regs->txfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dev_err(&spi->dev, "transfer timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) dmaengine_terminate_all(sspi->rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) sspi->left_rx_word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * we only wait tx-done event if transferring by DMA. for PIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * we get rx data by writing tx data, so if rx is done, tx has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * done earlier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_err(&spi->dev, "transfer timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (sspi->type == SIRF_USP_SPI_P2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) sspi->type == SIRF_USP_SPI_A7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) writel(0, sspi->base + sspi->regs->tx_rx_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dmaengine_terminate_all(sspi->tx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* TX, RX FIFO stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) writel(0, sspi->base + sspi->regs->rxfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) writel(0, sspi->base + sspi->regs->txfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (sspi->left_tx_word >= sspi->dat_max_frm_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) writel(0, sspi->base + sspi->regs->tx_rx_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (sspi->type == SIRF_USP_SPI_P2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) sspi->type == SIRF_USP_SPI_A7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) writel(0, sspi->base + sspi->regs->tx_rx_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static void spi_sirfsoc_pio_transfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct sirfsoc_spi *sspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int timeout = t->len * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned int data_units;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) sspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) writel(SIRFSOC_SPI_FIFO_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) sspi->base + sspi->regs->rxfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) writel(SIRFSOC_SPI_FIFO_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) sspi->base + sspi->regs->txfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) switch (sspi->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) case SIRF_USP_SPI_P2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) writel(0x0, sspi->base + sspi->regs->rxfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) writel(0x0, sspi->base + sspi->regs->txfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) writel(0, sspi->base + sspi->regs->int_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) writel(readl(sspi->base + sspi->regs->int_st),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) sspi->base + sspi->regs->int_st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) writel(min((sspi->left_tx_word * sspi->word_width),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) sspi->fifo_size),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) sspi->base + sspi->regs->tx_dma_io_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) writel(min((sspi->left_rx_word * sspi->word_width),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) sspi->fifo_size),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) sspi->base + sspi->regs->rx_dma_io_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) case SIRF_USP_SPI_A7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) writel(0x0, sspi->base + sspi->regs->rxfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) writel(0x0, sspi->base + sspi->regs->txfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) writel(readl(sspi->base + sspi->regs->int_st),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) sspi->base + sspi->regs->int_st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) writel(min((sspi->left_tx_word * sspi->word_width),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) sspi->fifo_size),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) sspi->base + sspi->regs->tx_dma_io_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) writel(min((sspi->left_rx_word * sspi->word_width),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) sspi->fifo_size),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) sspi->base + sspi->regs->rx_dma_io_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) case SIRF_REAL_SPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) writel(SIRFSOC_SPI_FIFO_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) sspi->base + sspi->regs->rxfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) writel(SIRFSOC_SPI_FIFO_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) sspi->base + sspi->regs->txfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) writel(0, sspi->base + sspi->regs->int_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) writel(readl(sspi->base + sspi->regs->int_st),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) sspi->base + sspi->regs->int_st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) writel(readl(sspi->base + sspi->regs->spi_ctrl) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) SIRFSOC_SPI_MUL_DAT_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) SIRFSOC_SPI_ENA_AUTO_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) sspi->base + sspi->regs->spi_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) data_units = sspi->fifo_size / sspi->word_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) writel(min(sspi->left_tx_word, data_units) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) sspi->base + sspi->regs->tx_dma_io_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) writel(min(sspi->left_rx_word, data_units) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) sspi->base + sspi->regs->rx_dma_io_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) while (!((readl(sspi->base + sspi->regs->txfifo_st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) & SIRFSOC_SPI_FIFO_FULL_MASK(sspi))) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) sspi->left_tx_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) sspi->tx_word(sspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) writel(SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) SIRFSOC_SPI_TX_UFLOW_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) SIRFSOC_SPI_RX_OFLOW_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) SIRFSOC_SPI_RX_IO_DMA_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) sspi->base + sspi->regs->int_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) sspi->base + sspi->regs->tx_rx_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (sspi->type == SIRF_USP_SPI_P2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) sspi->type == SIRF_USP_SPI_A7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) writel(SIRFSOC_SPI_FIFO_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) sspi->base + sspi->regs->rxfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) writel(SIRFSOC_SPI_FIFO_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) sspi->base + sspi->regs->txfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (!wait_for_completion_timeout(&sspi->tx_done, timeout) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) !wait_for_completion_timeout(&sspi->rx_done, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_err(&spi->dev, "transfer timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (sspi->type == SIRF_USP_SPI_P2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) sspi->type == SIRF_USP_SPI_A7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) writel(0, sspi->base + sspi->regs->tx_rx_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) while (!((readl(sspi->base + sspi->regs->rxfifo_st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) & SIRFSOC_SPI_FIFO_EMPTY_MASK(sspi))) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) sspi->left_rx_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) sspi->rx_word(sspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (sspi->type == SIRF_USP_SPI_P2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) sspi->type == SIRF_USP_SPI_A7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) writel(0, sspi->base + sspi->regs->tx_rx_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) writel(0, sspi->base + sspi->regs->rxfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) writel(0, sspi->base + sspi->regs->txfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) } while (sspi->left_tx_word != 0 || sspi->left_rx_word != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct sirfsoc_spi *sspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) sspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) sspi->tx = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) sspi->rx = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) reinit_completion(&sspi->rx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) reinit_completion(&sspi->tx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * in the transfer, if transfer data using command register with rx_buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * null, just fill command data into command register and wait for its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (sspi->type == SIRF_REAL_SPI && sspi->tx_by_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) spi_sirfsoc_cmd_transfer(spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) else if (IS_DMA_VALID(t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) spi_sirfsoc_dma_transfer(spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) spi_sirfsoc_pio_transfer(spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return t->len - sspi->left_rx_word * sspi->word_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (sspi->hw_cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) switch (sspi->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) case SIRF_REAL_SPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) regval = readl(sspi->base + sspi->regs->spi_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) switch (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) case BITBANG_CS_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (spi->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) regval |= SIRFSOC_SPI_CS_IO_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) regval &= ~SIRFSOC_SPI_CS_IO_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) case BITBANG_CS_INACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (spi->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) regval &= ~SIRFSOC_SPI_CS_IO_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) regval |= SIRFSOC_SPI_CS_IO_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) writel(regval, sspi->base + sspi->regs->spi_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) case SIRF_USP_SPI_P2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) case SIRF_USP_SPI_A7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) regval = readl(sspi->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) sspi->regs->usp_pin_io_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) switch (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) case BITBANG_CS_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (spi->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) regval |= SIRFSOC_USP_CS_HIGH_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) regval &= ~(SIRFSOC_USP_CS_HIGH_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) case BITBANG_CS_INACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (spi->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) regval &= ~(SIRFSOC_USP_CS_HIGH_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) regval |= SIRFSOC_USP_CS_HIGH_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) writel(regval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) sspi->base + sspi->regs->usp_pin_io_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) switch (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) case BITBANG_CS_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) gpio_direction_output(spi->cs_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) spi->mode & SPI_CS_HIGH ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) case BITBANG_CS_INACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) gpio_direction_output(spi->cs_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) spi->mode & SPI_CS_HIGH ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int spi_sirfsoc_config_mode(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct sirfsoc_spi *sspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u32 regval, usp_mode1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) sspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) regval = readl(sspi->base + sspi->regs->spi_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) usp_mode1 = readl(sspi->base + sspi->regs->usp_mode1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (!(spi->mode & SPI_CS_HIGH)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) regval |= SIRFSOC_SPI_CS_IDLE_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) usp_mode1 &= ~SIRFSOC_USP_CS_HIGH_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) regval &= ~SIRFSOC_SPI_CS_IDLE_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) usp_mode1 |= SIRFSOC_USP_CS_HIGH_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (!(spi->mode & SPI_LSB_FIRST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) regval |= SIRFSOC_SPI_TRAN_MSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) usp_mode1 &= ~SIRFSOC_USP_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) regval &= ~SIRFSOC_SPI_TRAN_MSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) usp_mode1 |= SIRFSOC_USP_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (spi->mode & SPI_CPOL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) regval |= SIRFSOC_SPI_CLK_IDLE_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) usp_mode1 |= SIRFSOC_USP_SCLK_IDLE_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) regval &= ~SIRFSOC_SPI_CLK_IDLE_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) usp_mode1 &= ~SIRFSOC_USP_SCLK_IDLE_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * Data should be driven at least 1/2 cycle before the fetch edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * to make sure that data gets stable at the fetch edge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) regval &= ~SIRFSOC_SPI_DRV_POS_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) usp_mode1 |= (SIRFSOC_USP_TXD_FALLING_EDGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) SIRFSOC_USP_RXD_FALLING_EDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) regval |= SIRFSOC_SPI_DRV_POS_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) usp_mode1 &= ~(SIRFSOC_USP_RXD_FALLING_EDGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) SIRFSOC_USP_TXD_FALLING_EDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) writel((SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size - 2) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) SIRFSOC_SPI_FIFO_SC_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size / 2) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) SIRFSOC_SPI_FIFO_LC_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, 2) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) SIRFSOC_SPI_FIFO_HC_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) sspi->base + sspi->regs->txfifo_level_chk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) writel((SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, 2) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) SIRFSOC_SPI_FIFO_SC_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size / 2) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) SIRFSOC_SPI_FIFO_LC_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size - 2) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) SIRFSOC_SPI_FIFO_HC_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) sspi->base + sspi->regs->rxfifo_level_chk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * it should never set to hardware cs mode because in hardware cs mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * cs signal can't controlled by driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) switch (sspi->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) case SIRF_REAL_SPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) regval |= SIRFSOC_SPI_CS_IO_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) writel(regval, sspi->base + sspi->regs->spi_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) case SIRF_USP_SPI_P2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) case SIRF_USP_SPI_A7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) usp_mode1 |= SIRFSOC_USP_SYNC_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) usp_mode1 |= SIRFSOC_USP_TFS_IO_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) usp_mode1 &= ~SIRFSOC_USP_TFS_IO_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) writel(usp_mode1, sspi->base + sspi->regs->usp_mode1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct sirfsoc_spi *sspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) u8 bits_per_word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int hz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) u32 regval, txfifo_ctrl, rxfifo_ctrl, tx_frm_ctl, rx_frm_ctl, usp_mode2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) sspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) usp_mode2 = regval = (sspi->ctrl_freq / (2 * hz)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (regval > 0xFFFF || regval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) dev_err(&spi->dev, "Speed %d not supported\n", hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) switch (bits_per_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) sspi->rx_word = spi_sirfsoc_rx_word_u8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) sspi->tx_word = spi_sirfsoc_tx_word_u8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) regval |= (bits_per_word == 12) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) SIRFSOC_SPI_TRAN_DAT_FORMAT_12 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) SIRFSOC_SPI_TRAN_DAT_FORMAT_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) sspi->rx_word = spi_sirfsoc_rx_word_u16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) sspi->tx_word = spi_sirfsoc_tx_word_u16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) sspi->rx_word = spi_sirfsoc_rx_word_u32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) sspi->tx_word = spi_sirfsoc_tx_word_u32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dev_err(&spi->dev, "bpw %d not supported\n", bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) sspi->word_width = DIV_ROUND_UP(bits_per_word, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) txfifo_ctrl = (((sspi->fifo_size / 2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) SIRFSOC_SPI_FIFO_THD_MASK(sspi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) << SIRFSOC_SPI_FIFO_THD_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) (sspi->word_width >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) rxfifo_ctrl = (((sspi->fifo_size / 2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) SIRFSOC_SPI_FIFO_THD_MASK(sspi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) << SIRFSOC_SPI_FIFO_THD_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) (sspi->word_width >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) writel(txfifo_ctrl, sspi->base + sspi->regs->txfifo_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) writel(rxfifo_ctrl, sspi->base + sspi->regs->rxfifo_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (sspi->type == SIRF_USP_SPI_P2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) sspi->type == SIRF_USP_SPI_A7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) tx_frm_ctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) tx_frm_ctl |= ((bits_per_word - 1) & SIRFSOC_USP_TX_DATA_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) << SIRFSOC_USP_TX_DATA_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) tx_frm_ctl |= ((bits_per_word + 1 + SIRFSOC_USP_TXD_DELAY_LEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) - 1) & SIRFSOC_USP_TX_SYNC_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) SIRFSOC_USP_TX_SYNC_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) tx_frm_ctl |= ((bits_per_word + 1 + SIRFSOC_USP_TXD_DELAY_LEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) + 2 - 1) & SIRFSOC_USP_TX_FRAME_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) SIRFSOC_USP_TX_FRAME_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) tx_frm_ctl |= ((bits_per_word - 1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) SIRFSOC_USP_TX_SHIFTER_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) SIRFSOC_USP_TX_SHIFTER_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) rx_frm_ctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) rx_frm_ctl |= ((bits_per_word - 1) & SIRFSOC_USP_RX_DATA_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) << SIRFSOC_USP_RX_DATA_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) rx_frm_ctl |= ((bits_per_word + 1 + SIRFSOC_USP_RXD_DELAY_LEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) + 2 - 1) & SIRFSOC_USP_RX_FRAME_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) SIRFSOC_USP_RX_FRAME_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) rx_frm_ctl |= ((bits_per_word - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) & SIRFSOC_USP_RX_SHIFTER_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) SIRFSOC_USP_RX_SHIFTER_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) writel(tx_frm_ctl | (((usp_mode2 >> 10) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) SIRFSOC_USP_CLK_10_11_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) SIRFSOC_USP_CLK_10_11_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) sspi->base + sspi->regs->usp_tx_frame_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) writel(rx_frm_ctl | (((usp_mode2 >> 12) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) SIRFSOC_USP_CLK_12_15_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) SIRFSOC_USP_CLK_12_15_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) sspi->base + sspi->regs->usp_rx_frame_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) writel(readl(sspi->base + sspi->regs->usp_mode2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ((usp_mode2 & SIRFSOC_USP_CLK_DIVISOR_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) SIRFSOC_USP_CLK_DIVISOR_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) (SIRFSOC_USP_RXD_DELAY_LEN <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) SIRFSOC_USP_RXD_DELAY_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) (SIRFSOC_USP_TXD_DELAY_LEN <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) SIRFSOC_USP_TXD_DELAY_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) sspi->base + sspi->regs->usp_mode2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (sspi->type == SIRF_REAL_SPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) writel(regval, sspi->base + sspi->regs->spi_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) spi_sirfsoc_config_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (sspi->type == SIRF_REAL_SPI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (t && t->tx_buf && !t->rx_buf &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) (t->len <= SIRFSOC_MAX_CMD_BYTES)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) sspi->tx_by_cmd = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) writel(readl(sspi->base + sspi->regs->spi_ctrl) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) (SIRFSOC_SPI_CMD_BYTE_NUM((t->len - 1)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) SIRFSOC_SPI_CMD_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) sspi->base + sspi->regs->spi_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) sspi->tx_by_cmd = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) writel(readl(sspi->base + sspi->regs->spi_ctrl) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ~SIRFSOC_SPI_CMD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) sspi->base + sspi->regs->spi_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (IS_DMA_VALID(t)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /* Enable DMA mode for RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) writel(0, sspi->base + sspi->regs->tx_dma_io_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) writel(SIRFSOC_SPI_RX_DMA_FLUSH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) sspi->base + sspi->regs->rx_dma_io_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* Enable IO mode for RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) writel(SIRFSOC_SPI_IO_MODE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) sspi->base + sspi->regs->tx_dma_io_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) writel(SIRFSOC_SPI_IO_MODE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) sspi->base + sspi->regs->rx_dma_io_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static int spi_sirfsoc_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct sirfsoc_spi *sspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) sspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (spi->cs_gpio == -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) sspi->hw_cs = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) sspi->hw_cs = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (!spi_get_ctldata(spi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) void *cs = kmalloc(sizeof(int), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (!cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ret = gpio_is_valid(spi->cs_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) dev_err(&spi->dev, "no valid gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) ret = gpio_request(spi->cs_gpio, DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) dev_err(&spi->dev, "failed to request gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) spi_set_ctldata(spi, cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) spi_sirfsoc_config_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) spi_sirfsoc_chipselect(spi, BITBANG_CS_INACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static void spi_sirfsoc_cleanup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (spi_get_ctldata(spi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) gpio_free(spi->cs_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) kfree(spi_get_ctldata(spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static const struct sirf_spi_comp_data sirf_real_spi = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .regs = &real_spi_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .type = SIRF_REAL_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .dat_max_frm_len = 64 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .fifo_size = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static const struct sirf_spi_comp_data sirf_usp_spi_p2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .regs = &usp_spi_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .type = SIRF_USP_SPI_P2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .dat_max_frm_len = 1024 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .fifo_size = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .hwinit = sirfsoc_usp_hwinit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static const struct sirf_spi_comp_data sirf_usp_spi_a7 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .regs = &usp_spi_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .type = SIRF_USP_SPI_A7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .dat_max_frm_len = 1024 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .fifo_size = 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .hwinit = sirfsoc_usp_hwinit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static const struct of_device_id spi_sirfsoc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) { .compatible = "sirf,prima2-spi", .data = &sirf_real_spi},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) { .compatible = "sirf,prima2-usp-spi", .data = &sirf_usp_spi_p2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) { .compatible = "sirf,atlas7-usp-spi", .data = &sirf_usp_spi_a7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static int spi_sirfsoc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct sirfsoc_spi *sspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) const struct sirf_spi_comp_data *spi_comp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) ret = device_reset(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) dev_err(&pdev->dev, "SPI reset failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) master = spi_alloc_master(&pdev->dev, sizeof(*sspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) dev_err(&pdev->dev, "Unable to allocate SPI master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) match = of_match_node(spi_sirfsoc_of_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) sspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) sspi->fifo_full_offset = ilog2(sspi->fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) spi_comp_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) sspi->regs = spi_comp_data->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) sspi->type = spi_comp_data->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) sspi->fifo_level_chk_mask = (sspi->fifo_size / 4) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) sspi->dat_max_frm_len = spi_comp_data->dat_max_frm_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) sspi->fifo_size = spi_comp_data->fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) sspi->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (IS_ERR(sspi->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ret = PTR_ERR(sspi->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) DRIVER_NAME, sspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) sspi->bitbang.master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) sspi->bitbang.master->setup = spi_sirfsoc_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) sspi->bitbang.master->cleanup = spi_sirfsoc_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) master->bus_num = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) master->max_speed_hz = SIRFSOC_SPI_DEFAULT_FRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* request DMA channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) sspi->rx_chan = dma_request_chan(&pdev->dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (IS_ERR(sspi->rx_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) dev_err(&pdev->dev, "can not allocate rx dma channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) ret = PTR_ERR(sspi->rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) sspi->tx_chan = dma_request_chan(&pdev->dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (IS_ERR(sspi->tx_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) dev_err(&pdev->dev, "can not allocate tx dma channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) ret = PTR_ERR(sspi->tx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) goto free_rx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) sspi->clk = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (IS_ERR(sspi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) ret = PTR_ERR(sspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) goto free_tx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) clk_prepare_enable(sspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (spi_comp_data->hwinit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) spi_comp_data->hwinit(sspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) sspi->ctrl_freq = clk_get_rate(sspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) init_completion(&sspi->rx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) init_completion(&sspi->tx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) ret = spi_bitbang_start(&sspi->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) goto free_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) dev_info(&pdev->dev, "registered, bus number = %d\n", master->bus_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) free_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) clk_disable_unprepare(sspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) clk_put(sspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) free_tx_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) dma_release_channel(sspi->tx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) free_rx_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) dma_release_channel(sspi->rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) free_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static int spi_sirfsoc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct sirfsoc_spi *sspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) sspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) spi_bitbang_stop(&sspi->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) clk_disable_unprepare(sspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) clk_put(sspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) dma_release_channel(sspi->rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) dma_release_channel(sspi->tx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static int spi_sirfsoc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ret = spi_master_suspend(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) clk_disable(sspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static int spi_sirfsoc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) clk_enable(sspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->rxfifo_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static SIMPLE_DEV_PM_OPS(spi_sirfsoc_pm_ops, spi_sirfsoc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) spi_sirfsoc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static struct platform_driver spi_sirfsoc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .pm = &spi_sirfsoc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .of_match_table = spi_sirfsoc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .probe = spi_sirfsoc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .remove = spi_sirfsoc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) module_platform_driver(spi_sirfsoc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) MODULE_DESCRIPTION("SiRF SoC SPI master driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) MODULE_AUTHOR("Barry Song <Baohua.Song@csr.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) MODULE_AUTHOR("Qipan Li <Qipan.Li@csr.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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