^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright 2018 SiFive, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // SiFive SPI controller driver (master mode only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Author: SiFive, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // sifive@sifive.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SIFIVE_SPI_DRIVER_NAME "sifive_spi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SIFIVE_SPI_MAX_CS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SIFIVE_SPI_DEFAULT_DEPTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SIFIVE_SPI_DEFAULT_MAX_BITS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* sckdiv bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* sckmode bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SIFIVE_SPI_SCKMODE_PHA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SIFIVE_SPI_SCKMODE_POL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SIFIVE_SPI_SCKMODE_POL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* csmode bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SIFIVE_SPI_CSMODE_MODE_AUTO 0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SIFIVE_SPI_CSMODE_MODE_HOLD 2U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SIFIVE_SPI_CSMODE_MODE_OFF 3U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* delay0 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* delay1 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* fmt bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SIFIVE_SPI_FMT_PROTO_SINGLE 0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SIFIVE_SPI_FMT_PROTO_DUAL 1U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SIFIVE_SPI_FMT_PROTO_QUAD 2U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SIFIVE_SPI_FMT_PROTO_MASK 3U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SIFIVE_SPI_FMT_ENDIAN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SIFIVE_SPI_FMT_DIR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* txdata bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SIFIVE_SPI_TXDATA_FULL BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* rxdata bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SIFIVE_SPI_RXDATA_EMPTY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* ie and ip bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SIFIVE_SPI_IP_TXWM BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SIFIVE_SPI_IP_RXWM BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct sifive_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void __iomem *regs; /* virt. address of control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct clk *clk; /* bus clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int fifo_depth; /* fifo depth in words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 cs_inactive; /* level of the CS pins when inactive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct completion done; /* wake-up from interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void sifive_spi_write(struct sifive_spi *spi, int offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) iowrite32(value, spi->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static u32 sifive_spi_read(struct sifive_spi *spi, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return ioread32(spi->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void sifive_spi_init(struct sifive_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Watermark interrupts are disabled by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Default watermark FIFO threshold values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) sifive_spi_write(spi, SIFIVE_SPI_REG_TXMARK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Set CS/SCK Delays and Inactive Time to defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SIFIVE_SPI_DELAY0_CSSCK(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SIFIVE_SPI_DELAY0_SCKCS(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SIFIVE_SPI_DELAY1_INTERCS(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) SIFIVE_SPI_DELAY1_INTERXFR(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Exit specialized memory-mapped SPI flash mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) sifive_spi_write(spi, SIFIVE_SPI_REG_FCTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) sifive_spi_prepare_message(struct spi_master *master, struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct sifive_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct spi_device *device = msg->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Update the chip select polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (device->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) spi->cs_inactive &= ~BIT(device->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) spi->cs_inactive |= BIT(device->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Select the correct device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, device->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Set clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) sifive_spi_write(spi, SIFIVE_SPI_REG_SCKMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) device->mode & SIFIVE_SPI_SCKMODE_MODE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void sifive_spi_set_cs(struct spi_device *device, bool is_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct sifive_spi *spi = spi_master_get_devdata(device->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Reverse polarity is handled by SCMR/CPOL. Not inverted CS. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (device->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) is_high = !is_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE, is_high ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) SIFIVE_SPI_CSMODE_MODE_AUTO :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SIFIVE_SPI_CSMODE_MODE_HOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) sifive_spi_prep_transfer(struct sifive_spi *spi, struct spi_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Calculate and program the clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) cr = DIV_ROUND_UP(clk_get_rate(spi->clk) >> 1, t->speed_hz) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) cr &= SIFIVE_SPI_SCKDIV_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) sifive_spi_write(spi, SIFIVE_SPI_REG_SCKDIV, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) mode = max_t(unsigned int, t->rx_nbits, t->tx_nbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Set frame format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) cr = SIFIVE_SPI_FMT_LEN(t->bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case SPI_NBITS_QUAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case SPI_NBITS_DUAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (device->mode & SPI_LSB_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) cr |= SIFIVE_SPI_FMT_ENDIAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!t->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cr |= SIFIVE_SPI_FMT_DIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) sifive_spi_write(spi, SIFIVE_SPI_REG_FMT, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* We will want to poll if the time we need to wait is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * less than the context switching time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Let's call that threshold 5us. The operation will take:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * (8/mode) * fifo_depth / hz <= 5 * 10^-6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * 1600000 * fifo_depth <= hz * mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 1600000 * spi->fifo_depth <= t->speed_hz * mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static irqreturn_t sifive_spi_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct sifive_spi *spi = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 ip = sifive_spi_read(spi, SIFIVE_SPI_REG_IP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (ip & (SIFIVE_SPI_IP_TXWM | SIFIVE_SPI_IP_RXWM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Disable interrupts until next transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) complete(&spi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void sifive_spi_wait(struct sifive_spi *spi, u32 bit, int poll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) cr = sifive_spi_read(spi, SIFIVE_SPI_REG_IP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) } while (!(cr & bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) reinit_completion(&spi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) sifive_spi_write(spi, SIFIVE_SPI_REG_IE, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) wait_for_completion(&spi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) WARN_ON_ONCE((sifive_spi_read(spi, SIFIVE_SPI_REG_TXDATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) & SIFIVE_SPI_TXDATA_FULL) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) sifive_spi_write(spi, SIFIVE_SPI_REG_TXDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 data = sifive_spi_read(spi, SIFIVE_SPI_REG_RXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) WARN_ON_ONCE((data & SIFIVE_SPI_RXDATA_EMPTY) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) *rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) sifive_spi_transfer_one(struct spi_master *master, struct spi_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct sifive_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int poll = sifive_spi_prep_transfer(spi, device, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) const u8 *tx_ptr = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u8 *rx_ptr = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int remaining_words = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) while (remaining_words) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int n_words = min(remaining_words, spi->fifo_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Enqueue n_words for transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) for (i = 0; i < n_words; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) sifive_spi_tx(spi, tx_ptr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (rx_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Wait for transmission + reception to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) n_words - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM, poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Read out all the data from the RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) for (i = 0; i < n_words; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) sifive_spi_rx(spi, rx_ptr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Wait for transmission to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM, poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) remaining_words -= n_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int sifive_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct sifive_spi *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int ret, irq, num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 cs_bits, max_bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) master = spi_alloc_master(&pdev->dev, sizeof(struct sifive_spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev_err(&pdev->dev, "out of memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) init_completion(&spi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) spi->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (IS_ERR(spi->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = PTR_ERR(spi->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) goto put_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) spi->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (IS_ERR(spi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_err(&pdev->dev, "Unable to find bus clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = PTR_ERR(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) goto put_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) goto put_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Optional parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) of_property_read_u32(pdev->dev.of_node, "sifive,fifo-depth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) &spi->fifo_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) spi->fifo_depth = SIFIVE_SPI_DEFAULT_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) of_property_read_u32(pdev->dev.of_node, "sifive,max-bits-per-word",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) &max_bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (!ret && max_bits_per_word < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev_err(&pdev->dev, "Only 8bit SPI words supported by the driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) goto put_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Spin up the bus clock before hitting registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = clk_prepare_enable(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dev_err(&pdev->dev, "Unable to enable bus clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) goto put_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* probe the number of CS lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) spi->cs_inactive = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, 0xffffffffU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) cs_bits = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (!cs_bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_err(&pdev->dev, "Could not auto probe CS lines\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) num_cs = ilog2(cs_bits) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (num_cs > SIFIVE_SPI_MAX_CS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev_err(&pdev->dev, "Invalid number of spi slaves\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Define our master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) master->bus_num = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) master->num_chipselect = num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) master->mode_bits = SPI_CPHA | SPI_CPOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) | SPI_CS_HIGH | SPI_LSB_FIRST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) | SPI_TX_DUAL | SPI_TX_QUAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) | SPI_RX_DUAL | SPI_RX_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* TODO: add driver support for bits_per_word < 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * we need to "left-align" the bits (unless SPI_LSB_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) master->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) master->flags = SPI_CONTROLLER_MUST_TX | SPI_MASTER_GPIO_SS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) master->prepare_message = sifive_spi_prepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) master->set_cs = sifive_spi_set_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) master->transfer_one = sifive_spi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) pdev->dev.dma_mask = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Configure the SPI master hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) sifive_spi_init(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Register for SPI Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = devm_request_irq(&pdev->dev, irq, sifive_spi_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_name(&pdev->dev), spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_err(&pdev->dev, "Unable to bind to interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_info(&pdev->dev, "mapped; irq=%d, cs=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) irq, master->num_chipselect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = devm_spi_register_master(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dev_err(&pdev->dev, "spi_register_master failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) clk_disable_unprepare(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) put_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int sifive_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct sifive_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* Disable all the interrupts just in case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) clk_disable_unprepare(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static const struct of_device_id sifive_spi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { .compatible = "sifive,spi0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) MODULE_DEVICE_TABLE(of, sifive_spi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static struct platform_driver sifive_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .probe = sifive_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .remove = sifive_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .name = SIFIVE_SPI_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .of_match_table = sifive_spi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) module_platform_driver(sifive_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MODULE_AUTHOR("SiFive, Inc. <sifive@sifive.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MODULE_DESCRIPTION("SiFive SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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