Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * SH SPI bus driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2011  Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Based on pxa2xx_spi.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SPI_SH_TBR		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SPI_SH_RBR		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SPI_SH_CR1		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SPI_SH_CR2		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SPI_SH_CR3		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SPI_SH_CR4		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SPI_SH_CR5		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* CR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SPI_SH_TBE		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SPI_SH_TBF		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SPI_SH_RBE		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SPI_SH_RBF		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SPI_SH_PFONRD		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SPI_SH_SSDB		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SPI_SH_SSD		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SPI_SH_SSA		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* CR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SPI_SH_RSTF		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SPI_SH_LOOPBK		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SPI_SH_CPOL		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SPI_SH_CPHA		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SPI_SH_L1M0		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /* CR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SPI_SH_MAX_BYTE		0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /* CR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SPI_SH_TBEI		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SPI_SH_TBFI		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SPI_SH_RBEI		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SPI_SH_RBFI		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SPI_SH_WPABRT		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SPI_SH_SSS		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* CR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SPI_SH_P1L0		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SPI_SH_PP1L0		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SPI_SH_MUXI		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SPI_SH_MUXIRQ		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define SPI_SH_FIFO_SIZE	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define SPI_SH_SEND_TIMEOUT	(3 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define SPI_SH_RECEIVE_TIMEOUT	(HZ >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) struct spi_sh_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct work_struct ws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	unsigned long cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	wait_queue_head_t wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static void spi_sh_write(struct spi_sh_data *ss, unsigned long data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			     unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (ss->width == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		iowrite8(data, ss->addr + (offset >> 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	else if (ss->width == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		iowrite32(data, ss->addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	if (ss->width == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		return ioread8(ss->addr + (offset >> 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	else if (ss->width == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		return ioread32(ss->addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 				unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	tmp = spi_sh_read(ss, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	tmp |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	spi_sh_write(ss, tmp, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void spi_sh_clear_bit(struct spi_sh_data *ss, unsigned long val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 				unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	tmp = spi_sh_read(ss, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	tmp &= ~val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	spi_sh_write(ss, tmp, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void clear_fifo(struct spi_sh_data *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	spi_sh_set_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	spi_sh_clear_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int spi_sh_wait_receive_buffer(struct spi_sh_data *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	int timeout = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	while (spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		if (timeout-- < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int spi_sh_wait_write_buffer_empty(struct spi_sh_data *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	int timeout = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	while (!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		if (timeout-- < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	int i, retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	int remain = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	int cur_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	unsigned char *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (t->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	data = (unsigned char *)t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	while (remain > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		cur_len = min(SPI_SH_FIFO_SIZE, remain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		for (i = 0; i < cur_len &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 				!(spi_sh_read(ss, SPI_SH_CR4) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 							SPI_SH_WPABRT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 				!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 				i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			spi_sh_write(ss, (unsigned long)data[i], SPI_SH_TBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		if (spi_sh_read(ss, SPI_SH_CR4) & SPI_SH_WPABRT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			/* Abort SPI operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			spi_sh_set_bit(ss, SPI_SH_WPABRT, SPI_SH_CR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			retval = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		cur_len = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		remain -= cur_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		data += cur_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		if (remain > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			ss->cr1 &= ~SPI_SH_TBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			ret = wait_event_interruptible_timeout(ss->wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 						 ss->cr1 & SPI_SH_TBE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 						 SPI_SH_SEND_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 				printk(KERN_ERR "%s: timeout\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 				return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (list_is_last(&t->transfer_list, &mesg->transfers)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		ss->cr1 &= ~SPI_SH_TBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		ret = wait_event_interruptible_timeout(ss->wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 					 ss->cr1 & SPI_SH_TBE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 					 SPI_SH_SEND_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			printk(KERN_ERR "%s: timeout\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			  struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	int remain = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	int cur_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	unsigned char *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (t->len > SPI_SH_MAX_BYTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		spi_sh_write(ss, SPI_SH_MAX_BYTE, SPI_SH_CR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		spi_sh_write(ss, t->len, SPI_SH_CR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	spi_sh_wait_write_buffer_empty(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	data = (unsigned char *)t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	while (remain > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		if (remain >= SPI_SH_FIFO_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			ss->cr1 &= ~SPI_SH_RBF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			spi_sh_set_bit(ss, SPI_SH_RBF, SPI_SH_CR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			ret = wait_event_interruptible_timeout(ss->wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 						 ss->cr1 & SPI_SH_RBF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 						 SPI_SH_RECEIVE_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			if (ret == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			    spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 				printk(KERN_ERR "%s: timeout\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 				return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		cur_len = min(SPI_SH_FIFO_SIZE, remain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		for (i = 0; i < cur_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			if (spi_sh_wait_receive_buffer(ss))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			data[i] = (unsigned char)spi_sh_read(ss, SPI_SH_RBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		remain -= cur_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		data += cur_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	/* deassert CS when SPI is receiving. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (t->len > SPI_SH_MAX_BYTE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		clear_fifo(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		spi_sh_write(ss, 1, SPI_SH_CR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		spi_sh_write(ss, 0, SPI_SH_CR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static void spi_sh_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	struct spi_sh_data *ss = container_of(work, struct spi_sh_data, ws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	struct spi_message *mesg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct spi_transfer *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	pr_debug("%s: enter\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	spin_lock_irqsave(&ss->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	while (!list_empty(&ss->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		mesg = list_entry(ss->queue.next, struct spi_message, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		list_del_init(&mesg->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		spin_unlock_irqrestore(&ss->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		list_for_each_entry(t, &mesg->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			pr_debug("tx_buf = %p, rx_buf = %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 					t->tx_buf, t->rx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			pr_debug("len = %d, delay_usecs = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 					t->len, t->delay_usecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			if (t->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				ret = spi_sh_send(ss, mesg, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 				if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 					goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			if (t->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 				ret = spi_sh_receive(ss, mesg, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 				if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 					goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			mesg->actual_length += t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		spin_lock_irqsave(&ss->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		mesg->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		if (mesg->complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			mesg->complete(mesg->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	clear_fifo(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	spi_sh_set_bit(ss, SPI_SH_SSD, SPI_SH_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			 SPI_SH_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	clear_fifo(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	spin_unlock_irqrestore(&ss->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)  error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	mesg->status = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	if (mesg->complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		mesg->complete(mesg->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			 SPI_SH_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	clear_fifo(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int spi_sh_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	pr_debug("%s: enter\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	spi_sh_write(ss, 0xfe, SPI_SH_CR1);	/* SPI sycle stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	spi_sh_write(ss, 0x00, SPI_SH_CR1);	/* CR1 init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	spi_sh_write(ss, 0x00, SPI_SH_CR3);	/* CR3 init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	clear_fifo(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	/* 1/8 clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	spi_sh_write(ss, spi_sh_read(ss, SPI_SH_CR2) | 0x07, SPI_SH_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int spi_sh_transfer(struct spi_device *spi, struct spi_message *mesg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	pr_debug("%s: enter\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	pr_debug("\tmode = %02x\n", spi->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	spin_lock_irqsave(&ss->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	mesg->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	mesg->status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	spi_sh_clear_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	list_add_tail(&mesg->queue, &ss->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	schedule_work(&ss->ws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	spin_unlock_irqrestore(&ss->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static void spi_sh_cleanup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	pr_debug("%s: enter\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			 SPI_SH_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static irqreturn_t spi_sh_irq(int irq, void *_ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	struct spi_sh_data *ss = (struct spi_sh_data *)_ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	unsigned long cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	cr1 = spi_sh_read(ss, SPI_SH_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	if (cr1 & SPI_SH_TBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		ss->cr1 |= SPI_SH_TBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	if (cr1 & SPI_SH_TBF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		ss->cr1 |= SPI_SH_TBF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	if (cr1 & SPI_SH_RBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		ss->cr1 |= SPI_SH_RBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	if (cr1 & SPI_SH_RBF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		ss->cr1 |= SPI_SH_RBF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	if (ss->cr1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		spi_sh_clear_bit(ss, ss->cr1, SPI_SH_CR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		wake_up(&ss->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int spi_sh_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	struct spi_sh_data *ss = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	spi_unregister_master(ss->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	flush_work(&ss->ws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	free_irq(ss->irq, ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static int spi_sh_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	struct spi_sh_data *ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	/* get base addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	if (unlikely(res == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		dev_err(&pdev->dev, "invalid resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	master = devm_spi_alloc_master(&pdev->dev, sizeof(struct spi_sh_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	if (master == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		dev_err(&pdev->dev, "spi_alloc_master error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	ss = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	platform_set_drvdata(pdev, ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	switch (res->flags & IORESOURCE_MEM_TYPE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	case IORESOURCE_MEM_8BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		ss->width = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	case IORESOURCE_MEM_32BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		ss->width = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		dev_err(&pdev->dev, "No support width\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	ss->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	ss->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	ss->addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	if (ss->addr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 		dev_err(&pdev->dev, "ioremap error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	INIT_LIST_HEAD(&ss->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	spin_lock_init(&ss->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	INIT_WORK(&ss->ws, spi_sh_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	init_waitqueue_head(&ss->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	ret = request_irq(irq, spi_sh_irq, 0, "spi_sh", ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		dev_err(&pdev->dev, "request_irq error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	master->num_chipselect = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	master->bus_num = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	master->setup = spi_sh_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	master->transfer = spi_sh_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	master->cleanup = spi_sh_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	ret = spi_register_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		printk(KERN_ERR "spi_register_master error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 		goto error3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)  error3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	free_irq(irq, ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static struct platform_driver spi_sh_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	.probe = spi_sh_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	.remove = spi_sh_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		.name = "sh_spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) module_platform_driver(spi_sh_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) MODULE_DESCRIPTION("SH SPI bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MODULE_AUTHOR("Yoshihiro Shimoda");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MODULE_ALIAS("platform:sh_spi");