^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SuperH MSIOF SPI Controller Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2009 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2014 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2014-2017 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/sh_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/spi/sh_msiof.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct sh_msiof_chipdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 bits_per_word_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u16 tx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u16 rx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u16 ctlr_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u16 min_div_pow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct sh_msiof_spi_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void __iomem *mapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct sh_msiof_spi_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct completion done_txdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int tx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int rx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int min_div_pow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void *tx_dma_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void *rx_dma_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) dma_addr_t tx_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) dma_addr_t rx_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) bool native_cs_inited;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) bool native_cs_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) bool slave_aborted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MAX_SS 3 /* Maximum number of native chip selects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SITMDR1 0x00 /* Transmit Mode Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SITMDR2 0x04 /* Transmit Mode Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SITMDR3 0x08 /* Transmit Mode Register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SIRMDR1 0x10 /* Receive Mode Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SIRMDR2 0x14 /* Receive Mode Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SIRMDR3 0x18 /* Receive Mode Register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SITSCR 0x20 /* Transmit Clock Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SIRSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SICTR 0x28 /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SIFCTR 0x30 /* FIFO Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SISTR 0x40 /* Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SIIER 0x44 /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SITDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SITDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SITFDR 0x50 /* Transmit FIFO Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SIRDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SIRDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SIRFDR 0x60 /* Receive FIFO Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* SITMDR1 and SIRMDR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SIMDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SIMDR1_SYNCMD_MASK GENMASK(29, 28) /* SYNC Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SIMDR1_SYNCMD_SPI (2 << 28) /* Level mode/SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SIMDR1_SYNCMD_LR (3 << 28) /* L/R mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SIMDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SIMDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SIMDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SIMDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SIMDR1_FLD_MASK GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SIMDR1_FLD_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SIMDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* SITMDR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SITMDR1_PCON BIT(30) /* Transfer Signal Connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SITMDR1_SYNCCH_MASK GENMASK(27, 26) /* Sync Signal Channel Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SITMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* SITMDR2 and SIRMDR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SIMDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SIMDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SIMDR2_GRPMASK1 BIT(0) /* Group Output Mask 1 (SH, A1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* SITSCR and SIRSCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SISCR_BRPS_MASK GENMASK(12, 8) /* Prescaler Setting (1-32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SISCR_BRPS(i) (((i) - 1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SISCR_BRDV_MASK GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SISCR_BRDV_DIV_2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SISCR_BRDV_DIV_4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SISCR_BRDV_DIV_8 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SISCR_BRDV_DIV_16 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SISCR_BRDV_DIV_32 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SISCR_BRDV_DIV_1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* SICTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SICTR_TSCKIZ_MASK GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SICTR_TSCKIZ_SCK BIT(31) /* Disable SCK when TX disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SICTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SICTR_RSCKIZ_MASK GENMASK(29, 28) /* Receive Clock Polarity Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SICTR_RSCKIZ_SCK BIT(29) /* Must match CTR_TSCKIZ_SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SICTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SICTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SICTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SICTR_TXDIZ_MASK GENMASK(23, 22) /* Pin Output When TX is Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SICTR_TXDIZ_LOW (0 << 22) /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SICTR_TXDIZ_HIGH (1 << 22) /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SICTR_TXDIZ_HIZ (2 << 22) /* High-impedance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SICTR_TSCKE BIT(15) /* Transmit Serial Clock Output Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SICTR_TFSE BIT(14) /* Transmit Frame Sync Signal Output Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SICTR_TXE BIT(9) /* Transmit Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SICTR_RXE BIT(8) /* Receive Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SICTR_TXRST BIT(1) /* Transmit Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SICTR_RXRST BIT(0) /* Receive Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* SIFCTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SIFCTR_TFWM_MASK GENMASK(31, 29) /* Transmit FIFO Watermark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SIFCTR_TFWM_64 (0 << 29) /* Transfer Request when 64 empty stages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SIFCTR_TFWM_32 (1 << 29) /* Transfer Request when 32 empty stages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SIFCTR_TFWM_24 (2 << 29) /* Transfer Request when 24 empty stages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SIFCTR_TFWM_16 (3 << 29) /* Transfer Request when 16 empty stages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SIFCTR_TFWM_12 (4 << 29) /* Transfer Request when 12 empty stages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SIFCTR_TFWM_8 (5 << 29) /* Transfer Request when 8 empty stages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SIFCTR_TFWM_4 (6 << 29) /* Transfer Request when 4 empty stages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SIFCTR_TFWM_1 (7 << 29) /* Transfer Request when 1 empty stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SIFCTR_TFUA_MASK GENMASK(26, 20) /* Transmit FIFO Usable Area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SIFCTR_TFUA_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SIFCTR_TFUA(i) ((i) << SIFCTR_TFUA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SIFCTR_RFWM_MASK GENMASK(15, 13) /* Receive FIFO Watermark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SIFCTR_RFWM_1 (0 << 13) /* Transfer Request when 1 valid stages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SIFCTR_RFWM_4 (1 << 13) /* Transfer Request when 4 valid stages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SIFCTR_RFWM_8 (2 << 13) /* Transfer Request when 8 valid stages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SIFCTR_RFWM_16 (3 << 13) /* Transfer Request when 16 valid stages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SIFCTR_RFWM_32 (4 << 13) /* Transfer Request when 32 valid stages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SIFCTR_RFWM_64 (5 << 13) /* Transfer Request when 64 valid stages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SIFCTR_RFWM_128 (6 << 13) /* Transfer Request when 128 valid stages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SIFCTR_RFWM_256 (7 << 13) /* Transfer Request when 256 valid stages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SIFCTR_RFUA_MASK GENMASK(12, 4) /* Receive FIFO Usable Area (0x40 = full) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SIFCTR_RFUA_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SIFCTR_RFUA(i) ((i) << SIFCTR_RFUA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* SISTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SISTR_TFEMP BIT(29) /* Transmit FIFO Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SISTR_TDREQ BIT(28) /* Transmit Data Transfer Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SISTR_TEOF BIT(23) /* Frame Transmission End */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SISTR_TFSERR BIT(21) /* Transmit Frame Synchronization Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SISTR_TFOVF BIT(20) /* Transmit FIFO Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SISTR_TFUDF BIT(19) /* Transmit FIFO Underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SISTR_RFFUL BIT(13) /* Receive FIFO Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SISTR_RDREQ BIT(12) /* Receive Data Transfer Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SISTR_REOF BIT(7) /* Frame Reception End */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SISTR_RFSERR BIT(5) /* Receive Frame Synchronization Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SISTR_RFUDF BIT(4) /* Receive FIFO Underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SISTR_RFOVF BIT(3) /* Receive FIFO Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* SIIER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SIIER_TDMAE BIT(31) /* Transmit Data DMA Transfer Req. Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SIIER_TFEMPE BIT(29) /* Transmit FIFO Empty Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SIIER_TDREQE BIT(28) /* Transmit Data Transfer Request Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SIIER_TEOFE BIT(23) /* Frame Transmission End Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SIIER_TFSERRE BIT(21) /* Transmit Frame Sync Error Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SIIER_TFOVFE BIT(20) /* Transmit FIFO Overflow Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SIIER_TFUDFE BIT(19) /* Transmit FIFO Underflow Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SIIER_RDMAE BIT(15) /* Receive Data DMA Transfer Req. Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SIIER_RFFULE BIT(13) /* Receive FIFO Full Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SIIER_RDREQE BIT(12) /* Receive Data Transfer Request Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SIIER_REOFE BIT(7) /* Frame Reception End Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SIIER_RFSERRE BIT(5) /* Receive Frame Sync Error Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SIIER_RFUDFE BIT(4) /* Receive FIFO Underflow Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SIIER_RFOVFE BIT(3) /* Receive FIFO Overflow Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) switch (reg_offs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) case SITSCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case SIRSCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ioread16(p->mapbase + reg_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return ioread32(p->mapbase + reg_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) switch (reg_offs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case SITSCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case SIRSCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) iowrite16(value, p->mapbase + reg_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) iowrite32(value, p->mapbase + reg_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 clr, u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 mask = clr | set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) data = sh_msiof_read(p, SICTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) data &= ~clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) data |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) sh_msiof_write(p, SICTR, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return readl_poll_timeout_atomic(p->mapbase + SICTR, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) (data & mask) == set, 1, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct sh_msiof_spi_priv *p = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* just disable the interrupt and wake up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) sh_msiof_write(p, SIIER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) complete(&p->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 mask = SICTR_TXRST | SICTR_RXRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) data = sh_msiof_read(p, SICTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) data |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) sh_msiof_write(p, SICTR, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) readl_poll_timeout_atomic(p->mapbase + SICTR, data, !(data & mask), 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const u32 sh_msiof_spi_div_array[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) SISCR_BRDV_DIV_1, SISCR_BRDV_DIV_2, SISCR_BRDV_DIV_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) SISCR_BRDV_DIV_8, SISCR_BRDV_DIV_16, SISCR_BRDV_DIV_32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned long parent_rate, u32 spi_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned long div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 brps, scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int div_pow = p->min_div_pow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (!spi_hz || !parent_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) WARN(1, "Invalid clock rate parameters %lu and %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) parent_rate, spi_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) div = DIV_ROUND_UP(parent_rate, spi_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (div <= 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* SISCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (!div_pow && div <= 32 && div > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) div_pow = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (div_pow)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) brps = (div + 1) >> div_pow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) brps = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) for (; brps > 32; div_pow++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) brps = (brps + 1) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Set transfer rate composite divisor to 2^5 * 32 = 1024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_err(&p->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "Requested SPI transfer rate %d is too low\n", spi_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) div_pow = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) brps = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) scr = sh_msiof_spi_div_array[div_pow] | SISCR_BRPS(brps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) sh_msiof_write(p, SITSCR, scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) sh_msiof_write(p, SIRSCR, scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * b'000 : 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * b'001 : 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * b'010 : 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * b'011 (SYNCDL only) : 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * b'101 : 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * b'110 : 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (dtdl_or_syncdl % 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return dtdl_or_syncdl / 100 + 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return dtdl_or_syncdl / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (!p->info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* check if DTDL and SYNCDL is allowed value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (p->info->dtdl > 200 || p->info->syncdl > 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* check if the sum of DTDL and SYNCDL becomes an integer value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if ((p->info->dtdl + p->info->syncdl) % 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) val = sh_msiof_get_delay_bit(p->info->dtdl) << SIMDR1_DTDL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) val |= sh_msiof_get_delay_bit(p->info->syncdl) << SIMDR1_SYNCDL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 cpol, u32 cpha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 tx_hi_z, u32 lsb_first, u32 cs_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * 0 0 10 10 1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * 0 1 10 10 0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * 1 0 11 11 0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * 1 1 11 11 1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) tmp = SIMDR1_SYNCMD_SPI | 1 << SIMDR1_FLD_SHIFT | SIMDR1_XXSTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) tmp |= !cs_high << SIMDR1_SYNCAC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) tmp |= lsb_first << SIMDR1_BITLSB_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (spi_controller_is_slave(p->ctlr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) sh_msiof_write(p, SITMDR1, tmp | SITMDR1_PCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) sh_msiof_write(p, SITMDR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) tmp | SIMDR1_TRMD | SITMDR1_PCON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) (ss < MAX_SS ? ss : 0) << SITMDR1_SYNCCH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (p->ctlr->flags & SPI_CONTROLLER_MUST_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* These bits are reserved if RX needs TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) tmp &= ~0x0000ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) sh_msiof_write(p, SIRMDR1, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) tmp |= SICTR_TSCKIZ_SCK | cpol << SICTR_TSCKIZ_POL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) tmp |= SICTR_RSCKIZ_SCK | cpol << SICTR_RSCKIZ_POL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) edge = cpol ^ !cpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) tmp |= edge << SICTR_TEDG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) tmp |= edge << SICTR_REDG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) tmp |= tx_hi_z ? SICTR_TXDIZ_HIZ : SICTR_TXDIZ_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) sh_msiof_write(p, SICTR, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) const void *tx_buf, void *rx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 bits, u32 words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u32 dr2 = SIMDR2_BITLEN1(bits) | SIMDR2_WDLEN1(words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) sh_msiof_write(p, SITMDR2, dr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) sh_msiof_write(p, SITMDR2, dr2 | SIMDR2_GRPMASK1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) sh_msiof_write(p, SIRMDR2, dr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) sh_msiof_write(p, SISTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) sh_msiof_read(p, SISTR) & ~(SISTR_TDREQ | SISTR_RDREQ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) const void *tx_buf, int words, int fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) const u8 *buf_8 = tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) for (k = 0; k < words; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) sh_msiof_write(p, SITFDR, buf_8[k] << fs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) const void *tx_buf, int words, int fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) const u16 *buf_16 = tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) for (k = 0; k < words; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) sh_msiof_write(p, SITFDR, buf_16[k] << fs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) const void *tx_buf, int words, int fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) const u16 *buf_16 = tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) for (k = 0; k < words; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) sh_msiof_write(p, SITFDR, get_unaligned(&buf_16[k]) << fs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) const void *tx_buf, int words, int fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) const u32 *buf_32 = tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) for (k = 0; k < words; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) sh_msiof_write(p, SITFDR, buf_32[k] << fs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) const void *tx_buf, int words, int fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) const u32 *buf_32 = tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) for (k = 0; k < words; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) sh_msiof_write(p, SITFDR, get_unaligned(&buf_32[k]) << fs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) const void *tx_buf, int words, int fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) const u32 *buf_32 = tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) for (k = 0; k < words; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) sh_msiof_write(p, SITFDR, swab32(buf_32[k] << fs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) const void *tx_buf, int words, int fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) const u32 *buf_32 = tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) for (k = 0; k < words; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) sh_msiof_write(p, SITFDR, swab32(get_unaligned(&buf_32[k]) << fs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) void *rx_buf, int words, int fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u8 *buf_8 = rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) for (k = 0; k < words; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) buf_8[k] = sh_msiof_read(p, SIRFDR) >> fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) void *rx_buf, int words, int fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u16 *buf_16 = rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) for (k = 0; k < words; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) buf_16[k] = sh_msiof_read(p, SIRFDR) >> fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) void *rx_buf, int words, int fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u16 *buf_16 = rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) for (k = 0; k < words; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_16[k]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) void *rx_buf, int words, int fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u32 *buf_32 = rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) for (k = 0; k < words; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) buf_32[k] = sh_msiof_read(p, SIRFDR) >> fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) void *rx_buf, int words, int fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 *buf_32 = rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) for (k = 0; k < words; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_32[k]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) void *rx_buf, int words, int fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u32 *buf_32 = rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) for (k = 0; k < words; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) buf_32[k] = swab32(sh_msiof_read(p, SIRFDR) >> fs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) void *rx_buf, int words, int fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 *buf_32 = rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) for (k = 0; k < words; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) put_unaligned(swab32(sh_msiof_read(p, SIRFDR) >> fs), &buf_32[k]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int sh_msiof_spi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct sh_msiof_spi_priv *p =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) spi_controller_get_devdata(spi->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 clr, set, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (spi->cs_gpiod || spi_controller_is_slave(p->ctlr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (p->native_cs_inited &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* Configure native chip select mode/polarity early */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) clr = SIMDR1_SYNCMD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) set = SIMDR1_SYNCMD_SPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (spi->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) clr |= BIT(SIMDR1_SYNCAC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) set |= BIT(SIMDR1_SYNCAC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) pm_runtime_get_sync(&p->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) tmp = sh_msiof_read(p, SITMDR1) & ~clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) sh_msiof_write(p, SITMDR1, tmp | set | SIMDR1_TRMD | SITMDR1_PCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) tmp = sh_msiof_read(p, SIRMDR1) & ~clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) sh_msiof_write(p, SIRMDR1, tmp | set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) pm_runtime_put(&p->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) p->native_cs_high = spi->mode & SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) p->native_cs_inited = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int sh_msiof_prepare_message(struct spi_controller *ctlr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) const struct spi_device *spi = msg->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u32 ss, cs_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Configure pins before asserting CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (spi->cs_gpiod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ss = ctlr->unused_native_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) cs_high = p->native_cs_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ss = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) cs_high = !!(spi->mode & SPI_CS_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) !!(spi->mode & SPI_CPHA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) !!(spi->mode & SPI_3WIRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) !!(spi->mode & SPI_LSB_FIRST), cs_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) bool slave = spi_controller_is_slave(p->ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* setup clock and rx/tx signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (!slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TSCKE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (rx_buf && !ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_RXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* start by setting frame bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (!ret && !slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TFSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) bool slave = spi_controller_is_slave(p->ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* shut down frame, rx/tx and clock signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (!slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ret = sh_msiof_modify_ctr_wait(p, SICTR_TFSE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ret = sh_msiof_modify_ctr_wait(p, SICTR_TXE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (rx_buf && !ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = sh_msiof_modify_ctr_wait(p, SICTR_RXE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (!ret && !slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ret = sh_msiof_modify_ctr_wait(p, SICTR_TSCKE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static int sh_msiof_slave_abort(struct spi_controller *ctlr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) p->slave_aborted = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) complete(&p->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) complete(&p->done_txdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct completion *x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (spi_controller_is_slave(p->ctlr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (wait_for_completion_interruptible(x) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) p->slave_aborted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dev_dbg(&p->pdev->dev, "interrupted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (!wait_for_completion_timeout(x, HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dev_err(&p->pdev->dev, "timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) void (*tx_fifo)(struct sh_msiof_spi_priv *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) const void *, int, int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) void (*rx_fifo)(struct sh_msiof_spi_priv *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) void *, int, int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) const void *tx_buf, void *rx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int words, int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) int fifo_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* limit maximum word transfer to rx/tx fifo size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) words = min_t(int, words, p->tx_fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) words = min_t(int, words, p->rx_fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* the fifo contents need shifting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) fifo_shift = 32 - bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* default FIFO watermarks for PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) sh_msiof_write(p, SIFCTR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* setup msiof transfer mode registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) sh_msiof_write(p, SIIER, SIIER_TEOFE | SIIER_REOFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* write tx fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) tx_fifo(p, tx_buf, words, fifo_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) reinit_completion(&p->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) p->slave_aborted = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ret = sh_msiof_spi_start(p, rx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) dev_err(&p->pdev->dev, "failed to start hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) goto stop_ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* wait for tx fifo to be emptied / rx fifo to be filled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ret = sh_msiof_wait_for_completion(p, &p->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) goto stop_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* read rx fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) rx_fifo(p, rx_buf, words, fifo_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* clear status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) sh_msiof_reset_str(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ret = sh_msiof_spi_stop(p, rx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dev_err(&p->pdev->dev, "failed to shut down hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) stop_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) sh_msiof_reset_str(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) sh_msiof_spi_stop(p, rx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) stop_ier:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) sh_msiof_write(p, SIIER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static void sh_msiof_dma_complete(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) complete(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) void *rx, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u32 ier_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* First prepare and submit the DMA request(s), as this may fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ier_bits |= SIIER_RDREQE | SIIER_RDMAE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) desc_rx = dmaengine_prep_slave_single(p->ctlr->dma_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) p->rx_dma_addr, len, DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (!desc_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) desc_rx->callback = sh_msiof_dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) desc_rx->callback_param = &p->done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) cookie = dmaengine_submit(desc_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (dma_submit_error(cookie))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ier_bits |= SIIER_TDREQE | SIIER_TDMAE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dma_sync_single_for_device(p->ctlr->dma_tx->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) p->tx_dma_addr, len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) desc_tx = dmaengine_prep_slave_single(p->ctlr->dma_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) p->tx_dma_addr, len, DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (!desc_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) goto no_dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) desc_tx->callback = sh_msiof_dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) desc_tx->callback_param = &p->done_txdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) cookie = dmaengine_submit(desc_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (dma_submit_error(cookie)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ret = cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) goto no_dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* 1 stage FIFO watermarks for DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) sh_msiof_write(p, SIFCTR, SIFCTR_TFWM_1 | SIFCTR_RFWM_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* setup msiof transfer mode registers (32-bit words) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) sh_msiof_write(p, SIIER, ier_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) reinit_completion(&p->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) reinit_completion(&p->done_txdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) p->slave_aborted = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* Now start DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dma_async_issue_pending(p->ctlr->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dma_async_issue_pending(p->ctlr->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ret = sh_msiof_spi_start(p, rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dev_err(&p->pdev->dev, "failed to start hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) goto stop_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* wait for tx DMA completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ret = sh_msiof_wait_for_completion(p, &p->done_txdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) goto stop_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* wait for rx DMA completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ret = sh_msiof_wait_for_completion(p, &p->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) goto stop_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) sh_msiof_write(p, SIIER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* wait for tx fifo to be emptied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) sh_msiof_write(p, SIIER, SIIER_TEOFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ret = sh_msiof_wait_for_completion(p, &p->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) goto stop_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* clear status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) sh_msiof_reset_str(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) ret = sh_msiof_spi_stop(p, rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) dev_err(&p->pdev->dev, "failed to shut down hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dma_sync_single_for_cpu(p->ctlr->dma_rx->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) p->rx_dma_addr, len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) stop_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) sh_msiof_reset_str(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) sh_msiof_spi_stop(p, rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) stop_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dmaengine_terminate_all(p->ctlr->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) no_dma_tx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) dmaengine_terminate_all(p->ctlr->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) sh_msiof_write(p, SIIER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* src or dst can be unaligned, but not both */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if ((unsigned long)src & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) while (words--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) *dst++ = swab32(get_unaligned(src));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) } else if ((unsigned long)dst & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) while (words--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) put_unaligned(swab32(*src++), dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) while (words--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) *dst++ = swab32(*src++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /* src or dst can be unaligned, but not both */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if ((unsigned long)src & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) while (words--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) *dst++ = swahw32(get_unaligned(src));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) } else if ((unsigned long)dst & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) while (words--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) put_unaligned(swahw32(*src++), dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) dst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) while (words--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) *dst++ = swahw32(*src++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) memcpy(dst, src, words * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static int sh_msiof_transfer_one(struct spi_controller *ctlr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) void (*copy32)(u32 *, const u32 *, unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) const void *tx_buf = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) void *rx_buf = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) unsigned int len = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) unsigned int bits = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) unsigned int bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) unsigned int words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) bool swab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* reset registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) sh_msiof_spi_reset_regs(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* setup clocks (clock already enabled in chipselect()) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!spi_controller_is_slave(p->ctlr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) while (ctlr->dma_tx && len > 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * words, with byte resp. word swapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) unsigned int l = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) l = min(round_down(len, 4), p->tx_fifo_size * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) l = min(round_down(len, 4), p->rx_fifo_size * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (bits <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) copy32 = copy_bswap32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) } else if (bits <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) copy32 = copy_wswap32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) copy32 = copy_plain32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) copy32(p->tx_dma_page, tx_buf, l / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (ret == -EAGAIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) dev_warn_once(&p->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) "DMA not available, falling back to PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) copy32(rx_buf, p->rx_dma_page, l / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) rx_buf += l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) tx_buf += l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) len -= l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (!len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (bits <= 8 && len > 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) bits = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) swab = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) swab = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* setup bytes per word and fifo read/write functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (bits <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) bytes_per_word = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) tx_fifo = sh_msiof_spi_write_fifo_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) rx_fifo = sh_msiof_spi_read_fifo_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) } else if (bits <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) bytes_per_word = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if ((unsigned long)tx_buf & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) tx_fifo = sh_msiof_spi_write_fifo_16u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) tx_fifo = sh_msiof_spi_write_fifo_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if ((unsigned long)rx_buf & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) rx_fifo = sh_msiof_spi_read_fifo_16u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) rx_fifo = sh_msiof_spi_read_fifo_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) } else if (swab) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) bytes_per_word = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if ((unsigned long)tx_buf & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) tx_fifo = sh_msiof_spi_write_fifo_s32u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) tx_fifo = sh_msiof_spi_write_fifo_s32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if ((unsigned long)rx_buf & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) rx_fifo = sh_msiof_spi_read_fifo_s32u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) rx_fifo = sh_msiof_spi_read_fifo_s32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) bytes_per_word = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if ((unsigned long)tx_buf & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) tx_fifo = sh_msiof_spi_write_fifo_32u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) tx_fifo = sh_msiof_spi_write_fifo_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if ((unsigned long)rx_buf & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) rx_fifo = sh_msiof_spi_read_fifo_32u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) rx_fifo = sh_msiof_spi_read_fifo_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /* transfer in fifo sized chunks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) words = len / bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) while (words > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) words, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (n < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) tx_buf += n * bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) rx_buf += n * bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) words -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (words == 0 && (len % bytes_per_word)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) words = len % bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) bits = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) bytes_per_word = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) tx_fifo = sh_msiof_spi_write_fifo_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) rx_fifo = sh_msiof_spi_read_fifo_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static const struct sh_msiof_chipdata sh_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .tx_fifo_size = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .rx_fifo_size = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .ctlr_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .min_div_pow = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static const struct sh_msiof_chipdata rcar_gen2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .tx_fifo_size = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .rx_fifo_size = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .ctlr_flags = SPI_CONTROLLER_MUST_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .min_div_pow = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static const struct sh_msiof_chipdata rcar_gen3_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .tx_fifo_size = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .rx_fifo_size = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .ctlr_flags = SPI_CONTROLLER_MUST_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .min_div_pow = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static const struct of_device_id sh_msiof_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) MODULE_DEVICE_TABLE(of, sh_msiof_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) struct sh_msiof_spi_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) u32 num_cs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) : MSIOF_SPI_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* Parse the MSIOF properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (info->mode == MSIOF_SPI_MASTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) of_property_read_u32(np, "num-cs", &num_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) of_property_read_u32(np, "renesas,tx-fifo-size",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) &info->tx_fifo_override);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) of_property_read_u32(np, "renesas,rx-fifo-size",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) &info->rx_fifo_override);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) info->num_chipselect = num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) return info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) struct dma_slave_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) dma_cap_set(DMA_SLAVE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) (void *)(unsigned long)id, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) dir == DMA_MEM_TO_DEV ? "tx" : "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (!chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) dev_warn(dev, "dma_request_slave_channel_compat failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) memset(&cfg, 0, sizeof(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) cfg.direction = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (dir == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) cfg.dst_addr = port_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) cfg.src_addr = port_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) ret = dmaengine_slave_config(chan, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) dma_release_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) struct platform_device *pdev = p->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) const struct sh_msiof_spi_info *info = p->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) unsigned int dma_tx_id, dma_rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) const struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct device *tx_dev, *rx_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /* In the OF case we will get the slave IDs from the DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) dma_tx_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) dma_rx_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) } else if (info && info->dma_tx_id && info->dma_rx_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) dma_tx_id = info->dma_tx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) dma_rx_id = info->dma_rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* The driver assumes no error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* The DMA engine uses the second register set, if present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ctlr = p->ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ctlr->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) dma_tx_id, res->start + SITFDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (!ctlr->dma_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) ctlr->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) dma_rx_id, res->start + SIRFDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (!ctlr->dma_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) goto free_tx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (!p->tx_dma_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) goto free_rx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (!p->rx_dma_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) goto free_tx_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) tx_dev = ctlr->dma_tx->device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (dma_mapping_error(tx_dev, p->tx_dma_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) goto free_rx_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) rx_dev = ctlr->dma_rx->device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (dma_mapping_error(rx_dev, p->rx_dma_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) goto unmap_tx_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) dev_info(dev, "DMA available");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) unmap_tx_page:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) free_rx_page:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) free_page((unsigned long)p->rx_dma_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) free_tx_page:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) free_page((unsigned long)p->tx_dma_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) free_rx_chan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) dma_release_channel(ctlr->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) free_tx_chan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) dma_release_channel(ctlr->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ctlr->dma_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct spi_controller *ctlr = p->ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (!ctlr->dma_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) dma_unmap_single(ctlr->dma_rx->device->dev, p->rx_dma_addr, PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) dma_unmap_single(ctlr->dma_tx->device->dev, p->tx_dma_addr, PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) free_page((unsigned long)p->rx_dma_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) free_page((unsigned long)p->tx_dma_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) dma_release_channel(ctlr->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) dma_release_channel(ctlr->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static int sh_msiof_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) const struct sh_msiof_chipdata *chipdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct sh_msiof_spi_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct sh_msiof_spi_priv *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) chipdata = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (chipdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) info = sh_msiof_spi_parse_dt(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) chipdata = (const void *)pdev->id_entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) info = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (!info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) dev_err(&pdev->dev, "failed to obtain device info\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (info->mode == MSIOF_SPI_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) ctlr = spi_alloc_slave(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) sizeof(struct sh_msiof_spi_priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) ctlr = spi_alloc_master(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) sizeof(struct sh_msiof_spi_priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (ctlr == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) p = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) platform_set_drvdata(pdev, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) p->ctlr = ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) p->info = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) p->min_div_pow = chipdata->min_div_pow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) init_completion(&p->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) init_completion(&p->done_txdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) p->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (IS_ERR(p->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) dev_err(&pdev->dev, "cannot get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ret = PTR_ERR(p->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) i = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (i < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) ret = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) p->mapbase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (IS_ERR(p->mapbase)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) ret = PTR_ERR(p->mapbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) dev_name(&pdev->dev), p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) dev_err(&pdev->dev, "unable to request irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) p->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) /* Platform data may override FIFO sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) p->tx_fifo_size = chipdata->tx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) p->rx_fifo_size = chipdata->rx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (p->info->tx_fifo_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) p->tx_fifo_size = p->info->tx_fifo_override;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (p->info->rx_fifo_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) p->rx_fifo_size = p->info->rx_fifo_override;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /* init controller code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) ctlr->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ctlr->flags = chipdata->ctlr_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) ctlr->bus_num = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) ctlr->num_chipselect = p->info->num_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ctlr->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ctlr->setup = sh_msiof_spi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) ctlr->prepare_message = sh_msiof_prepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) ctlr->slave_abort = sh_msiof_slave_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) ctlr->bits_per_word_mask = chipdata->bits_per_word_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) ctlr->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ctlr->transfer_one = sh_msiof_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ctlr->use_gpio_descriptors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ctlr->max_native_cs = MAX_SS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) ret = sh_msiof_request_dma(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) dev_warn(&pdev->dev, "DMA not available, using PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) ret = devm_spi_register_controller(&pdev->dev, ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) sh_msiof_release_dma(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) spi_controller_put(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) static int sh_msiof_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) sh_msiof_release_dma(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static const struct platform_device_id spi_driver_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) MODULE_DEVICE_TABLE(platform, spi_driver_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static int sh_msiof_spi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) return spi_controller_suspend(p->ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) static int sh_msiof_spi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return spi_controller_resume(p->ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) sh_msiof_spi_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #define DEV_PM_OPS (&sh_msiof_spi_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) #define DEV_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static struct platform_driver sh_msiof_spi_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .probe = sh_msiof_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .remove = sh_msiof_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .id_table = spi_driver_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .name = "spi_sh_msiof",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .pm = DEV_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .of_match_table = of_match_ptr(sh_msiof_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) module_platform_driver(sh_msiof_spi_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) MODULE_DESCRIPTION("SuperH MSIOF SPI Controller Interface Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) MODULE_AUTHOR("Magnus Damm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) MODULE_ALIAS("platform:spi_sh_msiof");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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