^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SuperH HSPI bus driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 Kuninori Morimoto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on spi-sh.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on pxa2xx_spi.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2011 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spi/sh_hspi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPCR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPSR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPSCR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPTBR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPRBR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPCR2 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* SPSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RXFL (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct hspi_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * basic function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static void hspi_write(struct hspi_priv *hspi, int reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) iowrite32(val, hspi->addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static u32 hspi_read(struct hspi_priv *hspi, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return ioread32(hspi->addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void hspi_bit_set(struct hspi_priv *hspi, int reg, u32 mask, u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 val = hspi_read(hspi, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) val |= set & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) hspi_write(hspi, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * transfer function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int t = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) while (t--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if ((mask & hspi_read(hspi, SPSR)) == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dev_err(hspi->dev, "timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * spi master function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define hspi_hw_cs_enable(hspi) hspi_hw_cs_ctrl(hspi, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define hspi_hw_cs_disable(hspi) hspi_hw_cs_ctrl(hspi, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static void hspi_hw_cs_ctrl(struct hspi_priv *hspi, int hi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) hspi_bit_set(hspi, SPSCR, (1 << 6), (hi) << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void hspi_hw_setup(struct hspi_priv *hspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct spi_message *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct spi_device *spi = msg->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct device *dev = hspi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 spcr, idiv_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 rate, best_rate, min, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * find best IDIV/CLKCx settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) min = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) best_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) spcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) for (idiv_clk = 0x00; idiv_clk <= 0x3F; idiv_clk++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) rate = clk_get_rate(hspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* IDIV calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (idiv_clk & (1 << 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) rate /= 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) rate /= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* CLKCx calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) rate /= (((idiv_clk & 0x1F) + 1) * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* save best settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) tmp = abs(t->speed_hz - rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (tmp < min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) min = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) spcr = idiv_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) best_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) spcr |= 1 << 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) spcr |= 1 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dev_dbg(dev, "speed %d/%d\n", t->speed_hz, best_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) hspi_write(hspi, SPCR, spcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) hspi_write(hspi, SPSR, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) hspi_write(hspi, SPSCR, 0x21); /* master mode / CS control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int hspi_transfer_one_message(struct spi_controller *ctlr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct hspi_priv *hspi = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct spi_transfer *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned int cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) const int nsecs = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dev_dbg(hspi->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) cs_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) list_for_each_entry(t, &msg->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (cs_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) hspi_hw_setup(hspi, msg, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) hspi_hw_cs_enable(hspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ndelay(nsecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) cs_change = t->cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) for (i = 0; i < t->len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* wait remains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ret = hspi_status_check_timeout(hspi, 0x1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (t->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tx = (u32)((u8 *)t->tx_buf)[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) hspi_write(hspi, SPTBR, tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* wait receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = hspi_status_check_timeout(hspi, 0x4, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) rx = hspi_read(hspi, SPRBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (t->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ((u8 *)t->rx_buf)[i] = (u8)rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) msg->actual_length += t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) spi_transfer_delay_exec(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (cs_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ndelay(nsecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) hspi_hw_cs_disable(hspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ndelay(nsecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) msg->status = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!cs_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ndelay(nsecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) hspi_hw_cs_disable(hspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) spi_finalize_current_message(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int hspi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct hspi_priv *hspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* get base addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev_err(&pdev->dev, "invalid resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ctlr = spi_alloc_master(&pdev->dev, sizeof(*hspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!ctlr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) clk = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_err(&pdev->dev, "couldn't get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) goto error0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) hspi = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) platform_set_drvdata(pdev, hspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* init hspi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) hspi->ctlr = ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) hspi->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) hspi->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) hspi->addr = devm_ioremap(hspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!hspi->addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) goto error1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ctlr->bus_num = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ctlr->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ctlr->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ctlr->transfer_one_message = hspi_transfer_one_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ret = devm_spi_register_controller(&pdev->dev, ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) goto error2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) error2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) error1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) error0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) spi_controller_put(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int hspi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct hspi_priv *hspi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) clk_put(hspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const struct of_device_id hspi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { .compatible = "renesas,hspi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MODULE_DEVICE_TABLE(of, hspi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static struct platform_driver hspi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .probe = hspi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .remove = hspi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .name = "sh-hspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .of_match_table = hspi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) module_platform_driver(hspi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MODULE_DESCRIPTION("SuperH HSPI bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MODULE_ALIAS("platform:sh-hspi");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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