^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * NXP SC18IS602/603 SPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) Guenter Roeck <linux@roeck-us.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_data/sc18is602.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) enum chips { sc18is602, sc18is602b, sc18is603 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SC18IS602_BUFSIZ 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SC18IS602_CLOCK 7372000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SC18IS602_MODE_CPHA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SC18IS602_MODE_CPOL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SC18IS602_MODE_LSB_FIRST BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SC18IS602_MODE_CLOCK_DIV_4 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SC18IS602_MODE_CLOCK_DIV_16 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SC18IS602_MODE_CLOCK_DIV_64 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SC18IS602_MODE_CLOCK_DIV_128 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct sc18is602 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u8 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* I2C data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) enum chips id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 buffer[SC18IS602_BUFSIZ + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int tlen; /* Data queued for tx in buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int rindex; /* Receive data index in buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct gpio_desc *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int sc18is602_wait_ready(struct sc18is602 *hw, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int usecs = 1000000 * len / hw->speed + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 dummy[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) err = i2c_master_recv(hw->client, dummy, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (err >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) usleep_range(usecs, usecs * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int sc18is602_txrx(struct sc18is602 *hw, struct spi_message *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct spi_transfer *t, bool do_transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int len = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (hw->tlen == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* First byte (I2C command) is chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) hw->buffer[0] = 1 << msg->spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) hw->tlen = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) hw->rindex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * We can not immediately send data to the chip, since each I2C message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * resembles a full SPI message (from CS active to CS inactive).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Enqueue messages up to the first read or until do_transfer is true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (t->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) memcpy(&hw->buffer[hw->tlen], t->tx_buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) hw->tlen += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (t->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) do_transfer = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) hw->rindex = hw->tlen - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) } else if (t->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * For receive-only transfers we still need to perform a dummy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * write to receive data from the SPI chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Read data starts at the end of transmit data (minus 1 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * account for CS).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) hw->rindex = hw->tlen - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) memset(&hw->buffer[hw->tlen], 0, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) hw->tlen += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) do_transfer = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (do_transfer && hw->tlen > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ret = sc18is602_wait_ready(hw, SC18IS602_BUFSIZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret = i2c_master_send(hw->client, hw->buffer, hw->tlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (ret != hw->tlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (t->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int rlen = hw->rindex + len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = sc18is602_wait_ready(hw, hw->tlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = i2c_master_recv(hw->client, hw->buffer, rlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ret != rlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) memcpy(t->rx_buf, &hw->buffer[hw->rindex], len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) hw->tlen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int sc18is602_setup_transfer(struct sc18is602 *hw, u32 hz, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u8 ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ctrl |= SC18IS602_MODE_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ctrl |= SC18IS602_MODE_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (mode & SPI_LSB_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ctrl |= SC18IS602_MODE_LSB_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Find the closest clock speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (hz >= hw->freq / 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ctrl |= SC18IS602_MODE_CLOCK_DIV_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) hw->speed = hw->freq / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) } else if (hz >= hw->freq / 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ctrl |= SC18IS602_MODE_CLOCK_DIV_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) hw->speed = hw->freq / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) } else if (hz >= hw->freq / 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ctrl |= SC18IS602_MODE_CLOCK_DIV_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) hw->speed = hw->freq / 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ctrl |= SC18IS602_MODE_CLOCK_DIV_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) hw->speed = hw->freq / 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Don't do anything if the control value did not change. The initial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * value of 0xff for hw->ctrl ensures that the correct mode will be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * with the first call to this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ctrl == hw->ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = i2c_smbus_write_byte_data(hw->client, 0xf0, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) hw->ctrl = ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int sc18is602_check_transfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct spi_transfer *t, int tlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (t && t->len + tlen > SC18IS602_BUFSIZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int sc18is602_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct spi_message *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct sc18is602 *hw = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct spi_device *spi = m->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct spi_transfer *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) hw->tlen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) list_for_each_entry(t, &m->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) bool do_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) status = sc18is602_check_transfer(spi, t, hw->tlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) status = sc18is602_setup_transfer(hw, t->speed_hz, spi->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) do_transfer = t->cs_change || list_is_last(&t->transfer_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) &m->transfers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (t->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) status = sc18is602_txrx(hw, m, t, do_transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) m->actual_length += status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) spi_transfer_delay_exec(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) m->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) spi_finalize_current_message(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int sc18is602_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct sc18is602 *hw = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* SC18IS602 does not support CS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (hw->id == sc18is602 && spi->chip_select == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int sc18is602_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct sc18is602_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct sc18is602 *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) master = devm_spi_alloc_master(dev, sizeof(struct sc18is602));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) hw = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) i2c_set_clientdata(client, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* assert reset and then release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) hw->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (IS_ERR(hw->reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return PTR_ERR(hw->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) gpiod_set_value_cansleep(hw->reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) hw->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) hw->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) hw->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) hw->ctrl = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (client->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) hw->id = (enum chips)of_device_get_match_data(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) hw->id = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) switch (hw->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case sc18is602:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case sc18is602b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) master->num_chipselect = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) hw->freq = SC18IS602_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case sc18is603:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) master->num_chipselect = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) hw->freq = pdata->clock_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) const __be32 *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) val = of_get_property(np, "clock-frequency", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (val && len >= sizeof(__be32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) hw->freq = be32_to_cpup(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (!hw->freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) hw->freq = SC18IS602_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) master->bus_num = np ? -1 : client->adapter->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) master->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) master->setup = sc18is602_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) master->transfer_one_message = sc18is602_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) master->dev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) master->min_speed_hz = hw->freq / 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) master->max_speed_hz = hw->freq / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return devm_spi_register_master(dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const struct i2c_device_id sc18is602_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { "sc18is602", sc18is602 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { "sc18is602b", sc18is602b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { "sc18is603", sc18is603 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MODULE_DEVICE_TABLE(i2c, sc18is602_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const struct of_device_id sc18is602_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .compatible = "nxp,sc18is602",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .data = (void *)sc18is602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .compatible = "nxp,sc18is602b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .data = (void *)sc18is602b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .compatible = "nxp,sc18is603",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .data = (void *)sc18is603
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) MODULE_DEVICE_TABLE(of, sc18is602_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static struct i2c_driver sc18is602_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .name = "sc18is602",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .of_match_table = of_match_ptr(sc18is602_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .probe = sc18is602_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .id_table = sc18is602_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) module_i2c_driver(sc18is602_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MODULE_DESCRIPTION("SC18IS602/603 SPI Master Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MODULE_AUTHOR("Guenter Roeck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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