^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2006 Ben Dooks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2006-2009 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spi/spi_bitbang.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spi/s3c24xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spi/s3c24xx-fiq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/fiq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "spi-s3c24xx-regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * struct s3c24xx_spi_devstate - per device data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @hz: Last frequency calculated for @sppre field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @mode: Last mode setting for the @spcon field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @spcon: Value to write to the SPCON register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @sppre: Value to write to the SPPRE register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct s3c24xx_spi_devstate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 spcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 sppre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum spi_fiq_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) FIQ_MODE_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) FIQ_MODE_TX = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) FIQ_MODE_RX = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) FIQ_MODE_TXRX = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct s3c24xx_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* bitbang has to be first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct spi_bitbang bitbang;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct fiq_handler fiq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum spi_fiq_mode fiq_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned char fiq_inuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned char fiq_claimed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void (*set_cs)(struct s3c2410_spi_info *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int cs, int pol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* data buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) const unsigned char *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned char *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct spi_device *curdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct s3c2410_spi_info *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return spi_master_get_devdata(sdev->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) gpio_set_value(spi->pin_cs, pol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct s3c24xx_spi_devstate *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct s3c24xx_spi *hw = to_hw(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* change the chipselect state and the state of the spi engine clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) switch (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case BITBANG_CS_INACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) writeb(cs->spcon, hw->regs + S3C2410_SPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case BITBANG_CS_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) writeb(cs->spcon | S3C2410_SPCON_ENSCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) hw->regs + S3C2410_SPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) hw->set_cs(hw->pdata, spi->chip_select, cspol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int s3c24xx_spi_update_state(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct s3c24xx_spi *hw = to_hw(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct s3c24xx_spi_devstate *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned long clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) hz = t ? t->speed_hz : spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) hz = spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (spi->mode != cs->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) spcon |= S3C2410_SPCON_CPHA_FMTB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) spcon |= S3C2410_SPCON_CPOL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) cs->mode = spi->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) cs->spcon = spcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (cs->hz != hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) clk = clk_get_rate(hw->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) div = DIV_ROUND_UP(clk, hz * 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (div > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) div = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) div, hz, clk / (2 * (div + 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) cs->hz = hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) cs->sppre = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int s3c24xx_spi_setupxfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct s3c24xx_spi_devstate *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct s3c24xx_spi *hw = to_hw(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = s3c24xx_spi_update_state(spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int s3c24xx_spi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct s3c24xx_spi_devstate *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct s3c24xx_spi *hw = to_hw(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* allocate settings on the first call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (!cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) cs = devm_kzalloc(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) sizeof(struct s3c24xx_spi_devstate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (!cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) cs->spcon = SPCON_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) cs->hz = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) spi->controller_state = cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* initialise the state from the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ret = s3c24xx_spi_update_state(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) mutex_lock(&hw->bitbang.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (!hw->bitbang.busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* need to ndelay for 0.5 clocktick ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mutex_unlock(&hw->bitbang.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return hw->tx ? hw->tx[count] : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #ifdef CONFIG_SPI_S3C24XX_FIQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Support for FIQ based pseudo-DMA to improve the transfer speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * This code uses the assembly helper in spi_s3c24xx_spi.S which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * used by the FIQ core to move data between main memory and the peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * block. Since this is code running on the processor, there is no problem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * with cache coherency of the buffers, so we can use any buffer we like.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * struct spi_fiq_code - FIQ code and header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @length: The length of the code fragment, excluding this header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @data: The code itself to install as a FIQ handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct spi_fiq_code {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 ack_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @hw: The hardware state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * Claim the FIQ handler (only one can be active at any one time) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * then setup the correct transfer code for this transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * This call updates all the necessary state information if successful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * so the caller does not need to do anything more than start the transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * as normal, since the IRQ will have been re-routed to the FIQ handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct pt_regs regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) enum spi_fiq_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct spi_fiq_code *code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 *ack_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!hw->fiq_claimed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* try and claim fiq if we haven't got it, and if not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * then return and simply use another transfer method */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ret = claim_fiq(&hw->fiq_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (hw->tx && !hw->rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mode = FIQ_MODE_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) else if (hw->rx && !hw->tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) mode = FIQ_MODE_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mode = FIQ_MODE_TXRX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) regs.uregs[fiq_rspi] = (long)hw->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) regs.uregs[fiq_rrx] = (long)hw->rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) regs.uregs[fiq_rtx] = (long)hw->tx + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) regs.uregs[fiq_rcount] = hw->len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) set_fiq_regs(®s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (hw->fiq_mode != mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) hw->fiq_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case FIQ_MODE_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) code = &s3c24xx_spi_fiq_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case FIQ_MODE_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) code = &s3c24xx_spi_fiq_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case FIQ_MODE_TXRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) code = &s3c24xx_spi_fiq_txrx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) code = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) BUG_ON(!code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ack_ptr = (u32 *)&code->data[code->ack_offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) set_fiq_handler(&code->data, code->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) s3c24xx_set_fiq(hw->irq, ack_ptr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) hw->fiq_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) hw->fiq_inuse = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * s3c24xx_spi_fiqop - FIQ core code callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * @pw: Data registered with the handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * @release: Whether this is a release or a return.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * Called by the FIQ code when another module wants to use the FIQ, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * return whether we are currently using this or not and then update our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * internal state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int s3c24xx_spi_fiqop(void *pw, int release)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct s3c24xx_spi *hw = pw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (release) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (hw->fiq_inuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* note, we do not need to unroute the FIQ, as the FIQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * vector code de-routes it to signal the end of transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) hw->fiq_mode = FIQ_MODE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) hw->fiq_claimed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) hw->fiq_claimed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * s3c24xx_spi_initfiq - setup the information for the FIQ core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * @hw: The hardware state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * Setup the fiq_handler block to pass to the FIQ core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) hw->fiq_handler.dev_id = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) hw->fiq_handler.name = dev_name(hw->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * s3c24xx_spi_usefiq - return if we should be using FIQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * @hw: The hardware state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * Return true if the platform data specifies whether this channel is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * allowed to use the FIQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return hw->pdata->use_fiq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * s3c24xx_spi_usingfiq - return if channel is using FIQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * @spi: The hardware state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * Return whether the channel is currently using the FIQ (separate from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * whether the FIQ is claimed).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return spi->fiq_inuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #endif /* CONFIG_SPI_S3C24XX_FIQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct s3c24xx_spi *hw = to_hw(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) hw->tx = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) hw->rx = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) hw->len = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) hw->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) init_completion(&hw->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) hw->fiq_inuse = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) s3c24xx_spi_tryfiq(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* send the first byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) wait_for_completion(&hw->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return hw->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct s3c24xx_spi *hw = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned int count = hw->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (spsta & S3C2410_SPSTA_DCOL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dev_dbg(hw->dev, "data-collision\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) complete(&hw->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) goto irq_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (!(spsta & S3C2410_SPSTA_READY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dev_dbg(hw->dev, "spi not ready for tx?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) complete(&hw->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) goto irq_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!s3c24xx_spi_usingfiq(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) hw->count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (hw->rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (count < hw->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) complete(&hw->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) hw->count = hw->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) hw->fiq_inuse = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (hw->rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) complete(&hw->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) irq_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* for the moment, permanently enable the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) clk_enable(hw->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* program defaults into the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) writeb(0xff, hw->regs + S3C2410_SPPRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (hw->pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (hw->set_cs == s3c24xx_spi_gpiocs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) gpio_direction_output(hw->pdata->pin_cs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (hw->pdata->gpio_setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) hw->pdata->gpio_setup(hw->pdata, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static int s3c24xx_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct s3c2410_spi_info *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct s3c24xx_spi *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (master == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_err(&pdev->dev, "No memory for spi_master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) hw = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) hw->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) hw->pdata = pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) hw->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (pdata == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev_err(&pdev->dev, "No platform data supplied\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) err = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) goto err_no_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) platform_set_drvdata(pdev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) init_completion(&hw->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* initialise fiq handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) s3c24xx_spi_initfiq(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* setup the master state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* the spi->mode bits understood by this driver: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) master->num_chipselect = hw->pdata->num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) master->bus_num = pdata->bus_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) master->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* setup the state for the bitbang driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) hw->bitbang.master = hw->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) hw->bitbang.chipselect = s3c24xx_spi_chipsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) hw->master->setup = s3c24xx_spi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* find and map our resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) hw->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (IS_ERR(hw->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) err = PTR_ERR(hw->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) goto err_no_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) hw->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (hw->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) err = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) goto err_no_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pdev->name, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dev_err(&pdev->dev, "Cannot claim IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) goto err_no_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) hw->clk = devm_clk_get(&pdev->dev, "spi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (IS_ERR(hw->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dev_err(&pdev->dev, "No clock for device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) err = PTR_ERR(hw->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) goto err_no_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* setup any gpio we can */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (!pdata->set_cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (pdata->pin_cs < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dev_err(&pdev->dev, "No chipselect pin\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) err = devm_gpio_request(&pdev->dev, pdata->pin_cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dev_err(&pdev->dev, "Failed to get gpio for cs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) hw->set_cs = s3c24xx_spi_gpiocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) gpio_direction_output(pdata->pin_cs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) hw->set_cs = pdata->set_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) s3c24xx_spi_initialsetup(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* register our spi controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) err = spi_bitbang_start(&hw->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dev_err(&pdev->dev, "Failed to register SPI master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) err_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) clk_disable(hw->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) err_no_pdata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) spi_master_put(hw->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int s3c24xx_spi_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct s3c24xx_spi *hw = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) spi_bitbang_stop(&hw->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) clk_disable(hw->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) spi_master_put(hw->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int s3c24xx_spi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct s3c24xx_spi *hw = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ret = spi_master_suspend(hw->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (hw->pdata && hw->pdata->gpio_setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) hw->pdata->gpio_setup(hw->pdata, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) clk_disable(hw->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int s3c24xx_spi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct s3c24xx_spi *hw = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) s3c24xx_spi_initialsetup(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return spi_master_resume(hw->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static const struct dev_pm_ops s3c24xx_spi_pmops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .suspend = s3c24xx_spi_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .resume = s3c24xx_spi_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define S3C24XX_SPI_PMOPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) MODULE_ALIAS("platform:s3c2410-spi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static struct platform_driver s3c24xx_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .probe = s3c24xx_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .remove = s3c24xx_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .name = "s3c2410-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .pm = S3C24XX_SPI_PMOPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) module_platform_driver(s3c24xx_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) MODULE_DESCRIPTION("S3C24XX SPI Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags