Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2004 Fetron GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * S3C2410 SPI register definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __SPI_S3C2410_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __SPI_S3C2410_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define S3C2410_SPCON		(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define S3C2410_SPCON_SMOD_DMA	(2 << 5)	/* DMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define S3C2410_SPCON_SMOD_INT	(1 << 5)	/* interrupt mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define S3C2410_SPCON_SMOD_POLL	(0 << 5)	/* polling mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define S3C2410_SPCON_ENSCK	(1 << 4)	/* Enable SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S3C2410_SPCON_MSTR	(1 << 3)	/* Master:1, Slave:0 select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define S3C2410_SPCON_CPOL_HIGH	(1 << 2)	/* Clock polarity select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S3C2410_SPCON_CPOL_LOW	(0 << 2)	/* Clock polarity select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S3C2410_SPCON_CPHA_FMTB	(1 << 1)	/* Clock Phase Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S3C2410_SPCON_CPHA_FMTA	(0 << 1)	/* Clock Phase Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define S3C2410_SPSTA		(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S3C2410_SPSTA_DCOL	(1 << 2)	/* Data Collision Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define S3C2410_SPSTA_MULD	(1 << 1)	/* Multi Master Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define S3C2410_SPSTA_READY	(1 << 0)	/* Data Tx/Rx ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define S3C2412_SPSTA_READY_ORG	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S3C2410_SPPIN		(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S3C2410_SPPIN_ENMUL	(1 << 2)	/* Multi Master Error detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define S3C2410_SPPIN_RESERVED	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define S3C2410_SPPIN_KEEP	(1 << 0)	/* Master Out keep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define S3C2410_SPPRE		(0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S3C2410_SPTDAT		(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S3C2410_SPRDAT		(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif /* __SPI_S3C2410_H */