Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // RPC-IF SPI/QSPI/Octa driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (C) 2018 ~ 2019 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // Copyright (C) 2019 Macronix International Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // Copyright (C) 2019 - 2020 Cogent Embedded, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/spi/spi-mem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <memory/renesas-rpc-if.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static void rpcif_spi_mem_prepare(struct spi_device *spi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 				  const struct spi_mem_op *spi_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 				  u64 *offs, size_t *len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	struct rpcif *rpc = spi_controller_get_devdata(spi_dev->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	struct rpcif_op rpc_op = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	rpc_op.cmd.opcode = spi_op->cmd.opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	rpc_op.cmd.buswidth = spi_op->cmd.buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	if (spi_op->addr.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		rpc_op.addr.buswidth = spi_op->addr.buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		rpc_op.addr.nbytes = spi_op->addr.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		rpc_op.addr.val = spi_op->addr.val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	if (spi_op->dummy.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		rpc_op.dummy.buswidth = spi_op->dummy.buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		rpc_op.dummy.ncycles  = spi_op->dummy.nbytes * 8 /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 					spi_op->dummy.buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	if (spi_op->data.nbytes || (offs && len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		rpc_op.data.buswidth = spi_op->data.buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		rpc_op.data.nbytes = spi_op->data.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		switch (spi_op->data.dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		case SPI_MEM_DATA_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 			rpc_op.data.dir = RPCIF_DATA_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 			rpc_op.data.buf.in = spi_op->data.buf.in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		case SPI_MEM_DATA_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 			rpc_op.data.dir = RPCIF_DATA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			rpc_op.data.buf.out = spi_op->data.buf.out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		case SPI_MEM_NO_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			rpc_op.data.dir = RPCIF_NO_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	} else	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		rpc_op.data.dir = RPCIF_NO_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	rpcif_prepare(rpc, &rpc_op, offs, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static bool rpcif_spi_mem_supports_op(struct spi_mem *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 				      const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (!spi_mem_default_supports_op(mem, op))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (op->data.buswidth > 4 || op->addr.buswidth > 4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	    op->dummy.buswidth > 4 || op->cmd.buswidth > 4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	    op->addr.nbytes > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static ssize_t rpcif_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 					 u64 offs, size_t len, void *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct rpcif *rpc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		spi_controller_get_devdata(desc->mem->spi->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (offs + desc->info.offset + len > U32_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	rpcif_spi_mem_prepare(desc->mem->spi, &desc->info.op_tmpl, &offs, &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return rpcif_dirmap_read(rpc, offs, len, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static int rpcif_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct rpcif *rpc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		spi_controller_get_devdata(desc->mem->spi->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (desc->info.offset + desc->info.length > U32_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (!rpcif_spi_mem_supports_op(desc->mem, &desc->info.op_tmpl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	if (!rpc->dirmap && desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int rpcif_spi_mem_exec_op(struct spi_mem *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 				 const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct rpcif *rpc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		spi_controller_get_devdata(mem->spi->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	rpcif_spi_mem_prepare(mem->spi, op, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return rpcif_manual_xfer(rpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct spi_controller_mem_ops rpcif_spi_mem_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.supports_op	= rpcif_spi_mem_supports_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.exec_op	= rpcif_spi_mem_exec_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.dirmap_create	= rpcif_spi_mem_dirmap_create,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.dirmap_read	= rpcif_spi_mem_dirmap_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int rpcif_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct device *parent = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct rpcif *rpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*rpc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (!ctlr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	rpc = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	error = rpcif_sw_init(rpc, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	platform_set_drvdata(pdev, ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	ctlr->dev.of_node = parent->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	rpcif_enable_rpm(rpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	ctlr->num_chipselect = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	ctlr->mem_ops = &rpcif_spi_mem_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_QUAD | SPI_RX_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	rpcif_hw_init(rpc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	error = spi_register_controller(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		dev_err(&pdev->dev, "spi_register_controller failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		rpcif_disable_rpm(rpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int rpcif_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct spi_controller *ctlr = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct rpcif *rpc = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	spi_unregister_controller(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	rpcif_disable_rpm(rpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int rpcif_spi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct spi_controller *ctlr = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	return spi_controller_suspend(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int rpcif_spi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct spi_controller *ctlr = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	return spi_controller_resume(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static SIMPLE_DEV_PM_OPS(rpcif_spi_pm_ops, rpcif_spi_suspend, rpcif_spi_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DEV_PM_OPS	(&rpcif_spi_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define DEV_PM_OPS	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static struct platform_driver rpcif_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.probe	= rpcif_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.remove	= rpcif_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		.name	= "rpc-if-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		.pm	= DEV_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) module_platform_driver(rpcif_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MODULE_DESCRIPTION("Renesas RPC-IF SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MODULE_LICENSE("GPL v2");