Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * SPI controller driver for the Mikrotik RB4xx boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2015 Bert Vermeulen <bert@biot.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This file was based on the patches for Linux 2.6.27.39 published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * MikroTik for their RouterBoard 4xx series devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/mach-ath79/ar71xx_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) struct rb4xx_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static inline u32 rb4xx_read(struct rb4xx_spi *rbspi, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	return __raw_readl(rbspi->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static inline void rb4xx_write(struct rb4xx_spi *rbspi, u32 reg, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	__raw_writel(value, rbspi->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static inline void do_spi_clk(struct rb4xx_spi *rbspi, u32 spi_ioc, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	regval = spi_ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	if (value & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		regval |= AR71XX_SPI_IOC_DO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static void do_spi_byte(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	for (i = 7; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		do_spi_clk(rbspi, spi_ioc, byte >> i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* The CS2 pin is used to clock in a second bit per clock cycle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static inline void do_spi_clk_two(struct rb4xx_spi *rbspi, u32 spi_ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 				   u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	regval = spi_ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	if (value & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		regval |= AR71XX_SPI_IOC_DO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	if (value & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		regval |= AR71XX_SPI_IOC_CS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* Two bits at a time, msb first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static void do_spi_byte_two(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	do_spi_clk_two(rbspi, spi_ioc, byte >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	do_spi_clk_two(rbspi, spi_ioc, byte >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	do_spi_clk_two(rbspi, spi_ioc, byte >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	do_spi_clk_two(rbspi, spi_ioc, byte >> 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static void rb4xx_set_cs(struct spi_device *spi, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 * Setting CS is done along with bitbanging the actual values,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	 * since it's all on the same hardware register. However the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 * CPLD needs CS deselected after every command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		rb4xx_write(rbspi, AR71XX_SPI_REG_IOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			    AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static int rb4xx_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			      struct spi_device *spi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct rb4xx_spi *rbspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u32 spi_ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	u8 *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	const u8 *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 * Prime the SPI register with the SPI device selected. The m25p80 boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 * flash and CPLD share the CS0 pin. This works because the CPLD's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 * command set was designed to almost not clash with that of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 * boot flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (spi->chip_select == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		/* MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		spi_ioc = AR71XX_SPI_IOC_CS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		/* Boot flash and CPLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		spi_ioc = AR71XX_SPI_IOC_CS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	tx_buf = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	rx_buf = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	for (i = 0; i < t->len; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		if (t->tx_nbits == SPI_NBITS_DUAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			/* CPLD can use two-wire transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			do_spi_byte_two(rbspi, spi_ioc, tx_buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			do_spi_byte(rbspi, spi_ioc, tx_buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		if (!rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		rx_buf[i] = rb4xx_read(rbspi, AR71XX_SPI_REG_RDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	spi_finalize_current_transfer(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int rb4xx_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct clk *ahb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct rb4xx_spi *rbspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	void __iomem *spi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	spi_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (IS_ERR(spi_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		return PTR_ERR(spi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	master = devm_spi_alloc_master(&pdev->dev, sizeof(*rbspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	ahb_clk = devm_clk_get(&pdev->dev, "ahb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (IS_ERR(ahb_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return PTR_ERR(ahb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	master->bus_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	master->num_chipselect = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	master->mode_bits = SPI_TX_DUAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	master->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	master->flags = SPI_MASTER_MUST_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	master->transfer_one = rb4xx_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	master->set_cs = rb4xx_set_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	rbspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	rbspi->base = spi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	rbspi->clk = ahb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	platform_set_drvdata(pdev, rbspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	err = devm_spi_register_master(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		dev_err(&pdev->dev, "failed to register SPI master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	err = clk_prepare_enable(ahb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/* Enable SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	rb4xx_write(rbspi, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int rb4xx_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	clk_disable_unprepare(rbspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const struct of_device_id rb4xx_spi_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	{ .compatible = "mikrotik,rb4xx-spi" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MODULE_DEVICE_TABLE(of, rb4xx_spi_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static struct platform_driver rb4xx_spi_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.probe = rb4xx_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.remove = rb4xx_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		.name = "rb4xx-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.of_match_table = of_match_ptr(rb4xx_spi_dt_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) module_platform_driver(rb4xx_spi_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MODULE_DESCRIPTION("Mikrotik RB4xx SPI controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MODULE_LICENSE("GPL v2");