^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef SPI_PXA2XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define SPI_PXA2XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pxa2xx_ssp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spi/pxa2xx_spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct driver_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Driver model hookup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* SSP Info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct ssp_device *ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* SPI framework hookup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum pxa_ssp_type ssp_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct spi_controller *controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* PXA hookup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct pxa2xx_spi_controller *controller_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* SSP register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) phys_addr_t ssdr_physical;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* SSP masks*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 dma_cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 int_cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 clear_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 mask_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* DMA engine support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) atomic_t dma_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Current transfer state info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) void *tx_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void *rx_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 n_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int (*write)(struct driver_data *drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int (*read)(struct driver_data *drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void (*cs_control)(u32 command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void __iomem *lpss_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* GPIOs for chip selects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct gpio_desc **cs_gpiods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Optional slave FIFO ready signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct gpio_desc *gpiod_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 dds_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 n_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 dma_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 dma_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u16 lpss_rx_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u16 lpss_tx_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 enable_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct gpio_desc *gpiod_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int frm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int gpio_cs_inverted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int (*write)(struct driver_data *drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int (*read)(struct driver_data *drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void (*cs_control)(u32 command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return __raw_readl(drv_data->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static inline void pxa2xx_spi_write(const struct driver_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __raw_writel(val, drv_data->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DMA_ALIGNMENT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) switch (drv_data->ssp_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case PXA25x_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) case CE4100_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) case QUARK_X1000_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (drv_data->ssp_type == CE4100_SSP ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) drv_data->ssp_type == QUARK_X1000_SSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) val |= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pxa2xx_spi_write(drv_data, SSSR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) extern int pxa2xx_spi_flush(struct driver_data *drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MAX_DMA_LEN SZ_64K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct spi_transfer *xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) extern void pxa2xx_spi_dma_stop(struct driver_data *drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 bits_per_word,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 *burst_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 *threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #endif /* SPI_PXA2XX_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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