^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/spi/pxa2xx_spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "spi-pxa2xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_AUTHOR("Stephen Street");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MODULE_ALIAS("platform:pxa2xx-spi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TIMOUT_DFLT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * for testing SSCR1 changes that require SSP restart, basically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * everything except the service and interrupt enables, the pxa270 developer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * list, but the PXA255 dev man says all bits without really meaning the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * service and interrupt enables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) | QUARK_X1000_SSCR1_EFWR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) | QUARK_X1000_SSCR1_RFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) | QUARK_X1000_SSCR1_TFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define LPSS_CS_CONTROL_SW_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LPSS_CS_CONTROL_CS_HIGH BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LPSS_CAPS_CS_EN_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LPSS_PRIV_CLOCK_GATE 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct lpss_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* LPSS offset from drv_data->ioaddr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Register offsets from drv_data->lpss_base or -1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int reg_general;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int reg_ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int reg_cs_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int reg_capabilities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* FIFO thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 rx_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 tx_threshold_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 tx_threshold_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Chip select control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned cs_sel_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned cs_sel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned cs_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned cs_clk_stays_gated : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Keep these sorted with enum pxa_ssp_type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const struct lpss_config lpss_platforms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { /* LPSS_LPT_SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .offset = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .reg_general = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .reg_ssp = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .reg_cs_ctrl = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .reg_capabilities = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .rx_threshold = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .tx_threshold_lo = 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .tx_threshold_hi = 224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { /* LPSS_BYT_SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .offset = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .reg_general = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .reg_ssp = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .reg_cs_ctrl = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .reg_capabilities = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .rx_threshold = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .tx_threshold_lo = 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .tx_threshold_hi = 224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { /* LPSS_BSW_SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .offset = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .reg_general = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .reg_ssp = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .reg_cs_ctrl = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .reg_capabilities = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .rx_threshold = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .tx_threshold_lo = 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .tx_threshold_hi = 224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .cs_sel_shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .cs_sel_mask = 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .cs_num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { /* LPSS_SPT_SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .offset = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .reg_general = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .reg_ssp = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .reg_cs_ctrl = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .reg_capabilities = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .rx_threshold = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .tx_threshold_lo = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .tx_threshold_hi = 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { /* LPSS_BXT_SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .offset = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .reg_general = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .reg_ssp = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .reg_cs_ctrl = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .reg_capabilities = 0xfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .rx_threshold = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .tx_threshold_lo = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .tx_threshold_hi = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .cs_sel_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .cs_sel_mask = 3 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .cs_clk_stays_gated = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { /* LPSS_CNL_SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .offset = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .reg_general = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .reg_ssp = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .reg_cs_ctrl = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .reg_capabilities = 0xfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .rx_threshold = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .tx_threshold_lo = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .tx_threshold_hi = 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .cs_sel_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .cs_sel_mask = 3 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .cs_clk_stays_gated = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static inline const struct lpss_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *lpss_get_config(const struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static bool is_lpss_ssp(const struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) switch (drv_data->ssp_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) case LPSS_LPT_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case LPSS_BYT_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) case LPSS_BSW_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) case LPSS_SPT_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case LPSS_BXT_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case LPSS_CNL_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return drv_data->ssp_type == QUARK_X1000_SSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static bool is_mmp2_ssp(const struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return drv_data->ssp_type == MMP2_SSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) switch (drv_data->ssp_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) case QUARK_X1000_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return QUARK_X1000_SSCR1_CHANGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case CE4100_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return CE4100_SSCR1_CHANGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return SSCR1_CHANGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) switch (drv_data->ssp_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) case QUARK_X1000_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return RX_THRESH_QUARK_X1000_DFLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case CE4100_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return RX_THRESH_CE4100_DFLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return RX_THRESH_DFLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) switch (drv_data->ssp_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) case QUARK_X1000_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mask = QUARK_X1000_SSSR_TFL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case CE4100_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) mask = CE4100_SSSR_TFL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mask = SSSR_TFL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 *sccr1_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) switch (drv_data->ssp_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case QUARK_X1000_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) mask = QUARK_X1000_SSCR1_RFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case CE4100_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) mask = CE4100_SSCR1_RFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) mask = SSCR1_RFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *sccr1_reg &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 *sccr1_reg, u32 threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) switch (drv_data->ssp_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case QUARK_X1000_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case CE4100_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *sccr1_reg |= SSCR1_RxTresh(threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 clk_div, u8 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) switch (drv_data->ssp_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case QUARK_X1000_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return clk_div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) | QUARK_X1000_SSCR0_Motorola
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) | SSCR0_SSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return clk_div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) | SSCR0_Motorola
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) | SSCR0_SSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) | (bits > 16 ? SSCR0_EDSS : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * Read and write LPSS SSP private registers. Caller must first check that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * is_lpss_ssp() returns true before these can be called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) WARN_ON(!drv_data->lpss_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return readl(drv_data->lpss_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static void __lpss_ssp_write_priv(struct driver_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) WARN_ON(!drv_data->lpss_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) writel(value, drv_data->lpss_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * lpss_ssp_setup - perform LPSS SSP specific setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * @drv_data: pointer to the driver private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * Perform LPSS SSP specific setup. This function must be called first if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * one is going to use LPSS SSP private registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void lpss_ssp_setup(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) const struct lpss_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) config = lpss_get_config(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) drv_data->lpss_base = drv_data->ioaddr + config->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Enable software chip select control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Enable multiblock DMA transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (drv_data->controller_info->enable_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (config->reg_general >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) value = __lpss_ssp_read_priv(drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) config->reg_general);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) __lpss_ssp_write_priv(drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) config->reg_general, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static void lpss_ssp_select_cs(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) const struct lpss_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct driver_data *drv_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) spi_controller_get_devdata(spi->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u32 value, cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (!config->cs_sel_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) cs = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) cs <<= config->cs_sel_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (cs != (value & config->cs_sel_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * When switching another chip select output active the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * output must be selected first and wait 2 ssp_clk cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * before changing state to active. Otherwise a short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * glitch will occur on the previous chip select since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * output select is latched but state control is not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) value &= ~config->cs_sel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) value |= cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) __lpss_ssp_write_priv(drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) config->reg_cs_ctrl, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ndelay(1000000000 /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) (drv_data->controller->max_speed_hz / 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct driver_data *drv_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) spi_controller_get_devdata(spi->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) const struct lpss_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) config = lpss_get_config(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) lpss_ssp_select_cs(spi, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) value &= ~LPSS_CS_CONTROL_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) value |= LPSS_CS_CONTROL_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (config->cs_clk_stays_gated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u32 clkgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * Changing CS alone when dynamic clock gating is on won't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * actually flip CS at that time. This ruins SPI transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * that specify delays, or have no data. Toggle the clock mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * to force on briefly to poke the CS pin to move.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static void cs_assert(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct chip_data *chip = spi_get_ctldata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct driver_data *drv_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) spi_controller_get_devdata(spi->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (drv_data->ssp_type == CE4100_SSP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pxa2xx_spi_write(drv_data, SSSR, chip->frm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (chip->cs_control) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) chip->cs_control(PXA2XX_CS_ASSERT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (chip->gpiod_cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (is_lpss_ssp(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) lpss_ssp_cs_control(spi, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static void cs_deassert(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct chip_data *chip = spi_get_ctldata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct driver_data *drv_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) spi_controller_get_devdata(spi->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (drv_data->ssp_type == CE4100_SSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Wait until SSP becomes idle before deasserting the CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) timeout = jiffies + msecs_to_jiffies(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) !time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (chip->cs_control) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) chip->cs_control(PXA2XX_CS_DEASSERT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (chip->gpiod_cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (is_lpss_ssp(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) lpss_ssp_cs_control(spi, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) cs_deassert(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) cs_assert(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int pxa2xx_spi_flush(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unsigned long limit = loops_per_jiffy << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) pxa2xx_spi_read(drv_data, SSDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) write_SSSR_CS(drv_data, SSSR_ROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static void pxa2xx_spi_off(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* On MMP, disabling SSE seems to corrupt the Rx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (is_mmp2_ssp(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) pxa2xx_spi_write(drv_data, SSCR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static int null_writer(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u8 n_bytes = drv_data->n_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (pxa2xx_spi_txfifo_full(drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) || (drv_data->tx == drv_data->tx_end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) pxa2xx_spi_write(drv_data, SSDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) drv_data->tx += n_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static int null_reader(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u8 n_bytes = drv_data->n_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) && (drv_data->rx < drv_data->rx_end)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pxa2xx_spi_read(drv_data, SSDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) drv_data->rx += n_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return drv_data->rx == drv_data->rx_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int u8_writer(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (pxa2xx_spi_txfifo_full(drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) || (drv_data->tx == drv_data->tx_end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ++drv_data->tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static int u8_reader(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) && (drv_data->rx < drv_data->rx_end)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ++drv_data->rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return drv_data->rx == drv_data->rx_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int u16_writer(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (pxa2xx_spi_txfifo_full(drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) || (drv_data->tx == drv_data->tx_end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) drv_data->tx += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static int u16_reader(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) && (drv_data->rx < drv_data->rx_end)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) drv_data->rx += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return drv_data->rx == drv_data->rx_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static int u32_writer(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (pxa2xx_spi_txfifo_full(drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) || (drv_data->tx == drv_data->tx_end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) drv_data->tx += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static int u32_reader(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) && (drv_data->rx < drv_data->rx_end)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) drv_data->rx += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return drv_data->rx == drv_data->rx_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static void reset_sccr1(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct chip_data *chip =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) spi_get_ctldata(drv_data->controller->cur_msg->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u32 sccr1_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) switch (drv_data->ssp_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) case QUARK_X1000_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) case CE4100_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) sccr1_reg &= ~CE4100_SSCR1_RFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) sccr1_reg &= ~SSCR1_RFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) sccr1_reg |= chip->threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static void int_error_stop(struct driver_data *drv_data, const char* msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* Stop and reset SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) write_SSSR_CS(drv_data, drv_data->clear_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) reset_sccr1(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (!pxa25x_ssp_comp(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) pxa2xx_spi_write(drv_data, SSTO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) pxa2xx_spi_flush(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) pxa2xx_spi_off(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) dev_err(&drv_data->pdev->dev, "%s\n", msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) drv_data->controller->cur_msg->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) spi_finalize_current_transfer(drv_data->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static void int_transfer_complete(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Clear and disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) write_SSSR_CS(drv_data, drv_data->clear_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) reset_sccr1(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (!pxa25x_ssp_comp(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) pxa2xx_spi_write(drv_data, SSTO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) spi_finalize_current_transfer(drv_data->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (irq_status & SSSR_ROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (irq_status & SSSR_TUR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) int_error_stop(drv_data, "interrupt_transfer: fifo underrun");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (irq_status & SSSR_TINT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (drv_data->read(drv_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) int_transfer_complete(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Drain rx fifo, Fill tx fifo and prevent overruns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (drv_data->read(drv_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) int_transfer_complete(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) } while (drv_data->write(drv_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (drv_data->read(drv_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) int_transfer_complete(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (drv_data->tx == drv_data->tx_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u32 bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u32 sccr1_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) sccr1_reg &= ~SSCR1_TIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * PXA25x_SSP has no timeout, set up rx threshould for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * remaining RX bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (pxa25x_ssp_comp(drv_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u32 rx_thre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) bytes_left = drv_data->rx_end - drv_data->rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) switch (drv_data->n_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) bytes_left >>= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) bytes_left >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (rx_thre > bytes_left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) rx_thre = bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* We did something */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static void handle_bad_msg(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) pxa2xx_spi_off(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) pxa2xx_spi_write(drv_data, SSCR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (!pxa25x_ssp_comp(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) pxa2xx_spi_write(drv_data, SSTO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) write_SSSR_CS(drv_data, drv_data->clear_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) dev_err(&drv_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) "bad message state in interrupt handler\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static irqreturn_t ssp_int(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct driver_data *drv_data = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u32 sccr1_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u32 mask = drv_data->mask_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * The IRQ might be shared with other peripherals so we must first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * check that are we RPM suspended or not. If we are we assume that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * the IRQ was not for us (we shouldn't be RPM suspended when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * interrupt is enabled).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (pm_runtime_suspended(&drv_data->pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * If the device is not yet in RPM suspended state and we get an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * interrupt that is meant for another device, check if status bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * are all set to one. That means that the device is already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * powered off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) status = pxa2xx_spi_read(drv_data, SSSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (status == ~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* Ignore possible writes if we don't need to write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (!(sccr1_reg & SSCR1_TIE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) mask &= ~SSSR_TFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* Ignore RX timeout interrupt if it is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (!(sccr1_reg & SSCR1_TINTE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) mask &= ~SSSR_TINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (!(status & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (!drv_data->controller->cur_msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) handle_bad_msg(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* Never fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return drv_data->transfer_handler(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * input frequency by fractions of 2^24. It also has a divider by 5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * There are formulas to get baud rate value for given input frequency and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * divider parameters, such as DDS_CLK_RATE and SCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * Fsys = 200MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * DDS_CLK_RATE either 2^n or 2^n / 5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * SCR is in range 0 .. 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * Divisor = 5^i * 2^j * 2 * k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * i = [0, 1] i = 1 iff j = 0 or j > 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * j = [0, 23] j = 0 iff i = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * k = [1, 256]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * Special case: j = 0, i = 1: Divisor = 2 / 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * Accordingly to the specification the recommended values for DDS_CLK_RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * Case 1: 2^n, n = [0, 23]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * Case 2: 2^24 * 2 / 5 (0x666666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * In all cases the lowest possible value is better.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * The function calculates parameters for all cases and chooses the one closest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * to the asked baud rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) unsigned long xtal = 200000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) unsigned long fref = xtal / 2; /* mandatory division by 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) see (2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* case 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) unsigned long fref1 = fref / 2; /* case 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) unsigned long fref2 = fref * 2 / 5; /* case 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) unsigned long scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) unsigned long q, q1, q2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) long r, r1, r2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u32 mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* Case 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* Set initial value for DDS_CLK_RATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) mul = (1 << 24) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* Calculate initial quot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) q1 = DIV_ROUND_UP(fref1, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* Scale q1 if it's too big */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (q1 > 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* Scale q1 to range [1, 512] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) scale = fls_long(q1 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (scale > 9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) q1 >>= scale - 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) mul >>= scale - 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* Round the result if we have a remainder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) q1 += q1 & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) scale = __ffs(q1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) q1 >>= scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) mul >>= scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* Get the remainder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* Case 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) q2 = DIV_ROUND_UP(fref2, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) r2 = abs(fref2 / q2 - rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * Choose the best between two: less remainder we have the better. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * can't go case 2 if q2 is greater than 256 since SCR register can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * hold only values 0 .. 255.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (r2 >= r1 || q2 > 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* case 1 is better */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) r = r1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) q = q1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* case 2 is better */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) r = r2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) q = q2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) mul = (1 << 24) * 2 / 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* Check case 3 only if the divisor is big enough */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (fref / rate >= 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) u64 fssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) u32 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* Calculate initial quot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) q1 = DIV_ROUND_UP(fref, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) m = (1 << 24) / q1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* Get the remainder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) fssp = (u64)fref * m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) do_div(fssp, 1 << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) r1 = abs(fssp - rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* Choose this one if it suits better */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (r1 < r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* case 3 is better */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) q = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) mul = m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) *dds = mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return q - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) unsigned long ssp_clk = drv_data->controller->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) const struct ssp_device *ssp = drv_data->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) rate = min_t(int, ssp_clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * that the SSP transmission rate can be greater than the device rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct chip_data *chip =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) spi_get_ctldata(drv_data->controller->cur_msg->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) unsigned int clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) switch (drv_data->ssp_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) case QUARK_X1000_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) clk_div = ssp_get_clk_div(drv_data, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return clk_div << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct chip_data *chip = spi_get_ctldata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return chip->enable_dma &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) xfer->len <= MAX_DMA_LEN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) xfer->len >= chip->dma_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct spi_transfer *transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct driver_data *drv_data = spi_controller_get_devdata(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct spi_message *message = controller->cur_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct chip_data *chip = spi_get_ctldata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) u32 dma_thresh = chip->dma_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) u32 dma_burst = chip->dma_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) u32 clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) u8 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u32 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) u32 cr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) u32 cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) int dma_mapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* Check if we can DMA this transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* reject already-mapped transfers; PIO won't always work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (message->is_dma_mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) || transfer->rx_dma || transfer->tx_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) "Mapped transfer length of %u is greater than %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) transfer->len, MAX_DMA_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* warn ... we force this to PIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) dev_warn_ratelimited(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) "DMA disabled for transfer length %ld greater than %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) (long)transfer->len, MAX_DMA_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* Setup the transfer state based on the type of transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (pxa2xx_spi_flush(drv_data) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) dev_err(&spi->dev, "Flush failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) drv_data->n_bytes = chip->n_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) drv_data->tx = (void *)transfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) drv_data->tx_end = drv_data->tx + transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) drv_data->rx = transfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) drv_data->rx_end = drv_data->rx + transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) drv_data->write = drv_data->tx ? chip->write : null_writer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) drv_data->read = drv_data->rx ? chip->read : null_reader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* Change speed and bit per word on a per transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) bits = transfer->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) speed = transfer->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (bits <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) drv_data->n_bytes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) drv_data->read = drv_data->read != null_reader ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) u8_reader : null_reader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) drv_data->write = drv_data->write != null_writer ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) u8_writer : null_writer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) } else if (bits <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) drv_data->n_bytes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) drv_data->read = drv_data->read != null_reader ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) u16_reader : null_reader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) drv_data->write = drv_data->write != null_writer ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) u16_writer : null_writer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) } else if (bits <= 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) drv_data->n_bytes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) drv_data->read = drv_data->read != null_reader ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) u32_reader : null_reader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) drv_data->write = drv_data->write != null_writer ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) u32_writer : null_writer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * if bits/word is changed in dma mode, then must check the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * thresholds and burst also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (chip->enable_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) bits, &dma_burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) &dma_thresh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) dev_warn_ratelimited(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) "DMA burst size reduced to match bits_per_word\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) dma_mapped = controller->can_dma &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) controller->can_dma(controller, spi, transfer) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) controller->cur_msg_mapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (dma_mapped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* Ensure we have the correct interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) err = pxa2xx_spi_dma_prepare(drv_data, transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* Clear status and start DMA engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) pxa2xx_spi_dma_start(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* Ensure we have the correct interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) drv_data->transfer_handler = interrupt_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* Clear status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) write_SSSR_CS(drv_data, drv_data->clear_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* NOTE: PXA25x_SSP _could_ use external clocking ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (!pxa25x_ssp_comp(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) dev_dbg(&spi->dev, "%u Hz actual, %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) controller->max_speed_hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dma_mapped ? "DMA" : "PIO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) dev_dbg(&spi->dev, "%u Hz actual, %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) controller->max_speed_hz / 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) dma_mapped ? "DMA" : "PIO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (is_lpss_ssp(drv_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) != chip->lpss_rx_threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) pxa2xx_spi_write(drv_data, SSIRF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) chip->lpss_rx_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) != chip->lpss_tx_threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) pxa2xx_spi_write(drv_data, SSITF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) chip->lpss_tx_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (is_quark_x1000_ssp(drv_data) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /* see if we need to reload the config registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) != (cr1 & change_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* stop the SSP, and update the other bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (!is_mmp2_ssp(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (!pxa25x_ssp_comp(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /* first set CR1 without interrupt and service enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /* restart the SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) pxa2xx_spi_write(drv_data, SSCR0, cr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (!pxa25x_ssp_comp(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (is_mmp2_ssp(drv_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) & SSSR_TFL_MASK) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (tx_level) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /* On MMP2, flipping SSE doesn't to empty TXFIFO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) tx_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (tx_level > transfer->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) tx_level = transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) drv_data->tx += tx_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (spi_controller_is_slave(controller)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) while (drv_data->write(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (drv_data->gpiod_ready) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) gpiod_set_value(drv_data->gpiod_ready, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) gpiod_set_value(drv_data->gpiod_ready, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) * Release the data by enabling service requests and interrupts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * without changing any mode bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) pxa2xx_spi_write(drv_data, SSCR1, cr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct driver_data *drv_data = spi_controller_get_devdata(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) /* Stop and reset SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) write_SSSR_CS(drv_data, drv_data->clear_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) reset_sccr1(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (!pxa25x_ssp_comp(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) pxa2xx_spi_write(drv_data, SSTO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) pxa2xx_spi_flush(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) pxa2xx_spi_off(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) drv_data->controller->cur_msg->status = -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) spi_finalize_current_transfer(drv_data->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static void pxa2xx_spi_handle_err(struct spi_controller *controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct driver_data *drv_data = spi_controller_get_devdata(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /* Disable the SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) pxa2xx_spi_off(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /* Clear and disable interrupts and service requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) write_SSSR_CS(drv_data, drv_data->clear_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) pxa2xx_spi_write(drv_data, SSCR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) pxa2xx_spi_read(drv_data, SSCR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) & ~(drv_data->int_cr1 | drv_data->dma_cr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (!pxa25x_ssp_comp(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) pxa2xx_spi_write(drv_data, SSTO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) * Stop the DMA if running. Note DMA callback handler may have unset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * the dma_running already, which is fine as stopping is not needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * then but we shouldn't rely this flag for anything else than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * stopping. For instance to differentiate between PIO and DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (atomic_read(&drv_data->dma_running))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) pxa2xx_spi_dma_stop(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) struct driver_data *drv_data = spi_controller_get_devdata(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* Disable the SSP now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) pxa2xx_spi_off(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static int setup_cs(struct spi_device *spi, struct chip_data *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) struct pxa2xx_spi_chip *chip_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct driver_data *drv_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) spi_controller_get_devdata(spi->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct gpio_desc *gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (chip == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (drv_data->cs_gpiods) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) gpiod = drv_data->cs_gpiods[spi->chip_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (gpiod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) chip->gpiod_cs = gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) gpiod_set_value(gpiod, chip->gpio_cs_inverted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (chip_info == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* NOTE: setup() can be called multiple times, possibly with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * different chip_info, release previously requested GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (chip->gpiod_cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) gpiod_put(chip->gpiod_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) chip->gpiod_cs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /* If (*cs_control) is provided, ignore GPIO chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (chip_info->cs_control) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) chip->cs_control = chip_info->cs_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (gpio_is_valid(chip_info->gpio_cs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) err = gpio_request(chip_info->gpio_cs, "SPI_CS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) chip_info->gpio_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) gpiod = gpio_to_desc(chip_info->gpio_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) chip->gpiod_cs = gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) gpiod_put(chip->gpiod_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static int setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) struct pxa2xx_spi_chip *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct chip_data *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) const struct lpss_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) struct driver_data *drv_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) spi_controller_get_devdata(spi->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) uint tx_thres, tx_hi_thres, rx_thres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) switch (drv_data->ssp_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) case QUARK_X1000_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) tx_thres = TX_THRESH_QUARK_X1000_DFLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) tx_hi_thres = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) rx_thres = RX_THRESH_QUARK_X1000_DFLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) case CE4100_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) tx_thres = TX_THRESH_CE4100_DFLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) tx_hi_thres = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) rx_thres = RX_THRESH_CE4100_DFLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) case LPSS_LPT_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) case LPSS_BYT_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) case LPSS_BSW_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) case LPSS_SPT_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) case LPSS_BXT_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) case LPSS_CNL_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) config = lpss_get_config(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) tx_thres = config->tx_threshold_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) tx_hi_thres = config->tx_threshold_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) rx_thres = config->rx_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) tx_hi_thres = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (spi_controller_is_slave(drv_data->controller)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) tx_thres = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) rx_thres = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) tx_thres = TX_THRESH_DFLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) rx_thres = RX_THRESH_DFLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /* Only alloc on first setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) chip = spi_get_ctldata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (!chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (drv_data->ssp_type == CE4100_SSP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (spi->chip_select > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) "failed setup: cs number must not be > 4.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) chip->frm = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) chip->enable_dma = drv_data->controller_info->enable_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) chip->timeout = TIMOUT_DFLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) /* protocol drivers may change the chip settings, so...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * if chip_info exists, use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) chip_info = spi->controller_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /* chip_info isn't always needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) chip->cr1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (chip_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (chip_info->timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) chip->timeout = chip_info->timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (chip_info->tx_threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) tx_thres = chip_info->tx_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (chip_info->tx_hi_threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) tx_hi_thres = chip_info->tx_hi_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (chip_info->rx_threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) rx_thres = chip_info->rx_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) chip->dma_threshold = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (chip_info->enable_loopback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) chip->cr1 = SSCR1_LBM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (spi_controller_is_slave(drv_data->controller)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) chip->cr1 |= SSCR1_SCFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) chip->cr1 |= SSCR1_SCLKDIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) chip->cr1 |= SSCR1_SFRMDIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) chip->cr1 |= SSCR1_SPH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) | SSITF_TxHiThresh(tx_hi_thres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /* set dma burst and threshold outside of chip_info path so that if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * chip_info goes away after setting chip->enable_dma, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * burst and threshold can still respond to changes in bits_per_word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (chip->enable_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) /* set up legal burst and threshold for dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) spi->bits_per_word,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) &chip->dma_burst_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) &chip->dma_threshold)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) dev_warn(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) "in setup: DMA burst size reduced to match bits_per_word\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) dev_dbg(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) "in setup: DMA burst size set to %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) chip->dma_burst_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) switch (drv_data->ssp_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) case QUARK_X1000_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) & QUARK_X1000_SSCR1_RFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) & QUARK_X1000_SSCR1_TFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) case CE4100_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (spi->mode & SPI_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) chip->cr1 |= SSCR1_LBM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (spi->bits_per_word <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) chip->n_bytes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) chip->read = u8_reader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) chip->write = u8_writer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) } else if (spi->bits_per_word <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) chip->n_bytes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) chip->read = u16_reader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) chip->write = u16_writer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) } else if (spi->bits_per_word <= 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) chip->n_bytes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) chip->read = u32_reader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) chip->write = u32_writer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) spi_set_ctldata(spi, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (drv_data->ssp_type == CE4100_SSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) err = setup_cs(spi, chip, chip_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static void cleanup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) struct chip_data *chip = spi_get_ctldata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) struct driver_data *drv_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) spi_controller_get_devdata(spi->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) chip->gpiod_cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) gpiod_put(chip->gpiod_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) { "INT33C0", LPSS_LPT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) { "INT33C1", LPSS_LPT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) { "INT3430", LPSS_LPT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) { "INT3431", LPSS_LPT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) { "80860F0E", LPSS_BYT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) { "8086228E", LPSS_BSW_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) * PCI IDs of compound devices that integrate both host controller and private
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) * integrated DMA engine. Please note these are not used in module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * autoloading and probing in this module but matching the LPSS SSP type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) /* SPT-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* SPT-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* KBL-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) /* CML-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) { PCI_VDEVICE(INTEL, 0xa3a9), LPSS_SPT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) { PCI_VDEVICE(INTEL, 0xa3aa), LPSS_SPT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /* BXT A-Step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) /* BXT B-Step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /* GLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) /* ICL-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) /* EHL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) { PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) { PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) { PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) /* JSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) { PCI_VDEVICE(INTEL, 0x4daa), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) { PCI_VDEVICE(INTEL, 0x4dab), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) { PCI_VDEVICE(INTEL, 0x4dfb), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) /* TGL-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) { PCI_VDEVICE(INTEL, 0x43aa), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) { PCI_VDEVICE(INTEL, 0x43ab), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) { PCI_VDEVICE(INTEL, 0x43fb), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) { PCI_VDEVICE(INTEL, 0x43fd), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /* APL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) /* CNL-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) /* CNL-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) /* CML-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /* CML-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) { PCI_VDEVICE(INTEL, 0x06aa), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) { PCI_VDEVICE(INTEL, 0x06ab), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) { PCI_VDEVICE(INTEL, 0x06fb), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* TGL-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) { PCI_VDEVICE(INTEL, 0xa0aa), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) { PCI_VDEVICE(INTEL, 0xa0ab), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) { PCI_VDEVICE(INTEL, 0xa0de), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) { PCI_VDEVICE(INTEL, 0xa0df), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) { PCI_VDEVICE(INTEL, 0xa0fb), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) { PCI_VDEVICE(INTEL, 0xa0fd), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) { PCI_VDEVICE(INTEL, 0xa0fe), LPSS_CNL_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) static const struct of_device_id pxa2xx_spi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) static int pxa2xx_spi_get_port_id(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) struct acpi_device *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) unsigned int devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) int port_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) adev = ACPI_COMPANION(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) if (adev && adev->pnp.unique_id &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) !kstrtouint(adev->pnp.unique_id, 0, &devid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) port_id = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) return port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) #else /* !CONFIG_ACPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) static int pxa2xx_spi_get_port_id(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) #endif /* CONFIG_ACPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) return param == chan->device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) static struct pxa2xx_spi_controller *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) pxa2xx_spi_init_pdata(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) struct pxa2xx_spi_controller *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) struct ssp_device *ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) struct device *parent = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) struct pci_dev *pcidev = dev_is_pci(parent) ? to_pci_dev(parent) : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) const struct pci_device_id *pcidev_id = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) enum pxa_ssp_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) const void *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (pcidev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) match = device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) type = (enum pxa_ssp_type)match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) else if (pcidev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) type = (enum pxa_ssp_type)pcidev_id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) ssp = &pdata->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (IS_ERR(ssp->mmio_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) return ERR_CAST(ssp->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) ssp->phys_base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) if (pcidev_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) pdata->tx_param = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) pdata->rx_param = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) pdata->dma_filter = pxa2xx_spi_idma_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) ssp->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (IS_ERR(ssp->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) return ERR_CAST(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) ssp->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) if (ssp->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) return ERR_PTR(ssp->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) ssp->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) ssp->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) ssp->port_id = pxa2xx_spi_get_port_id(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) pdata->is_slave = device_property_read_bool(&pdev->dev, "spi-slave");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) pdata->num_chipselect = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) pdata->enable_dma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) pdata->dma_burst_size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) unsigned int cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) struct driver_data *drv_data = spi_controller_get_devdata(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (has_acpi_companion(&drv_data->pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) switch (drv_data->ssp_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) * For Atoms the ACPI DeviceSelection used by the Windows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) * driver starts from 1 instead of 0 so translate it here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) * to match what Linux expects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) case LPSS_BYT_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) case LPSS_BSW_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) return cs - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) return cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) return MAX_DMA_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) static int pxa2xx_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) struct pxa2xx_spi_controller *platform_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) struct spi_controller *controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) struct driver_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) struct ssp_device *ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) const struct lpss_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) int status, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) platform_info = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) if (!platform_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) platform_info = pxa2xx_spi_init_pdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (IS_ERR(platform_info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) dev_err(&pdev->dev, "missing platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) return PTR_ERR(platform_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) ssp = pxa_ssp_request(pdev->id, pdev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) if (!ssp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) ssp = &platform_info->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if (!ssp->mmio_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) dev_err(&pdev->dev, "failed to get ssp\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if (platform_info->is_slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) controller = devm_spi_alloc_slave(dev, sizeof(*drv_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) controller = devm_spi_alloc_master(dev, sizeof(*drv_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (!controller) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) dev_err(&pdev->dev, "cannot alloc spi_controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) pxa_ssp_free(ssp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) drv_data = spi_controller_get_devdata(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) drv_data->controller = controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) drv_data->controller_info = platform_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) drv_data->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) drv_data->ssp = ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) controller->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /* the spi->mode bits understood by this driver: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) controller->bus_num = ssp->port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) controller->dma_alignment = DMA_ALIGNMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) controller->cleanup = cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) controller->setup = setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) controller->set_cs = pxa2xx_spi_set_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) controller->transfer_one = pxa2xx_spi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) controller->slave_abort = pxa2xx_spi_slave_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) controller->handle_err = pxa2xx_spi_handle_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) controller->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) drv_data->ssp_type = ssp->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) drv_data->ioaddr = ssp->mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) drv_data->ssdr_physical = ssp->phys_base + SSDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if (pxa25x_ssp_comp(drv_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) switch (drv_data->ssp_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) case QUARK_X1000_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) drv_data->dma_cr1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) drv_data->clear_sr = SSSR_ROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) drv_data->dma_cr1 = DEFAULT_DMA_CR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) | SSSR_ROR | SSSR_TUR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) goto out_error_controller_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) /* Setup DMA if requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (platform_info->enable_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) status = pxa2xx_spi_dma_setup(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) dev_warn(dev, "no DMA channels available, using PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) platform_info->enable_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) controller->can_dma = pxa2xx_spi_can_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) controller->max_dma_len = MAX_DMA_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) controller->max_transfer_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) pxa2xx_spi_max_dma_transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) /* Enable SOC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) status = clk_prepare_enable(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) goto out_error_dma_irq_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) controller->max_speed_hz = clk_get_rate(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) * Set minimum speed for all other platforms than Intel Quark which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) * able do under 1 Hz transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) if (!pxa25x_ssp_comp(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) controller->min_speed_hz =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) DIV_ROUND_UP(controller->max_speed_hz, 4096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) else if (!is_quark_x1000_ssp(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) controller->min_speed_hz =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) DIV_ROUND_UP(controller->max_speed_hz, 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) /* Load default SSP configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) pxa2xx_spi_write(drv_data, SSCR0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) switch (drv_data->ssp_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) case QUARK_X1000_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) pxa2xx_spi_write(drv_data, SSCR1, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) /* using the Motorola SPI protocol and use 8 bit frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) pxa2xx_spi_write(drv_data, SSCR0, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) case CE4100_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) pxa2xx_spi_write(drv_data, SSCR1, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) pxa2xx_spi_write(drv_data, SSCR0, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) if (spi_controller_is_slave(controller)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) tmp = SSCR1_SCFR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) SSCR1_SCLKDIR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) SSCR1_SFRMDIR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) SSCR1_RxTresh(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) SSCR1_TxTresh(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) SSCR1_SPH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) SSCR1_TxTresh(TX_THRESH_DFLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) pxa2xx_spi_write(drv_data, SSCR1, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) tmp = SSCR0_Motorola | SSCR0_DataSize(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (!spi_controller_is_slave(controller))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) tmp |= SSCR0_SCR(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) pxa2xx_spi_write(drv_data, SSCR0, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) if (!pxa25x_ssp_comp(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) pxa2xx_spi_write(drv_data, SSTO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if (!is_quark_x1000_ssp(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) pxa2xx_spi_write(drv_data, SSPSP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) if (is_lpss_ssp(drv_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) lpss_ssp_setup(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) config = lpss_get_config(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (config->reg_capabilities >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) tmp = __lpss_ssp_read_priv(drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) config->reg_capabilities);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) tmp &= LPSS_CAPS_CS_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) tmp >>= LPSS_CAPS_CS_EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) platform_info->num_chipselect = ffz(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) } else if (config->cs_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) platform_info->num_chipselect = config->cs_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) controller->num_chipselect = platform_info->num_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) count = gpiod_count(&pdev->dev, "cs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) if (count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) controller->num_chipselect = max_t(int, count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) controller->num_chipselect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) controller->num_chipselect, sizeof(struct gpio_desc *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) if (!drv_data->cs_gpiods) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) status = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) goto out_error_clock_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) for (i = 0; i < controller->num_chipselect; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) struct gpio_desc *gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) if (IS_ERR(gpiod)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) /* Means use native chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (PTR_ERR(gpiod) == -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) status = PTR_ERR(gpiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) goto out_error_clock_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) drv_data->cs_gpiods[i] = gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (platform_info->is_slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) "ready", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (IS_ERR(drv_data->gpiod_ready)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) status = PTR_ERR(drv_data->gpiod_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) goto out_error_clock_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) /* Register with the SPI framework */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) platform_set_drvdata(pdev, drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) status = spi_register_controller(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) if (status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) dev_err(&pdev->dev, "problem registering spi controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) goto out_error_pm_runtime_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) out_error_pm_runtime_enabled:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) out_error_clock_enabled:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) clk_disable_unprepare(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) out_error_dma_irq_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) pxa2xx_spi_dma_release(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) free_irq(ssp->irq, drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) out_error_controller_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) pxa_ssp_free(ssp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) static int pxa2xx_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) struct driver_data *drv_data = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) struct ssp_device *ssp = drv_data->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) spi_unregister_controller(drv_data->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) /* Disable the SSP at the peripheral and SOC level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) pxa2xx_spi_write(drv_data, SSCR0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) clk_disable_unprepare(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) /* Release DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) if (drv_data->controller_info->enable_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) pxa2xx_spi_dma_release(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) /* Release IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) free_irq(ssp->irq, drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) /* Release SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) pxa_ssp_free(ssp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) static int pxa2xx_spi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) struct driver_data *drv_data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) struct ssp_device *ssp = drv_data->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) status = spi_controller_suspend(drv_data->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (status != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) pxa2xx_spi_write(drv_data, SSCR0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) if (!pm_runtime_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) clk_disable_unprepare(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) static int pxa2xx_spi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) struct driver_data *drv_data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) struct ssp_device *ssp = drv_data->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) /* Enable the SSP clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) if (!pm_runtime_suspended(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) status = clk_prepare_enable(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) /* Start the queue running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) return spi_controller_resume(drv_data->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) static int pxa2xx_spi_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) struct driver_data *drv_data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) clk_disable_unprepare(drv_data->ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) static int pxa2xx_spi_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) struct driver_data *drv_data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) status = clk_prepare_enable(drv_data->ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) pxa2xx_spi_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) static struct platform_driver driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .name = "pxa2xx-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .pm = &pxa2xx_spi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .of_match_table = of_match_ptr(pxa2xx_spi_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .probe = pxa2xx_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .remove = pxa2xx_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) static int __init pxa2xx_spi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) return platform_driver_register(&driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) subsys_initcall(pxa2xx_spi_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) static void __exit pxa2xx_spi_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) platform_driver_unregister(&driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) module_exit(pxa2xx_spi_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) MODULE_SOFTDEP("pre: dw_dmac");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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