Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * CE4100's SPI device is more or less the same one as found on PXA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2016, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/spi/pxa2xx_spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_data/dma-dw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	PORT_QUARK_X1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	PORT_BYT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	PORT_MRFLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	PORT_BSW0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	PORT_BSW1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	PORT_BSW2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	PORT_CE4100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	PORT_LPT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	PORT_LPT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) struct pxa_spi_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	enum pxa_ssp_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	int port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	int num_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	unsigned long max_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	/* DMA channel request parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	bool (*dma_filter)(struct dma_chan *chan, void *param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	void *tx_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	void *rx_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	int dma_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	int (*setup)(struct pci_dev *pdev, struct pxa_spi_info *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static struct dw_dma_slave byt_tx_param = { .dst_id = 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static struct dw_dma_slave byt_rx_param = { .src_id = 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static struct dw_dma_slave mrfld3_tx_param = { .dst_id = 15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static struct dw_dma_slave mrfld3_rx_param = { .src_id = 14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static struct dw_dma_slave mrfld5_tx_param = { .dst_id = 13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static struct dw_dma_slave mrfld5_rx_param = { .src_id = 12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static struct dw_dma_slave mrfld6_tx_param = { .dst_id = 11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static struct dw_dma_slave mrfld6_rx_param = { .src_id = 10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static struct dw_dma_slave bsw0_tx_param = { .dst_id = 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static struct dw_dma_slave bsw0_rx_param = { .src_id = 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static struct dw_dma_slave bsw1_tx_param = { .dst_id = 6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static struct dw_dma_slave bsw1_rx_param = { .src_id = 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static struct dw_dma_slave bsw2_tx_param = { .dst_id = 8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static struct dw_dma_slave bsw2_rx_param = { .src_id = 9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static struct dw_dma_slave lpt1_tx_param = { .dst_id = 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static struct dw_dma_slave lpt1_rx_param = { .src_id = 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static struct dw_dma_slave lpt0_tx_param = { .dst_id = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static struct dw_dma_slave lpt0_rx_param = { .src_id = 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static bool lpss_dma_filter(struct dma_chan *chan, void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct dw_dma_slave *dws = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (dws->dma_dev != chan->device->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	chan->private = dws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static void lpss_dma_put_device(void *dma_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	pci_dev_put(dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static int lpss_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct pci_dev *dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	c->num_chipselect = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	c->max_clk_rate = 50000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	ret = devm_add_action_or_reset(&dev->dev, lpss_dma_put_device, dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	if (c->tx_param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		struct dw_dma_slave *slave = c->tx_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		slave->dma_dev = &dma_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		slave->m_master = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		slave->p_master = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	if (c->rx_param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		struct dw_dma_slave *slave = c->rx_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		slave->dma_dev = &dma_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		slave->m_master = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		slave->p_master = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	c->dma_filter = lpss_dma_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int mrfld_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct dw_dma_slave *tx, *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct pci_dev *dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	switch (PCI_FUNC(dev->devfn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		c->port_id = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		c->num_chipselect = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		c->tx_param = &mrfld3_tx_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		c->rx_param = &mrfld3_rx_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		c->port_id = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		c->num_chipselect = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		c->tx_param = &mrfld5_tx_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		c->rx_param = &mrfld5_rx_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		c->port_id = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		c->num_chipselect = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		c->tx_param = &mrfld6_tx_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		c->rx_param = &mrfld6_rx_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(21, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ret = devm_add_action_or_reset(&dev->dev, lpss_dma_put_device, dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	tx = c->tx_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	tx->dma_dev = &dma_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	rx = c->rx_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	rx->dma_dev = &dma_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	c->dma_filter = lpss_dma_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	c->dma_burst_size = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static struct pxa_spi_info spi_info_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	[PORT_CE4100] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		.type = PXA25x_SSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		.port_id =  -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		.num_chipselect = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		.max_clk_rate = 3686400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	[PORT_BYT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		.type = LPSS_BYT_SSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.port_id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.setup = lpss_spi_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		.tx_param = &byt_tx_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		.rx_param = &byt_rx_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	[PORT_BSW0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		.type = LPSS_BSW_SSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		.port_id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		.setup = lpss_spi_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		.tx_param = &bsw0_tx_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		.rx_param = &bsw0_rx_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	[PORT_BSW1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		.type = LPSS_BSW_SSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		.port_id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		.setup = lpss_spi_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		.tx_param = &bsw1_tx_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		.rx_param = &bsw1_rx_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	[PORT_BSW2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.type = LPSS_BSW_SSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		.port_id = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		.setup = lpss_spi_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		.tx_param = &bsw2_tx_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		.rx_param = &bsw2_rx_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	[PORT_MRFLD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.type = PXA27x_SSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.max_clk_rate = 25000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		.setup = mrfld_spi_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	[PORT_QUARK_X1000] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		.type = QUARK_X1000_SSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		.port_id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		.num_chipselect = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.max_clk_rate = 50000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	[PORT_LPT0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		.type = LPSS_LPT_SSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		.port_id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.setup = lpss_spi_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.tx_param = &lpt0_tx_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		.rx_param = &lpt0_rx_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	[PORT_LPT1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		.type = LPSS_LPT_SSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		.port_id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		.setup = lpss_spi_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		.tx_param = &lpt1_tx_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		.rx_param = &lpt1_rx_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int pxa2xx_spi_pci_probe(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct platform_device_info pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	struct pxa2xx_spi_controller spi_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct ssp_device *ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct pxa_spi_info *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	char buf[40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	ret = pcim_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	ret = pcim_iomap_regions(dev, 1 << 0, "PXA2xx SPI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	c = &spi_info_configs[ent->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (c->setup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		ret = c->setup(dev, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	memset(&spi_pdata, 0, sizeof(spi_pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	spi_pdata.num_chipselect = (c->num_chipselect > 0) ? c->num_chipselect : dev->devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	spi_pdata.dma_filter = c->dma_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	spi_pdata.tx_param = c->tx_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	spi_pdata.rx_param = c->rx_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	spi_pdata.enable_dma = c->rx_param && c->tx_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	spi_pdata.dma_burst_size = c->dma_burst_size ? c->dma_burst_size : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	ssp = &spi_pdata.ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	ssp->phys_base = pci_resource_start(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	ssp->mmio_base = pcim_iomap_table(dev)[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	ssp->port_id = (c->port_id >= 0) ? c->port_id : dev->devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	ssp->type = c->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	pci_set_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	ret = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	ssp->irq = pci_irq_vector(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	snprintf(buf, sizeof(buf), "pxa2xx-spi.%d", ssp->port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	ssp->clk = clk_register_fixed_rate(&dev->dev, buf , NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 					   c->max_clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	 if (IS_ERR(ssp->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		return PTR_ERR(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	memset(&pi, 0, sizeof(pi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	pi.fwnode = dev->dev.fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	pi.parent = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	pi.name = "pxa2xx-spi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	pi.id = ssp->port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	pi.data = &spi_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	pi.size_data = sizeof(spi_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	pdev = platform_device_register_full(&pi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (IS_ERR(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		clk_unregister(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		return PTR_ERR(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	pci_set_drvdata(dev, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void pxa2xx_spi_pci_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	struct platform_device *pdev = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	struct pxa2xx_spi_controller *spi_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	spi_pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	platform_device_unregister(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	clk_unregister(spi_pdata->ssp.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static const struct pci_device_id pxa2xx_spi_pci_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	{ PCI_VDEVICE(INTEL, 0x0935), PORT_QUARK_X1000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	{ PCI_VDEVICE(INTEL, 0x0f0e), PORT_BYT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	{ PCI_VDEVICE(INTEL, 0x1194), PORT_MRFLD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	{ PCI_VDEVICE(INTEL, 0x228e), PORT_BSW0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	{ PCI_VDEVICE(INTEL, 0x2290), PORT_BSW1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	{ PCI_VDEVICE(INTEL, 0x22ac), PORT_BSW2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	{ PCI_VDEVICE(INTEL, 0x2e6a), PORT_CE4100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	{ PCI_VDEVICE(INTEL, 0x9ce5), PORT_LPT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	{ PCI_VDEVICE(INTEL, 0x9ce6), PORT_LPT1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_DEVICE_TABLE(pci, pxa2xx_spi_pci_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct pci_driver pxa2xx_spi_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.name           = "pxa2xx_spi_pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.id_table       = pxa2xx_spi_pci_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.probe          = pxa2xx_spi_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.remove         = pxa2xx_spi_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) module_pci_driver(pxa2xx_spi_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MODULE_DESCRIPTION("CE4100/LPSS PCI-SPI glue code for PXA's driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>");