Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * PXA2xx SPI DMA engine support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/pxa2xx_ssp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/spi/pxa2xx_spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "spi-pxa2xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 					     bool error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	struct spi_message *msg = drv_data->controller->cur_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	 * It is possible that one CPU is handling ROR interrupt and other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	 * just gets DMA completion. Calling pump_transfers() twice for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	 * same transfer leads to problems thus we prevent concurrent calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	 * by using ->dma_running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	if (atomic_dec_and_test(&drv_data->dma_running)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		 * If the other CPU is still handling the ROR interrupt we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		 * might not know about the error yet. So we re-check the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		 * ROR bit here before we clear the status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		if (!error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 			u32 status = pxa2xx_spi_read(drv_data, SSSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 				     & drv_data->mask_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 			error = status & SSSR_ROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		/* Clear status & disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		pxa2xx_spi_write(drv_data, SSCR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 				 pxa2xx_spi_read(drv_data, SSCR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 				 & ~drv_data->dma_cr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		write_SSSR_CS(drv_data, drv_data->clear_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		if (!pxa25x_ssp_comp(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			pxa2xx_spi_write(drv_data, SSTO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			/* In case we got an error we disable the SSP now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			pxa2xx_spi_write(drv_data, SSCR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 					 pxa2xx_spi_read(drv_data, SSCR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 					 & ~SSCR0_SSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			msg->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		spi_finalize_current_transfer(drv_data->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static void pxa2xx_spi_dma_callback(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	pxa2xx_spi_dma_transfer_complete(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			   enum dma_transfer_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			   struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct chip_data *chip =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		spi_get_ctldata(drv_data->controller->cur_msg->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	enum dma_slave_buswidth width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct dma_slave_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct sg_table *sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	switch (drv_data->n_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		width = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	memset(&cfg, 0, sizeof(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	cfg.direction = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (dir == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		cfg.dst_addr = drv_data->ssdr_physical;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		cfg.dst_addr_width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		cfg.dst_maxburst = chip->dma_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		sgt = &xfer->tx_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		chan = drv_data->controller->dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		cfg.src_addr = drv_data->ssdr_physical;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		cfg.src_addr_width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		cfg.src_maxburst = chip->dma_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		sgt = &xfer->rx_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		chan = drv_data->controller->dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	ret = dmaengine_slave_config(chan, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		dev_warn(&drv_data->pdev->dev, "DMA slave config failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	return dmaengine_prep_slave_sg(chan, sgt->sgl, sgt->nents, dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 				       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	status = pxa2xx_spi_read(drv_data, SSSR) & drv_data->mask_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (status & SSSR_ROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		dev_err(&drv_data->pdev->dev, "FIFO overrun\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		dmaengine_terminate_async(drv_data->controller->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		dmaengine_terminate_async(drv_data->controller->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		pxa2xx_spi_dma_transfer_complete(drv_data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			   struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct dma_async_tx_descriptor *tx_desc, *rx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	tx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_MEM_TO_DEV, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (!tx_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		dev_err(&drv_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			"failed to get DMA TX descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		goto err_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	rx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_DEV_TO_MEM, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (!rx_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		dev_err(&drv_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			"failed to get DMA RX descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		goto err_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/* We are ready when RX completes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	rx_desc->callback = pxa2xx_spi_dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	rx_desc->callback_param = drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	dmaengine_submit(rx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	dmaengine_submit(tx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) err_rx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	dmaengine_terminate_async(drv_data->controller->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) err_tx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) void pxa2xx_spi_dma_start(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	dma_async_issue_pending(drv_data->controller->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	dma_async_issue_pending(drv_data->controller->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	atomic_set(&drv_data->dma_running, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) void pxa2xx_spi_dma_stop(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	atomic_set(&drv_data->dma_running, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	dmaengine_terminate_sync(drv_data->controller->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	dmaengine_terminate_sync(drv_data->controller->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct pxa2xx_spi_controller *pdata = drv_data->controller_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct device *dev = &drv_data->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct spi_controller *controller = drv_data->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	dma_cap_set(DMA_SLAVE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	controller->dma_tx = dma_request_slave_channel_compat(mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				pdata->dma_filter, pdata->tx_param, dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (!controller->dma_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	controller->dma_rx = dma_request_slave_channel_compat(mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 				pdata->dma_filter, pdata->rx_param, dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (!controller->dma_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		dma_release_channel(controller->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		controller->dma_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) void pxa2xx_spi_dma_release(struct driver_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	struct spi_controller *controller = drv_data->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (controller->dma_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		dmaengine_terminate_sync(controller->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		dma_release_channel(controller->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		controller->dma_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (controller->dma_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		dmaengine_terminate_sync(controller->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		dma_release_channel(controller->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		controller->dma_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 					   struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 					   u8 bits_per_word, u32 *burst_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 					   u32 *threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	struct pxa2xx_spi_chip *chip_info = spi->controller_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	struct driver_data *drv_data = spi_controller_get_devdata(spi->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	u32 dma_burst_size = drv_data->controller_info->dma_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	 * If the DMA burst size is given in chip_info we use that,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	 * otherwise we use the default. Also we use the default FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 * thresholds for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	*burst_code = chip_info ? chip_info->dma_burst_size : dma_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	*threshold = SSCR1_RxTresh(RX_THRESH_DFLT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		   | SSCR1_TxTresh(TX_THRESH_DFLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }