^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SPI_PPC4XX SPI controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based in part on drivers/spi/spi_s3c24xx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (c) 2006 Ben Dooks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (c) 2006 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * The PPC4xx SPI controller has no FIFO so each sent/received byte will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * generate an interrupt to the CPU. This can cause high CPU utilization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * This driver allows platforms to reduce the interrupt load on the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * during SPI transfers by setting max_speed_hz via the device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/spi/spi_bitbang.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/dcr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/dcr-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* bits in mode register - bit 0 is MSb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Note: This is the inverse of CPHA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPI_PPC4XX_MODE_SCP (0x80 >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPI_PPC4XX_MODE_SPE (0x80 >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Note: This is identical to SPI_LSB_FIRST.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPI_PPC4XX_MODE_RD (0x80 >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Note: This is identical to CPOL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPI_PPC4XX_MODE_CI (0x80 >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SPI_PPC4XX_MODE_IL (0x80 >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* bits in control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* starts a transfer when set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SPI_PPC4XX_CR_STR (0x80 >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* bits in status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* port is busy with a transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SPI_PPC4XX_SR_BSY (0x80 >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* RxD ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SPI_PPC4XX_SR_RBR (0x80 >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* clock settings (SCP and CI) for various SPI modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SPI_CLK_MODE1 (0 | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SPI_CLK_MODE3 (0 | SPI_PPC4XX_MODE_CI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DRIVER_NAME "spi_ppc4xx_of"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct spi_ppc4xx_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 rxd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u8 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Clock divisor modulus register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * This uses the following formula:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * SCPClkOut = OPBCLK/(4(CDM + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * CDM = (OPBCLK/4*SCPClkOut) - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * bit 0 is the MSb!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 cdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* SPI Controller driver's private data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct ppc4xx_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* bitbang has to be first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct spi_bitbang bitbang;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u64 mapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u64 mapsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int irqnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* need this to set the SPI clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int opb_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* for transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* data buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const unsigned char *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned char *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* need this so we can set the clock in the chipselect routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct spi_ppc4xx_cs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct ppc4xx_spi *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) t->tx_buf, t->rx_buf, t->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) hw = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) hw->tx = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) hw->rx = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) hw->len = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) hw->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* send the first byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) data = hw->tx ? hw->tx[0] : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) out_8(&hw->regs->txd, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) wait_for_completion(&hw->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return hw->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct spi_ppc4xx_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u8 cdm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Start with the generic configuration for this device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) bits_per_word = spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) speed = spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Modify the configuration if the transfer overrides it. Do not allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * the transfer to overwrite the generic configuration with zeros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (t->bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) bits_per_word = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (t->speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) speed = min(t->speed_hz, spi->max_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (!speed || (speed > spi->max_speed_hz)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Write new configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) out_8(&hw->regs->mode, cs->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Set the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* opb_freq was already divided by 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) scr = (hw->opb_freq / speed) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (scr > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) cdm = min(scr, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (in_8(&hw->regs->cdm) != cdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) out_8(&hw->regs->cdm, cdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mutex_lock(&hw->bitbang.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (!hw->bitbang.busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Need to ndelay here? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) mutex_unlock(&hw->bitbang.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int spi_ppc4xx_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct spi_ppc4xx_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!spi->max_speed_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (cs == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) cs = kzalloc(sizeof *cs, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) spi->controller_state = cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * We set all bits of the SPI0_MODE register, so,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * no need to read-modify-write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) cs->mode = SPI_PPC4XX_MODE_SPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) switch (spi->mode & (SPI_CPHA | SPI_CPOL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) case SPI_MODE_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) cs->mode |= SPI_CLK_MODE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case SPI_MODE_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) cs->mode |= SPI_CLK_MODE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case SPI_MODE_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) cs->mode |= SPI_CLK_MODE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case SPI_MODE_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) cs->mode |= SPI_CLK_MODE3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (spi->mode & SPI_LSB_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) cs->mode |= SPI_PPC4XX_MODE_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct ppc4xx_spi *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) hw = (struct ppc4xx_spi *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) status = in_8(&hw->regs->sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * BSY de-asserts one cycle after the transfer is complete. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * interrupt is asserted after the transfer is complete. The exact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * relationship is not documented, hence this code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u8 lstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ndelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) lstatus = in_8(&hw->regs->sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (cnt >= 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_err(hw->dev, "busywait: too many loops!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) complete(&hw->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* status is always 1 (RBR) here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) status = in_8(&hw->regs->sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) count = hw->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) hw->count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* RBR triggered this interrupt. Therefore, data must be ready. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) data = in_8(&hw->regs->rxd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (hw->rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) hw->rx[count] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (count < hw->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) data = hw->tx ? hw->tx[count] : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) out_8(&hw->regs->txd, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) complete(&hw->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void spi_ppc4xx_cleanup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) kfree(spi->controller_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * On all 4xx PPC's the SPI bus is shared/multiplexed with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * the 2nd I2C bus. We need to enable the the SPI bus before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * using it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* need to clear bit 14 to enable SPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * platform_device layer stuff...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int spi_ppc4xx_of_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct ppc4xx_spi *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct spi_bitbang *bbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct resource resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct device_node *np = op->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct device *dev = &op->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct device_node *opbnp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) const unsigned int *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) master = spi_alloc_master(dev, sizeof *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (master == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) master->dev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) platform_set_drvdata(op, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) hw = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) hw->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) hw->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) init_completion(&hw->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Setup the state for the bitbang driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) bbp = &hw->bitbang;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) bbp->master = hw->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) bbp->setup_transfer = spi_ppc4xx_setupxfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) bbp->txrx_bufs = spi_ppc4xx_txrx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) bbp->use_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) bbp->master->setup = spi_ppc4xx_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) bbp->master->cleanup = spi_ppc4xx_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) bbp->master->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) bbp->master->use_gpio_descriptors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * The SPI core will count the number of GPIO descriptors to figure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * out the number of chip selects available on the platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) bbp->master->num_chipselect = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* the spi->mode bits understood by this driver: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) bbp->master->mode_bits =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Get the clock for the OPB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (opbnp == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev_err(dev, "OPB: cannot find node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Get the clock (Hz) for the OPB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) clk = of_get_property(opbnp, "clock-frequency", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (clk == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_err(dev, "OPB: no clock-frequency property set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) of_node_put(opbnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) hw->opb_freq = *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) hw->opb_freq >>= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) of_node_put(opbnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = of_address_to_resource(np, 0, &resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dev_err(dev, "error while parsing device node resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) hw->mapbase = resource.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) hw->mapsize = resource_size(&resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_err(dev, "too small to map registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Request IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) hw->irqnum = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret = request_irq(hw->irqnum, spi_ppc4xx_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 0, "spi_ppc4xx_of", (void *)hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_err(dev, "unable to allocate interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_err(dev, "resource unavailable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) goto request_mem_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!hw->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev_err(dev, "unable to memory map registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) goto map_io_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) spi_ppc4xx_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* Finally register our spi controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dev->dma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = spi_bitbang_start(bbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(dev, "failed to register SPI master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) goto unmap_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_info(dev, "driver initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unmap_regs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) iounmap(hw->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) map_io_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) release_mem_region(hw->mapbase, hw->mapsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) request_mem_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) free_irq(hw->irqnum, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) free_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_err(dev, "initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int spi_ppc4xx_of_remove(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct spi_master *master = platform_get_drvdata(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct ppc4xx_spi *hw = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) spi_bitbang_stop(&hw->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) release_mem_region(hw->mapbase, hw->mapsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) free_irq(hw->irqnum, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) iounmap(hw->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const struct of_device_id spi_ppc4xx_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { .compatible = "ibm,ppc4xx-spi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static struct platform_driver spi_ppc4xx_of_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .probe = spi_ppc4xx_of_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .remove = spi_ppc4xx_of_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .of_match_table = spi_ppc4xx_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) module_platform_driver(spi_ppc4xx_of_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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