^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008-2012 ST-Ericsson AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Linus Walleij <linus.walleij@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Initial version inspired by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Initial adoption to PL022 by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Sachin Verma <sachin.verma@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/amba/bus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/amba/pl022.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * This macro is used to define some register default values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * reg is masked with mask, the OR:ed with an (again masked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * val shifted sb steps to the left.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SSP_WRITE_BITS(reg, val, mask, sb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * This macro is also used to define some default values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * It will just shift val by sb steps to the left and mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * the result with mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GEN_MASK_BITS(val, mask, sb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) (((val)<<(sb)) & (mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DRIVE_TX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DO_NOT_DRIVE_TX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DO_NOT_QUEUE_DMA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define QUEUE_DMA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RX_TRANSFER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TX_TRANSFER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Macros to access SSP Registers with their offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SSP_CR0(r) (r + 0x000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SSP_CR1(r) (r + 0x004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SSP_DR(r) (r + 0x008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SSP_SR(r) (r + 0x00C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SSP_CPSR(r) (r + 0x010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SSP_IMSC(r) (r + 0x014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SSP_RIS(r) (r + 0x018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SSP_MIS(r) (r + 0x01C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SSP_ICR(r) (r + 0x020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SSP_DMACR(r) (r + 0x024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SSP_CSR(r) (r + 0x030) /* vendor extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SSP_ITCR(r) (r + 0x080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SSP_ITIP(r) (r + 0x084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SSP_ITOP(r) (r + 0x088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SSP_TDR(r) (r + 0x08C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SSP_PID0(r) (r + 0xFE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SSP_PID1(r) (r + 0xFE4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SSP_PID2(r) (r + 0xFE8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SSP_PID3(r) (r + 0xFEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SSP_CID0(r) (r + 0xFF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SSP_CID1(r) (r + 0xFF4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SSP_CID2(r) (r + 0xFF8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SSP_CID3(r) (r + 0xFFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * SSP Control Register 0 - SSP_CR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SSP_CR0_MASK_DSS (0x0FUL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SSP_CR0_MASK_FRF (0x3UL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SSP_CR0_MASK_SPO (0x1UL << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SSP_CR0_MASK_SPH (0x1UL << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SSP_CR0_MASK_SCR (0xFFUL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * The ST version of this block moves som bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * in SSP_CR0 and extends it to 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * SSP Control Register 0 - SSP_CR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SSP_CR1_MASK_LBM (0x1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SSP_CR1_MASK_SSE (0x1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SSP_CR1_MASK_MS (0x1UL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SSP_CR1_MASK_SOD (0x1UL << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * The ST version of this block adds some bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * in SSP_CR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* This one is only in the PL023 variant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * SSP Status Register - SSP_SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * SSP Clock Prescale Register - SSP_CPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * SSP Raw Interrupt Status Register - SSP_RIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Receive Overrun Raw Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SSP_RIS_MASK_RORRIS (0x1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Receive Timeout Raw Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SSP_RIS_MASK_RTRIS (0x1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Receive FIFO Raw Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SSP_RIS_MASK_RXRIS (0x1UL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Transmit FIFO Raw Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SSP_RIS_MASK_TXRIS (0x1UL << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * SSP Masked Interrupt Status Register - SSP_MIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Receive Overrun Masked Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SSP_MIS_MASK_RORMIS (0x1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Receive Timeout Masked Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SSP_MIS_MASK_RTMIS (0x1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Receive FIFO Masked Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SSP_MIS_MASK_RXMIS (0x1UL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Transmit FIFO Masked Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SSP_MIS_MASK_TXMIS (0x1UL << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * SSP Interrupt Clear Register - SSP_ICR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Receive Overrun Raw Clear Interrupt bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SSP_ICR_MASK_RORIC (0x1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Receive Timeout Clear Interrupt bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SSP_ICR_MASK_RTIC (0x1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * SSP DMA Control Register - SSP_DMACR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Receive DMA Enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Transmit DMA Enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * SSP Chip Select Control Register - SSP_CSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * (vendor extension)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SSP_CSR_CSVALUE_MASK (0x1FUL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * SSP Integration Test control Register - SSP_ITCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SSP_ITCR_MASK_ITEN (0x1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * SSP Integration Test Input Register - SSP_ITIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define ITIP_MASK_SSPRXD (0x1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define ITIP_MASK_SSPFSSIN (0x1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define ITIP_MASK_SSPCLKIN (0x1UL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define ITIP_MASK_RXDMAC (0x1UL << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define ITIP_MASK_TXDMAC (0x1UL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define ITIP_MASK_SSPTXDIN (0x1UL << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * SSP Integration Test output Register - SSP_ITOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ITOP_MASK_SSPTXD (0x1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ITOP_MASK_SSPOEn (0x1UL << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ITOP_MASK_RORINTR (0x1UL << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ITOP_MASK_RTINTR (0x1UL << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ITOP_MASK_RXINTR (0x1UL << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define ITOP_MASK_TXINTR (0x1UL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define ITOP_MASK_INTR (0x1UL << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define ITOP_MASK_RXDMABREQ (0x1UL << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define ITOP_MASK_RXDMASREQ (0x1UL << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define ITOP_MASK_TXDMABREQ (0x1UL << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define ITOP_MASK_TXDMASREQ (0x1UL << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * SSP Test Data Register - SSP_TDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TDR_MASK_TESTDATA (0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Message State
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * we use the spi_message.state (void *) pointer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * hold a single state value, that's why all this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * (void *) casting is done here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define STATE_START ((void *) 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define STATE_RUNNING ((void *) 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define STATE_DONE ((void *) 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define STATE_ERROR ((void *) -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define STATE_TIMEOUT ((void *) -2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * SSP State - Whether Enabled or Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SSP_DISABLED (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SSP_ENABLED (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * SSP DMA State - Whether DMA Enabled or Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SSP_DMA_DISABLED (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SSP_DMA_ENABLED (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * SSP Clock Defaults
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SSP_DEFAULT_CLKRATE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SSP_DEFAULT_PRESCALE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * SSP Clock Parameter ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CPSDVR_MIN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CPSDVR_MAX 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SCR_MIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SCR_MAX 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * SSP Interrupt related Macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define DEFAULT_SSP_REG_IMSC 0x0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ENABLE_ALL_INTERRUPTS ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) SSP_IMSC_MASK_RORIM | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) SSP_IMSC_MASK_RTIM | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) SSP_IMSC_MASK_RXIM | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) SSP_IMSC_MASK_TXIM \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CLEAR_ALL_INTERRUPTS 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SPI_POLLING_TIMEOUT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * The type of reading going on on this chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) enum ssp_reading {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) READING_NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) READING_U8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) READING_U16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) READING_U32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * The type of writing going on on this chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) enum ssp_writing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) WRITING_NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) WRITING_U8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) WRITING_U16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) WRITING_U32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * struct vendor_data - vendor-specific config parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * for PL022 derivates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * @fifodepth: depth of FIFOs (both)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * @max_bpw: maximum number of bits per word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * @unidir: supports unidirection transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * @extended_cr: 32 bit wide control register 0 with extra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * features and extra features in CR1 as found in the ST variants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * @pl023: supports a subset of the ST extensions called "PL023"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * @loopback: supports loopback mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * @internal_cs_ctrl: supports chip select control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct vendor_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int fifodepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int max_bpw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) bool unidir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) bool extended_cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) bool pl023;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) bool loopback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) bool internal_cs_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * struct pl022 - This is the private SSP driver data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * @adev: AMBA device model hookup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * @vendor: vendor data for the IP block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * @phybase: the physical memory where the SSP device resides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * @virtbase: the virtual memory where the SSP is mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * @clk: outgoing clock "SPICLK" for the SPI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * @master: SPI framework hookup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * @master_info: controller-specific data from machine setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * @pump_transfers: Tasklet used in Interrupt Transfer mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * @cur_msg: Pointer to current spi_message being processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * @cur_transfer: Pointer to current spi_transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * @cur_chip: pointer to current clients chip(assigned from controller_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @next_msg_cs_active: the next message in the queue has been examined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * and it was found that it uses the same chip select as the previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * message, so we left it active after the previous transfer, and it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * active already.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * @tx: current position in TX buffer to be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * @tx_end: end position in TX buffer to be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * @rx: current position in RX buffer to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * @rx_end: end position in RX buffer to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * @read: the type of read currently going on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * @write: the type of write currently going on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * @exp_fifo_level: expected FIFO level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * @rx_lev_trig: receive FIFO watermark level which triggers IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * @tx_lev_trig: transmit FIFO watermark level which triggers IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * @dma_rx_channel: optional channel for RX DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * @dma_tx_channel: optional channel for TX DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * @sgt_rx: scattertable for the RX transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * @sgt_tx: scattertable for the TX transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * @dummypage: a dummy page used for driving data on the bus with DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * @dma_running: indicates whether DMA is in operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * @cur_cs: current chip select (gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * @chipselects: list of chipselects (gpios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct pl022 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct amba_device *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct vendor_data *vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) resource_size_t phybase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) void __iomem *virtbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct pl022_ssp_controller *master_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Message per-transfer pump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct tasklet_struct pump_transfers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct spi_message *cur_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct spi_transfer *cur_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct chip_data *cur_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) bool next_msg_cs_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) void *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) void *tx_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) void *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) void *rx_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) enum ssp_reading read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) enum ssp_writing write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 exp_fifo_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) enum ssp_rx_level_trig rx_lev_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) enum ssp_tx_level_trig tx_lev_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* DMA settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #ifdef CONFIG_DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct dma_chan *dma_rx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct dma_chan *dma_tx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct sg_table sgt_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct sg_table sgt_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) char *dummypage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) bool dma_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int cur_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int *chipselects;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * struct chip_data - To maintain runtime state of SSP for each client chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * @cr0: Value of control register CR0 of SSP - on later ST variants this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * register is 32 bits wide rather than just 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * @cr1: Value of control register CR1 of SSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * @dmacr: Value of DMA control Register of SSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * @cpsr: Value of Clock prescale register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * @enable_dma: Whether to enable DMA or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * @read: function ptr to be used to read when doing xfer for this chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * @write: function ptr to be used to write when doing xfer for this chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * @cs_control: chip select callback provided by chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * @xfer_type: polling/interrupt/DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Runtime state of the SSP controller, maintained per chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * This would be set according to the current message that would be served
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u32 cr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u16 cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u16 dmacr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u16 cpsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u8 n_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) bool enable_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) enum ssp_reading read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) enum ssp_writing write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) void (*cs_control) (u32 command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int xfer_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * null_cs_control - Dummy chip select function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * @command: select/delect the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * If no chip select function is provided by client this is used as dummy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * chip select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static void null_cs_control(u32 command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * internal_cs_control - Control chip select signals via SSP_CSR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * @pl022: SSP driver private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * @command: select/delect the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * Used on controller with internal chip select control via SSP_CSR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * (vendor extension). Each of the 5 LSB in the register controls one chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * select signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static void internal_cs_control(struct pl022 *pl022, u32 command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) tmp = readw(SSP_CSR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (command == SSP_CHIP_SELECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) tmp &= ~BIT(pl022->cur_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) tmp |= BIT(pl022->cur_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) writew(tmp, SSP_CSR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static void pl022_cs_control(struct pl022 *pl022, u32 command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (pl022->vendor->internal_cs_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) internal_cs_control(pl022, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) else if (gpio_is_valid(pl022->cur_cs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) gpio_set_value(pl022->cur_cs, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) pl022->cur_chip->cs_control(command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * giveback - current spi_message is over, schedule next message and call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * callback of this message. Assumes that caller already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * set message->status; dma and pio irqs are blocked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * @pl022: SSP driver private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static void giveback(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct spi_transfer *last_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) pl022->next_msg_cs_active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) last_transfer = list_last_entry(&pl022->cur_msg->transfers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct spi_transfer, transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Delay if requested before any change in chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * FIXME: This runs in interrupt context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * Is this really smart?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) spi_transfer_delay_exec(last_transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (!last_transfer->cs_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct spi_message *next_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * cs_change was not set. We can keep the chip select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * enabled if there is message in the queue and it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * for the same spi device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * We cannot postpone this until pump_messages, because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * after calling msg->complete (below) the driver that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * sent the current message could be unloaded, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * could invalidate the cs_control() callback...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* get a pointer to the next message, if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) next_msg = spi_get_next_queued_message(pl022->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * see if the next and current messages point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * to the same spi device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (next_msg && next_msg->spi != pl022->cur_msg->spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) next_msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (!next_msg || pl022->cur_msg->state == STATE_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) pl022_cs_control(pl022, SSP_CHIP_DESELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pl022->next_msg_cs_active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) pl022->cur_msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) pl022->cur_transfer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) pl022->cur_chip = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* disable the SPI/SSP operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) writew((readw(SSP_CR1(pl022->virtbase)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) spi_finalize_current_message(pl022->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * flush - flush the FIFO to reach a clean state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * @pl022: SSP driver private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static int flush(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) unsigned long limit = loops_per_jiffy << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dev_dbg(&pl022->adev->dev, "flush\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) readw(SSP_DR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pl022->exp_fifo_level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * restore_state - Load configuration of current chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * @pl022: SSP driver private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static void restore_state(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct chip_data *chip = pl022->cur_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (pl022->vendor->extended_cr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) writel(chip->cr0, SSP_CR0(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) writew(chip->cr0, SSP_CR0(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) writew(chip->cr1, SSP_CR1(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * Default SSP Register Values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define DEFAULT_SSP_REG_CR0 ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* ST versions have slightly different bit layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define DEFAULT_SSP_REG_CR0_ST ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* The PL023 version is slightly different again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define DEFAULT_SSP_REG_CR1 ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* ST versions extend this register to use all 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define DEFAULT_SSP_REG_CR1_ST ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) DEFAULT_SSP_REG_CR1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * The PL023 variant has further differences: no loopback mode, no microwire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * support, and a new clock feedback delay setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define DEFAULT_SSP_REG_CPSR ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define DEFAULT_SSP_REG_DMACR (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * load_ssp_default_config - Load default configuration for SSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * @pl022: SSP driver private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static void load_ssp_default_config(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (pl022->vendor->pl023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) } else if (pl022->vendor->extended_cr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * This will write to TX and read from RX according to the parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * set in pl022.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static void readwriter(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * The FIFO depth is different between primecell variants.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * I believe filling in too much in the FIFO might cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * errons in 8bit wide transfers on ARM variants (just 8 words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * FIFO, means only 8x8 = 64 bits in FIFO) at least.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * To prevent this issue, the TX FIFO is only filled to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * unused RX FIFO fill length, regardless of what the TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * FIFO status flag indicates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_dbg(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Read as much as you can */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) && (pl022->rx < pl022->rx_end)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) switch (pl022->read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) case READING_NULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) readw(SSP_DR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) case READING_U8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) *(u8 *) (pl022->rx) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) readw(SSP_DR(pl022->virtbase)) & 0xFFU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) case READING_U16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) *(u16 *) (pl022->rx) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) (u16) readw(SSP_DR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) case READING_U32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) *(u32 *) (pl022->rx) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) readl(SSP_DR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) pl022->rx += (pl022->cur_chip->n_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) pl022->exp_fifo_level--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * Write as much as possible up to the RX FIFO size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) && (pl022->tx < pl022->tx_end)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) switch (pl022->write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) case WRITING_NULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) writew(0x0, SSP_DR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) case WRITING_U8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) case WRITING_U16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) case WRITING_U32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) pl022->tx += (pl022->cur_chip->n_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) pl022->exp_fifo_level++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * This inner reader takes care of things appearing in the RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * FIFO as we're transmitting. This will happen a lot since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * clock starts running when you put things into the TX FIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * and then things are continuously clocked into the RX FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) && (pl022->rx < pl022->rx_end)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) switch (pl022->read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) case READING_NULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) readw(SSP_DR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) case READING_U8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) *(u8 *) (pl022->rx) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) readw(SSP_DR(pl022->virtbase)) & 0xFFU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) case READING_U16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) *(u16 *) (pl022->rx) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) (u16) readw(SSP_DR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) case READING_U32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) *(u32 *) (pl022->rx) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) readl(SSP_DR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) pl022->rx += (pl022->cur_chip->n_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) pl022->exp_fifo_level--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * When we exit here the TX FIFO should be full and the RX FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * should be empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * next_transfer - Move to the Next transfer in the current spi message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * @pl022: SSP driver private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * This function moves though the linked list of spi transfers in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * current spi message and returns with the state of current spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * message i.e whether its last transfer is done(STATE_DONE) or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * Next transfer is ready(STATE_RUNNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static void *next_transfer(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct spi_message *msg = pl022->cur_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct spi_transfer *trans = pl022->cur_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* Move to next transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (trans->transfer_list.next != &msg->transfers) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) pl022->cur_transfer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) list_entry(trans->transfer_list.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct spi_transfer, transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return STATE_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return STATE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * This DMA functionality is only compiled in if we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * access to the generic DMA devices/DMA engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #ifdef CONFIG_DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static void unmap_free_dma_scatter(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* Unmap and free the SG tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) pl022->sgt_tx.nents, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) pl022->sgt_rx.nents, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) sg_free_table(&pl022->sgt_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) sg_free_table(&pl022->sgt_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static void dma_callback(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct pl022 *pl022 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct spi_message *msg = pl022->cur_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) BUG_ON(!pl022->sgt_rx.sgl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #ifdef VERBOSE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * Optionally dump out buffers to inspect contents, this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * good if you want to convince yourself that the loopback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * read/write contents are the same, when adopting to a new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * DMA engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dma_sync_sg_for_cpu(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) pl022->sgt_rx.sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) pl022->sgt_rx.nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) print_hex_dump(KERN_ERR, "SPI RX: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) sg_virt(sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) sg_dma_len(sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) print_hex_dump(KERN_ERR, "SPI TX: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) sg_virt(sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) sg_dma_len(sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) unmap_free_dma_scatter(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* Update total bytes transferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) msg->actual_length += pl022->cur_transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* Move to next transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) msg->state = next_transfer(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) pl022_cs_control(pl022, SSP_CHIP_DESELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) tasklet_schedule(&pl022->pump_transfers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static void setup_dma_scatter(struct pl022 *pl022,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) void *buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) unsigned int length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct sg_table *sgtab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int bytesleft = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) void *bufp = buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int mapbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * If there are less bytes left than what fits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * in the current page (plus page alignment offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * we just feed in this, else we stuff in as much
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * as we can.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) mapbytes = bytesleft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) mapbytes = PAGE_SIZE - offset_in_page(bufp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) sg_set_page(sg, virt_to_page(bufp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) mapbytes, offset_in_page(bufp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) bufp += mapbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) bytesleft -= mapbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) dev_dbg(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) "set RX/TX target page @ %p, %d bytes, %d left\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) bufp, mapbytes, bytesleft);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* Map the dummy buffer on every page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (bytesleft < PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) mapbytes = bytesleft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) mapbytes = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) sg_set_page(sg, virt_to_page(pl022->dummypage),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) mapbytes, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) bytesleft -= mapbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dev_dbg(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) "set RX/TX to dummy page %d bytes, %d left\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) mapbytes, bytesleft);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) BUG_ON(bytesleft);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * configure_dma - configures the channels for the next transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * @pl022: SSP driver's private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static int configure_dma(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct dma_slave_config rx_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .src_addr = SSP_DR(pl022->phybase),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .direction = DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .device_fc = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct dma_slave_config tx_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .dst_addr = SSP_DR(pl022->phybase),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .direction = DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .device_fc = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) unsigned int pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) int rx_sglen, tx_sglen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct dma_chan *rxchan = pl022->dma_rx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct dma_chan *txchan = pl022->dma_tx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct dma_async_tx_descriptor *rxdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct dma_async_tx_descriptor *txdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* Check that the channels are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (!rxchan || !txchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * If supplied, the DMA burstsize should equal the FIFO trigger level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * Notice that the DMA engine uses one-to-one mapping. Since we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * not trigger on 2 elements this needs explicit mapping rather than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * calculation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) switch (pl022->rx_lev_trig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) case SSP_RX_1_OR_MORE_ELEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) rx_conf.src_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) case SSP_RX_4_OR_MORE_ELEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) rx_conf.src_maxburst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) case SSP_RX_8_OR_MORE_ELEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) rx_conf.src_maxburst = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) case SSP_RX_16_OR_MORE_ELEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) rx_conf.src_maxburst = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) case SSP_RX_32_OR_MORE_ELEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) rx_conf.src_maxburst = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) switch (pl022->tx_lev_trig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) case SSP_TX_1_OR_MORE_EMPTY_LOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) tx_conf.dst_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) case SSP_TX_4_OR_MORE_EMPTY_LOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) tx_conf.dst_maxburst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) case SSP_TX_8_OR_MORE_EMPTY_LOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) tx_conf.dst_maxburst = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) case SSP_TX_16_OR_MORE_EMPTY_LOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) tx_conf.dst_maxburst = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) case SSP_TX_32_OR_MORE_EMPTY_LOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) tx_conf.dst_maxburst = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) switch (pl022->read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) case READING_NULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* Use the same as for writing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) case READING_U8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) case READING_U16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) case READING_U32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) switch (pl022->write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) case WRITING_NULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* Use the same as for reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) case WRITING_U8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) case WRITING_U16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) case WRITING_U32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /* SPI pecularity: we need to read and write the same width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) rx_conf.src_addr_width = tx_conf.dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) tx_conf.dst_addr_width = rx_conf.src_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) dmaengine_slave_config(rxchan, &rx_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) dmaengine_slave_config(txchan, &tx_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* Create sglists for the transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) goto err_alloc_rx_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) goto err_alloc_tx_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /* Fill in the scatterlists for the RX+TX buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) setup_dma_scatter(pl022, pl022->rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) pl022->cur_transfer->len, &pl022->sgt_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) setup_dma_scatter(pl022, pl022->tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) pl022->cur_transfer->len, &pl022->sgt_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* Map DMA buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) pl022->sgt_rx.nents, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (!rx_sglen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) goto err_rx_sgmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) pl022->sgt_tx.nents, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (!tx_sglen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) goto err_tx_sgmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* Send both scatterlists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) rxdesc = dmaengine_prep_slave_sg(rxchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) pl022->sgt_rx.sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) rx_sglen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (!rxdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) goto err_rxdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) txdesc = dmaengine_prep_slave_sg(txchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) pl022->sgt_tx.sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) tx_sglen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (!txdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) goto err_txdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /* Put the callback on the RX transfer only, that should finish last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) rxdesc->callback = dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) rxdesc->callback_param = pl022;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /* Submit and fire RX and TX with TX last so we're ready to read! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) dmaengine_submit(rxdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) dmaengine_submit(txdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) dma_async_issue_pending(rxchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) dma_async_issue_pending(txchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) pl022->dma_running = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) err_txdesc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) dmaengine_terminate_all(txchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) err_rxdesc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) dmaengine_terminate_all(rxchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) pl022->sgt_tx.nents, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) err_tx_sgmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) pl022->sgt_rx.nents, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) err_rx_sgmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) sg_free_table(&pl022->sgt_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) err_alloc_tx_sg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) sg_free_table(&pl022->sgt_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) err_alloc_rx_sg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static int pl022_dma_probe(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /* Try to acquire a generic DMA engine slave channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) dma_cap_set(DMA_SLAVE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * We need both RX and TX channels to do DMA, else do none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * of them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) pl022->dma_rx_channel = dma_request_channel(mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) pl022->master_info->dma_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) pl022->master_info->dma_rx_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (!pl022->dma_rx_channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) goto err_no_rxchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) pl022->dma_tx_channel = dma_request_channel(mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) pl022->master_info->dma_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) pl022->master_info->dma_tx_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (!pl022->dma_tx_channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) goto err_no_txchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (!pl022->dummypage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) goto err_no_dummypage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) dma_chan_name(pl022->dma_rx_channel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) dma_chan_name(pl022->dma_tx_channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) err_no_dummypage:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) dma_release_channel(pl022->dma_tx_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) err_no_txchan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) dma_release_channel(pl022->dma_rx_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) pl022->dma_rx_channel = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) err_no_rxchan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) "Failed to work in dma mode, work without dma!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static int pl022_dma_autoprobe(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct device *dev = &pl022->adev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /* automatically configure DMA channels from platform, normally using DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) chan = dma_request_chan(dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (IS_ERR(chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) err = PTR_ERR(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) goto err_no_rxchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) pl022->dma_rx_channel = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) chan = dma_request_chan(dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (IS_ERR(chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) err = PTR_ERR(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) goto err_no_txchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) pl022->dma_tx_channel = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (!pl022->dummypage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) goto err_no_dummypage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) err_no_dummypage:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) dma_release_channel(pl022->dma_tx_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) pl022->dma_tx_channel = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) err_no_txchan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) dma_release_channel(pl022->dma_rx_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) pl022->dma_rx_channel = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) err_no_rxchan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static void terminate_dma(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct dma_chan *rxchan = pl022->dma_rx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct dma_chan *txchan = pl022->dma_tx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) dmaengine_terminate_all(rxchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) dmaengine_terminate_all(txchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) unmap_free_dma_scatter(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) pl022->dma_running = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static void pl022_dma_remove(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (pl022->dma_running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) terminate_dma(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (pl022->dma_tx_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) dma_release_channel(pl022->dma_tx_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (pl022->dma_rx_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) dma_release_channel(pl022->dma_rx_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) kfree(pl022->dummypage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static inline int configure_dma(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static inline int pl022_dma_autoprobe(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static inline int pl022_dma_probe(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static inline void pl022_dma_remove(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * pl022_interrupt_handler - Interrupt handler for SSP controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * @irq: IRQ number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * @dev_id: Local device data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) * This function handles interrupts generated for an interrupt based transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * current message's state as STATE_ERROR and schedule the tasklet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) * pump_transfers which will do the postprocessing of the current message by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * calling giveback(). Otherwise it reads data from RX FIFO till there is no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) * more data, and writes data in TX FIFO till it is not full. If we complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) * the transfer we move to the next transfer and schedule the tasklet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) struct pl022 *pl022 = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct spi_message *msg = pl022->cur_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) u16 irq_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (unlikely(!msg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) "bad message state in interrupt handler");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /* Never fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) /* Read the Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) irq_status = readw(SSP_MIS(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (unlikely(!irq_status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * This handles the FIFO interrupts, the timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * interrupts are flatly ignored, they cannot be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) * trusted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * Overrun interrupt - bail out since our Data has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * corrupted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) dev_err(&pl022->adev->dev, "FIFO overrun\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) "RXFIFO is full\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * Disable and clear interrupts, disable SSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * mark message with bad status so it can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * retried.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) writew(DISABLE_ALL_INTERRUPTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) SSP_IMSC(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) writew((readw(SSP_CR1(pl022->virtbase)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) msg->state = STATE_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) /* Schedule message queue handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) tasklet_schedule(&pl022->pump_transfers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) readwriter(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (pl022->tx == pl022->tx_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /* Disable Transmit interrupt, enable receive interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) writew((readw(SSP_IMSC(pl022->virtbase)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) SSP_IMSC(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * Since all transactions must write as much as shall be read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * we can conclude the entire transaction once RX is complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * At this point, all TX will always be finished.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (pl022->rx >= pl022->rx_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) writew(DISABLE_ALL_INTERRUPTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) SSP_IMSC(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (unlikely(pl022->rx > pl022->rx_end)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) dev_warn(&pl022->adev->dev, "read %u surplus "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) "bytes (did you request an odd "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) "number of bytes on a 16bit bus?)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) (u32) (pl022->rx - pl022->rx_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /* Update total bytes transferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) msg->actual_length += pl022->cur_transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /* Move to next transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) msg->state = next_transfer(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) pl022_cs_control(pl022, SSP_CHIP_DESELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) tasklet_schedule(&pl022->pump_transfers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * This sets up the pointers to memory for the next message to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * send out on the SPI bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) static int set_up_next_transfer(struct pl022 *pl022,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) struct spi_transfer *transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) int residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /* Sanity check the message for this bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) if (unlikely(residue != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) "message of %u bytes to transmit but the current "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) "chip bus has a data width of %u bytes!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) pl022->cur_transfer->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) pl022->cur_chip->n_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) dev_err(&pl022->adev->dev, "skipping this message\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) pl022->tx = (void *)transfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) pl022->rx = (void *)transfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) pl022->write =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * pump_transfers - Tasklet function which schedules next transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * when running in interrupt or DMA transfer mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * @data: SSP driver private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) static void pump_transfers(unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) struct pl022 *pl022 = (struct pl022 *) data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) struct spi_message *message = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) struct spi_transfer *transfer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) struct spi_transfer *previous = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) /* Get current state information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) message = pl022->cur_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) transfer = pl022->cur_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) /* Handle for abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (message->state == STATE_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) message->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) giveback(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /* Handle end of message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (message->state == STATE_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) message->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) giveback(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) /* Delay if requested at end of transfer before CS change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (message->state == STATE_RUNNING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) previous = list_entry(transfer->transfer_list.prev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct spi_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) * FIXME: This runs in interrupt context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) * Is this really smart?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) spi_transfer_delay_exec(previous);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /* Reselect chip select only if cs_change was requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (previous->cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) pl022_cs_control(pl022, SSP_CHIP_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) /* STATE_START */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) message->state = STATE_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (set_up_next_transfer(pl022, transfer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) message->state = STATE_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) message->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) giveback(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /* Flush the FIFOs and let's go! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) flush(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (pl022->cur_chip->enable_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (configure_dma(pl022)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) dev_dbg(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) "configuration of DMA failed, fall back to interrupt mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) goto err_config_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) err_config_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /* enable all interrupts except RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) static void do_interrupt_dma_transfer(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * Default is to enable all interrupts except RX -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) * this will be enabled once TX is complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) u32 irqflags = (u32)(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /* Enable target chip, if not already active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (!pl022->next_msg_cs_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) pl022_cs_control(pl022, SSP_CHIP_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) /* Error path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) pl022->cur_msg->state = STATE_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) pl022->cur_msg->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) giveback(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /* If we're using DMA, set up DMA here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (pl022->cur_chip->enable_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* Configure DMA transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) if (configure_dma(pl022)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) dev_dbg(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) "configuration of DMA failed, fall back to interrupt mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) goto err_config_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /* Disable interrupts in DMA mode, IRQ from DMA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) irqflags = DISABLE_ALL_INTERRUPTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) err_config_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) /* Enable SSP, turn on interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) SSP_CR1(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) writew(irqflags, SSP_IMSC(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) static void print_current_status(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) u32 read_cr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) u16 read_cr1, read_dmacr, read_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (pl022->vendor->extended_cr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) read_cr0 = readl(SSP_CR0(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) read_cr0 = readw(SSP_CR0(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) read_cr1 = readw(SSP_CR1(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) read_dmacr = readw(SSP_DMACR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) read_sr = readw(SSP_SR(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) dev_warn(&pl022->adev->dev, "spi-pl022 CR0: %x\n", read_cr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) dev_warn(&pl022->adev->dev, "spi-pl022 CR1: %x\n", read_cr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n", read_dmacr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) dev_warn(&pl022->adev->dev, "spi-pl022 SR: %x\n", read_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) dev_warn(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) "spi-pl022 exp_fifo_level/fifodepth: %u/%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) pl022->exp_fifo_level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) pl022->vendor->fifodepth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static void do_polling_transfer(struct pl022 *pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) struct spi_message *message = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) struct spi_transfer *transfer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) struct spi_transfer *previous = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) unsigned long time, timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) message = pl022->cur_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) while (message->state != STATE_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) /* Handle for abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) if (message->state == STATE_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) transfer = pl022->cur_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* Delay if requested at end of transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (message->state == STATE_RUNNING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) previous =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) list_entry(transfer->transfer_list.prev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct spi_transfer, transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) spi_transfer_delay_exec(previous);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (previous->cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) pl022_cs_control(pl022, SSP_CHIP_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) /* STATE_START */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) message->state = STATE_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (!pl022->next_msg_cs_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) pl022_cs_control(pl022, SSP_CHIP_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) /* Configuration Changing Per Transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (set_up_next_transfer(pl022, transfer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /* Error path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) message->state = STATE_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) /* Flush FIFOs and enable SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) flush(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) SSP_CR1(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) time = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) readwriter(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (time_after(time, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) dev_warn(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) "%s: timeout!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) message->state = STATE_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) print_current_status(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /* Update total byte transferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) message->actual_length += pl022->cur_transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) /* Move to next transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) message->state = next_transfer(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (message->state != STATE_DONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) && pl022->cur_transfer->cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) pl022_cs_control(pl022, SSP_CHIP_DESELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /* Handle end of message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) if (message->state == STATE_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) message->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) else if (message->state == STATE_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) message->status = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) message->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) giveback(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static int pl022_transfer_one_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) struct pl022 *pl022 = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /* Initial message state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) pl022->cur_msg = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) msg->state = STATE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) pl022->cur_transfer = list_entry(msg->transfers.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) struct spi_transfer, transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) /* Setup the SPI using the per chip configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) pl022->cur_chip = spi_get_ctldata(msg->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) pl022->cur_cs = pl022->chipselects[msg->spi->chip_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) restore_state(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) flush(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) do_polling_transfer(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) do_interrupt_dma_transfer(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) static int pl022_unprepare_transfer_hardware(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) struct pl022 *pl022 = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) /* nothing more to do - disable spi/ssp and power off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) writew((readw(SSP_CR1(pl022->virtbase)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) static int verify_controller_parameters(struct pl022 *pl022,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) struct pl022_config_chip const *chip_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) "interface is configured incorrectly\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) (!pl022->vendor->unidir)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) "unidirectional mode not supported in this "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) "hardware version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if ((chip_info->hierarchy != SSP_MASTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) && (chip_info->hierarchy != SSP_SLAVE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) "hierarchy is configured incorrectly\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if ((chip_info->com_mode != INTERRUPT_TRANSFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) && (chip_info->com_mode != DMA_TRANSFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) && (chip_info->com_mode != POLLING_TRANSFER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) "Communication mode is configured incorrectly\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) switch (chip_info->rx_lev_trig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) case SSP_RX_1_OR_MORE_ELEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) case SSP_RX_4_OR_MORE_ELEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) case SSP_RX_8_OR_MORE_ELEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) /* These are always OK, all variants can handle this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) case SSP_RX_16_OR_MORE_ELEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (pl022->vendor->fifodepth < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) "RX FIFO Trigger Level is configured incorrectly\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) case SSP_RX_32_OR_MORE_ELEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (pl022->vendor->fifodepth < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) "RX FIFO Trigger Level is configured incorrectly\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) "RX FIFO Trigger Level is configured incorrectly\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) switch (chip_info->tx_lev_trig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) case SSP_TX_1_OR_MORE_EMPTY_LOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) case SSP_TX_4_OR_MORE_EMPTY_LOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) case SSP_TX_8_OR_MORE_EMPTY_LOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) /* These are always OK, all variants can handle this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) case SSP_TX_16_OR_MORE_EMPTY_LOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (pl022->vendor->fifodepth < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) "TX FIFO Trigger Level is configured incorrectly\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) case SSP_TX_32_OR_MORE_EMPTY_LOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) if (pl022->vendor->fifodepth < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) "TX FIFO Trigger Level is configured incorrectly\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) "TX FIFO Trigger Level is configured incorrectly\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if ((chip_info->ctrl_len < SSP_BITS_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) || (chip_info->ctrl_len > SSP_BITS_32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) "CTRL LEN is configured incorrectly\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) "Wait State is configured incorrectly\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) /* Half duplex is only available in the ST Micro version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (pl022->vendor->extended_cr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if ((chip_info->duplex !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) && (chip_info->duplex !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) "Microwire duplex mode is configured incorrectly\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) "Microwire half duplex mode requested,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) " but this is only available in the"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) " ST version of PL022\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) return rate / (cpsdvsr * (1 + scr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) ssp_clock_params * clk_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) /* Lets calculate the frequency parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) best_scr = 0, tmp, found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) rate = clk_get_rate(pl022->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) /* cpsdvscr = 2 & scr 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) /* cpsdvsr = 254 & scr = 255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) if (freq > max_tclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) dev_warn(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) "Max speed that can be programmed is %d Hz, you requested %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) max_tclk, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (freq < min_tclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) dev_err(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) "Requested frequency: %d Hz is less than minimum possible %d Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) freq, min_tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) * best_freq will give closest possible available rate (<= requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) * freq) for all values of scr & cpsdvsr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) while ((cpsdvsr <= CPSDVR_MAX) && !found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) while (scr <= SCR_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) tmp = spi_rate(rate, cpsdvsr, scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if (tmp > freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) /* we need lower freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) scr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) * If found exact value, mark found and break.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) * If found more closer value, update and break.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) if (tmp > best_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) best_freq = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) best_cpsdvsr = cpsdvsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) best_scr = scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (tmp == freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) * increased scr will give lower rates, which are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) * required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) cpsdvsr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) scr = SCR_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) clk_freq->scr = (u8) (best_scr & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) dev_dbg(&pl022->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) "SSP Target Frequency is: %u, Effective Frequency is %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) freq, best_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) clk_freq->cpsdvsr, clk_freq->scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) * A piece of default chip info unless the platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) * supplies it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) static const struct pl022_config_chip pl022_default_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .com_mode = POLLING_TRANSFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .iface = SSP_INTERFACE_MOTOROLA_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .hierarchy = SSP_SLAVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .slave_tx_disable = DO_NOT_DRIVE_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .ctrl_len = SSP_BITS_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) .wait_state = SSP_MWIRE_WAIT_ZERO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .cs_control = null_cs_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) * pl022_setup - setup function registered to SPI master framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) * @spi: spi device which is requesting setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) * This function is registered to the SPI framework for this SPI master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) * controller. If it is the first time when setup is called by this device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) * this function will initialize the runtime state for this chip and save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) * the same in the device structure. Else it will update the runtime info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) * with the updated chip info. Nothing is really being written to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) * controller hardware here, that is not done until the actual transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) * commence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) static int pl022_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) struct pl022_config_chip const *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) struct pl022_config_chip chip_info_dt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) struct chip_data *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) struct pl022 *pl022 = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) unsigned int bits = spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) struct device_node *np = spi->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (!spi->max_speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) /* Get controller_state if one is supplied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) chip = spi_get_ctldata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) if (chip == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) dev_dbg(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) "allocated memory for controller's runtime state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) /* Get controller data if one is supplied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) chip_info = spi->controller_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) if (chip_info == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) chip_info_dt = pl022_default_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) chip_info_dt.hierarchy = SSP_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) of_property_read_u32(np, "pl022,interface",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) &chip_info_dt.iface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) of_property_read_u32(np, "pl022,com-mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) &chip_info_dt.com_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) of_property_read_u32(np, "pl022,rx-level-trig",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) &chip_info_dt.rx_lev_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) of_property_read_u32(np, "pl022,tx-level-trig",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) &chip_info_dt.tx_lev_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) of_property_read_u32(np, "pl022,ctrl-len",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) &chip_info_dt.ctrl_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) of_property_read_u32(np, "pl022,wait-state",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) &chip_info_dt.wait_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) of_property_read_u32(np, "pl022,duplex",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) &chip_info_dt.duplex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) chip_info = &chip_info_dt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) chip_info = &pl022_default_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) /* spi_board_info.controller_data not is supplied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) dev_dbg(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) "using default controller_data settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) dev_dbg(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) "using user supplied controller_data settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) * We can override with custom divisors, else we use the board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) * frequency setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) if ((0 == chip_info->clk_freq.cpsdvsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) && (0 == chip_info->clk_freq.scr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) status = calculate_effective_freq(pl022,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) spi->max_speed_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) &clk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) goto err_config_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) if ((clk_freq.cpsdvsr % 2) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) clk_freq.cpsdvsr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) clk_freq.cpsdvsr - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) if ((clk_freq.cpsdvsr < CPSDVR_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) status = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) "cpsdvsr is configured incorrectly\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) goto err_config_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) status = verify_controller_parameters(pl022, chip_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) dev_err(&spi->dev, "controller data is incorrect");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) goto err_config_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) pl022->rx_lev_trig = chip_info->rx_lev_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) pl022->tx_lev_trig = chip_info->tx_lev_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) /* Now set controller state based on controller data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) chip->xfer_type = chip_info->com_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if (!chip_info->cs_control) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) chip->cs_control = null_cs_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) if (!gpio_is_valid(pl022->chipselects[spi->chip_select]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) dev_warn(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) "invalid chip select\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) chip->cs_control = chip_info->cs_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) /* Check bits per word with vendor specific range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) status = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) dev_err(&spi->dev, "illegal data size for this controller!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) pl022->vendor->max_bpw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) goto err_config_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) } else if (bits <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) chip->n_bytes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) chip->read = READING_U8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) chip->write = WRITING_U8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) } else if (bits <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) chip->n_bytes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) chip->read = READING_U16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) chip->write = WRITING_U16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) chip->n_bytes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) chip->read = READING_U32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) chip->write = WRITING_U32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) /* Now Initialize all register settings required for this chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) chip->cr0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) chip->cr1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) chip->dmacr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) chip->cpsr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) if ((chip_info->com_mode == DMA_TRANSFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) && ((pl022->master_info)->enable_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) chip->enable_dma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) dev_dbg(&spi->dev, "DMA mode set in controller state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) SSP_DMACR_MASK_RXDMAE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) SSP_DMACR_MASK_TXDMAE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) chip->enable_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) SSP_DMACR_MASK_RXDMAE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) SSP_DMACR_MASK_TXDMAE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) chip->cpsr = clk_freq.cpsdvsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) /* Special setup for the ST micro extended control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (pl022->vendor->extended_cr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) u32 etx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) if (pl022->vendor->pl023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) /* These bits are only in the PL023 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) SSP_CR1_MASK_FBCLKDEL_ST, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) /* These bits are in the PL022 but not PL023 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) SSP_CR0_MASK_HALFDUP_ST, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) SSP_CR0_MASK_CSS_ST, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) SSP_WRITE_BITS(chip->cr0, chip_info->iface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) SSP_CR0_MASK_FRF_ST, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) SSP_CR1_MASK_MWAIT_ST, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) SSP_WRITE_BITS(chip->cr0, bits - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) SSP_CR0_MASK_DSS_ST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) if (spi->mode & SPI_LSB_FIRST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) tmp = SSP_RX_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) etx = SSP_TX_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) tmp = SSP_RX_MSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) etx = SSP_TX_MSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) SSP_CR1_MASK_RXIFLSEL_ST, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) SSP_CR1_MASK_TXIFLSEL_ST, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) SSP_WRITE_BITS(chip->cr0, bits - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) SSP_CR0_MASK_DSS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) SSP_WRITE_BITS(chip->cr0, chip_info->iface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) SSP_CR0_MASK_FRF, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) /* Stuff that is common for all versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) tmp = SSP_CLK_POL_IDLE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) tmp = SSP_CLK_POL_IDLE_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) tmp = SSP_CLK_SECOND_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) tmp = SSP_CLK_FIRST_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) /* Loopback is available on all versions except PL023 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) if (pl022->vendor->loopback) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) if (spi->mode & SPI_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) tmp = LOOPBACK_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) tmp = LOOPBACK_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) /* Save controller_state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) spi_set_ctldata(spi, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) err_config_params:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) spi_set_ctldata(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) * pl022_cleanup - cleanup function registered to SPI master framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) * @spi: spi device which is requesting cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) * This function is registered to the SPI framework for this SPI master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) * controller. It will free the runtime state of chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) static void pl022_cleanup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) struct chip_data *chip = spi_get_ctldata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) spi_set_ctldata(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) static struct pl022_ssp_controller *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) pl022_platform_data_dt_get(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) struct pl022_ssp_controller *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) u32 tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) dev_err(dev, "no dt node defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) if (!pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) pd->bus_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) pd->enable_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) of_property_read_u32(np, "num-cs", &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) pd->num_chipselect = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) of_property_read_u32(np, "pl022,autosuspend-delay",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) &pd->autosuspend_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) pd->rt = of_property_read_bool(np, "pl022,rt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) return pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) struct device *dev = &adev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) struct pl022_ssp_controller *platform_info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) dev_get_platdata(&adev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) struct pl022 *pl022 = NULL; /*Data for this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) struct device_node *np = adev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) int status = 0, i, num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) dev_info(&adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) if (!platform_info && IS_ENABLED(CONFIG_OF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) platform_info = pl022_platform_data_dt_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) if (!platform_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) dev_err(dev, "probe: no platform data defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) if (platform_info->num_chipselect) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) num_cs = platform_info->num_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) dev_err(dev, "probe: no chip select defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) /* Allocate master with space for data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) master = spi_alloc_master(dev, sizeof(struct pl022));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) if (master == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) pl022 = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) pl022->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) pl022->master_info = platform_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) pl022->adev = adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) pl022->vendor = id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) pl022->chipselects = devm_kcalloc(dev, num_cs, sizeof(int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) if (!pl022->chipselects) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) status = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) goto err_no_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) * Bus Number Which has been Assigned to this SSP controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) * on this board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) master->bus_num = platform_info->bus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) master->num_chipselect = num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) master->cleanup = pl022_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) master->setup = pl022_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) master->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) master->transfer_one_message = pl022_transfer_one_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) master->rt = platform_info->rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) master->dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) if (platform_info->num_chipselect && platform_info->chipselects) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) for (i = 0; i < num_cs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) pl022->chipselects[i] = platform_info->chipselects[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) } else if (pl022->vendor->internal_cs_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) for (i = 0; i < num_cs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) pl022->chipselects[i] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) } else if (IS_ENABLED(CONFIG_OF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) for (i = 0; i < num_cs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) if (cs_gpio == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) status = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) goto err_no_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) pl022->chipselects[i] = cs_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) if (gpio_is_valid(cs_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) if (devm_gpio_request(dev, cs_gpio, "ssp-pl022"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) dev_err(&adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) "could not request %d gpio\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) cs_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) else if (gpio_direction_output(cs_gpio, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) dev_err(&adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) "could not set gpio %d as output\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) cs_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) * Supports mode 0-3, loopback, and active low CS. Transfers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) * always MS bit first on the original pl022.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) if (pl022->vendor->extended_cr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) master->mode_bits |= SPI_LSB_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) status = amba_request_regions(adev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) goto err_no_ioregion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) pl022->phybase = adev->res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) pl022->virtbase = devm_ioremap(dev, adev->res.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) resource_size(&adev->res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) if (pl022->virtbase == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) status = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) goto err_no_ioremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) dev_info(&adev->dev, "mapped registers from %pa to %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) &adev->res.start, pl022->virtbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) pl022->clk = devm_clk_get(&adev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) if (IS_ERR(pl022->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) status = PTR_ERR(pl022->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) goto err_no_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) status = clk_prepare_enable(pl022->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) goto err_no_clk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) /* Initialize transfer pump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) tasklet_init(&pl022->pump_transfers, pump_transfers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) (unsigned long)pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) /* Disable SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) SSP_CR1(pl022->virtbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) load_ssp_default_config(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) 0, "pl022", pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) goto err_no_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) /* Get DMA channels, try autoconfiguration first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) status = pl022_dma_autoprobe(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) if (status == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) dev_dbg(dev, "deferring probe to get DMA channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) goto err_no_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) /* If that failed, use channels from platform_info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) platform_info->enable_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) else if (platform_info->enable_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) status = pl022_dma_probe(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) if (status != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) platform_info->enable_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) /* Register with the SPI framework */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) amba_set_drvdata(adev, pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) status = devm_spi_register_master(&adev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) dev_err(&adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) "probe - problem registering spi master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) goto err_spi_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) dev_dbg(dev, "probe succeeded\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) /* let runtime pm put suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) if (platform_info->autosuspend_delay > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) dev_info(&adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) "will use autosuspend for runtime pm, delay %dms\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) platform_info->autosuspend_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) pm_runtime_set_autosuspend_delay(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) platform_info->autosuspend_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) pm_runtime_use_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) err_spi_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) if (platform_info->enable_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) pl022_dma_remove(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) err_no_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) clk_disable_unprepare(pl022->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) err_no_clk_en:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) err_no_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) err_no_ioremap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) amba_release_regions(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) err_no_ioregion:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) err_no_gpio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) err_no_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) pl022_remove(struct amba_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) struct pl022 *pl022 = amba_get_drvdata(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) if (!pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) * undo pm_runtime_put() in probe. I assume that we're not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) * accessing the primecell here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) pm_runtime_get_noresume(&adev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) load_ssp_default_config(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) if (pl022->master_info->enable_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) pl022_dma_remove(pl022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) clk_disable_unprepare(pl022->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) amba_release_regions(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) tasklet_disable(&pl022->pump_transfers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) static int pl022_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) struct pl022 *pl022 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) ret = spi_master_suspend(pl022->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) ret = pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) spi_master_resume(pl022->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) dev_dbg(dev, "suspended\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) static int pl022_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) struct pl022 *pl022 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) ret = pm_runtime_force_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) dev_err(dev, "problem resuming\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) /* Start the queue running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) ret = spi_master_resume(pl022->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) dev_dbg(dev, "resumed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) static int pl022_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) struct pl022 *pl022 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) clk_disable_unprepare(pl022->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) pinctrl_pm_select_idle_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) static int pl022_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) struct pl022 *pl022 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) clk_prepare_enable(pl022->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) static const struct dev_pm_ops pl022_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) static struct vendor_data vendor_arm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .fifodepth = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .max_bpw = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .unidir = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .extended_cr = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .pl023 = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .loopback = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .internal_cs_ctrl = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) static struct vendor_data vendor_st = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) .fifodepth = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .max_bpw = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .unidir = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .extended_cr = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .pl023 = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .loopback = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) .internal_cs_ctrl = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) static struct vendor_data vendor_st_pl023 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .fifodepth = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .max_bpw = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .unidir = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) .extended_cr = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .pl023 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) .loopback = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) .internal_cs_ctrl = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) static struct vendor_data vendor_lsi = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .fifodepth = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .max_bpw = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) .unidir = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .extended_cr = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .pl023 = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .loopback = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .internal_cs_ctrl = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) static const struct amba_id pl022_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) * ARM PL022 variant, this has a 16bit wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) * and 8 locations deep TX/RX FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .id = 0x00041022,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .mask = 0x000fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .data = &vendor_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) * ST Micro derivative, this has 32bit wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) * and 32 locations deep TX/RX FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .id = 0x01080022,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .mask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) .data = &vendor_st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) * ST-Ericsson derivative "PL023" (this is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) * an official ARM number), this is a PL022 SSP block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) * stripped to SPI mode only, it has 32bit wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) * and 32 locations deep TX/RX FIFO but no extended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) * CR0/CR1 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .id = 0x00080023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) .mask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .data = &vendor_st_pl023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) * PL022 variant that has a chip select control register whih
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) * allows control of 5 output signals nCS[0:4].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) .id = 0x000b6022,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) .mask = 0x000fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) .data = &vendor_lsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) MODULE_DEVICE_TABLE(amba, pl022_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) static struct amba_driver pl022_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) .name = "ssp-pl022",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .pm = &pl022_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) .id_table = pl022_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .probe = pl022_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .remove = pl022_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) static int __init pl022_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) return amba_driver_register(&pl022_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) subsys_initcall(pl022_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) static void __exit pl022_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) amba_driver_unregister(&pl022_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) module_exit(pl022_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) MODULE_DESCRIPTION("PL022 SSP Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags