^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Microchip PIC32 SPI controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Purna Chandra Mandal <purna.mandal@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2016, Microchip Technology Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* SPI controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct pic32_spi_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 ctrl_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 ctrl_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 ctrl_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 status_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 status_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 status_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 dontuse[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 dontuse2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 ctrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 ctrl2_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 ctrl2_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 ctrl2_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Bit fields of SPI Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CTRL_RX_INT_SHIFT 0 /* Rx interrupt generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RX_FIFO_EMPTY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RX_FIFO_NOT_EMPTY 1 /* not empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RX_FIFO_HALF_FULL 2 /* full by half or more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RX_FIFO_FULL 3 /* completely full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CTRL_TX_INT_SHIFT 2 /* TX interrupt generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TX_FIFO_ALL_EMPTY 0 /* completely empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TX_FIFO_EMPTY 1 /* empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TX_FIFO_HALF_EMPTY 2 /* empty by half or more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TX_FIFO_NOT_FULL 3 /* atleast one empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CTRL_MSTEN BIT(5) /* enable master mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CTRL_CKP BIT(6) /* active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CTRL_CKE BIT(8) /* Tx on falling edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CTRL_SMP BIT(9) /* Rx at middle or end of tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CTRL_BPW_MASK 0x03 /* bits per word/sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CTRL_BPW_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PIC32_BPW_8 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PIC32_BPW_16 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PIC32_BPW_32 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CTRL_SIDL BIT(13) /* sleep when idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CTRL_ON BIT(15) /* enable macro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CTRL_ENHBUF BIT(16) /* enable enhanced buffering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CTRL_MCLKSEL BIT(23) /* select clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CTRL_MSSEN BIT(28) /* macro driven /SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CTRL_FRMEN BIT(31) /* enable framing mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Bit fields of SPI Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define STAT_RF_EMPTY BIT(5) /* RX Fifo empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define STAT_RX_OV BIT(6) /* err, s/w needs to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define STAT_TX_UR BIT(8) /* UR in Framed SPI modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define STAT_FRM_ERR BIT(12) /* Multiple Frame Sync pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define STAT_TF_LVL_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define STAT_TF_LVL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define STAT_RF_LVL_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define STAT_RF_LVL_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Bit fields of SPI Baud Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BAUD_MASK 0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Bit fields of SPI Control2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CTRL2_TX_UR_EN BIT(10) /* Enable int on Tx under-run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CTRL2_RX_OV_EN BIT(11) /* Enable int on Rx over-run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CTRL2_FRM_ERR_EN BIT(12) /* Enable frame err int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Minimum DMA transfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PIC32_DMA_LEN_MIN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct pic32_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dma_addr_t dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct pic32_spi_regs __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int fault_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int rx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int tx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 fifo_n_byte; /* FIFO depth in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Current controller setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 speed_hz; /* spi-clk rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 fifo_n_elm; /* FIFO depth in words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PIC32F_DMA_PREP 0 /* DMA chnls configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Current transfer state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct completion xfer_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* PIO transfer specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) const void *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const void *tx_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) const void *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) const void *rx_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) void (*rx_fifo)(struct pic32_spi *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void (*tx_fifo)(struct pic32_spi *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static inline void pic32_spi_enable(struct pic32_spi *pic32s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static inline void pic32_spi_disable(struct pic32_spi *pic32s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* avoid SPI registers read/write at immediate next CPU clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ndelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void pic32_spi_set_clk_rate(struct pic32_spi *pic32s, u32 spi_ck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* div = (clk_in / 2 * spi_ck) - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) div = DIV_ROUND_CLOSEST(clk_get_rate(pic32s->clk), 2 * spi_ck) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) writel(div & BAUD_MASK, &pic32s->regs->baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static inline u32 pic32_rx_fifo_level(struct pic32_spi *pic32s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 sr = readl(&pic32s->regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return (sr >> STAT_RF_LVL_SHIFT) & STAT_RF_LVL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static inline u32 pic32_tx_fifo_level(struct pic32_spi *pic32s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 sr = readl(&pic32s->regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return (sr >> STAT_TF_LVL_SHIFT) & STAT_TF_LVL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Return the max entries we can fill into tx fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static u32 pic32_tx_max(struct pic32_spi *pic32s, int n_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 tx_left, tx_room, rxtx_gap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) tx_left = (pic32s->tx_end - pic32s->tx) / n_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) tx_room = pic32s->fifo_n_elm - pic32_tx_fifo_level(pic32s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Another concern is about the tx/rx mismatch, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * though to use (pic32s->fifo_n_byte - rxfl - txfl) as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * one maximum value for tx, but it doesn't cover the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * data which is out of tx/rx fifo and inside the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * shift registers. So a ctrl from sw point of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * view is taken.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) rxtx_gap = ((pic32s->rx_end - pic32s->rx) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) (pic32s->tx_end - pic32s->tx)) / n_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return min3(tx_left, tx_room, (u32)(pic32s->fifo_n_elm - rxtx_gap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Return the max entries we should read out of rx fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static u32 pic32_rx_max(struct pic32_spi *pic32s, int n_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 rx_left = (pic32s->rx_end - pic32s->rx) / n_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return min_t(u32, rx_left, pic32_rx_fifo_level(pic32s));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define BUILD_SPI_FIFO_RW(__name, __type, __bwl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void pic32_spi_rx_##__name(struct pic32_spi *pic32s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) __type v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 mx = pic32_rx_max(pic32s, sizeof(__type)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) for (; mx; mx--) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) v = read##__bwl(&pic32s->regs->buf); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (pic32s->rx_end - pic32s->len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) *(__type *)(pic32s->rx) = v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pic32s->rx += sizeof(__type); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void pic32_spi_tx_##__name(struct pic32_spi *pic32s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) __type v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 mx = pic32_tx_max(pic32s, sizeof(__type)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) for (; mx ; mx--) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) v = (__type)~0U; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (pic32s->tx_end - pic32s->len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) v = *(__type *)(pic32s->tx); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) write##__bwl(v, &pic32s->regs->buf); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pic32s->tx += sizeof(__type); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) BUILD_SPI_FIFO_RW(byte, u8, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) BUILD_SPI_FIFO_RW(word, u16, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) BUILD_SPI_FIFO_RW(dword, u32, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void pic32_err_stop(struct pic32_spi *pic32s, const char *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) disable_irq_nosync(pic32s->fault_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) disable_irq_nosync(pic32s->rx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) disable_irq_nosync(pic32s->tx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Show err message and abort xfer with err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dev_err(&pic32s->master->dev, "%s\n", msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (pic32s->master->cur_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pic32s->master->cur_msg->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) complete(&pic32s->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static irqreturn_t pic32_spi_fault_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct pic32_spi *pic32s = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) status = readl(&pic32s->regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Error handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (status & (STAT_RX_OV | STAT_TX_UR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) writel(STAT_RX_OV, &pic32s->regs->status_clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) writel(STAT_TX_UR, &pic32s->regs->status_clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pic32_err_stop(pic32s, "err_irq: fifo ov/ur-run\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (status & STAT_FRM_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pic32_err_stop(pic32s, "err_irq: frame error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (!pic32s->master->cur_msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pic32_err_stop(pic32s, "err_irq: no mesg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static irqreturn_t pic32_spi_rx_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct pic32_spi *pic32s = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pic32s->rx_fifo(pic32s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* rx complete ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (pic32s->rx_end == pic32s->rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) disable_irq_nosync(pic32s->fault_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) disable_irq_nosync(pic32s->rx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* complete current xfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) complete(&pic32s->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static irqreturn_t pic32_spi_tx_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct pic32_spi *pic32s = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pic32s->tx_fifo(pic32s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* tx complete? disable tx interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (pic32s->tx_end == pic32s->tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) disable_irq_nosync(pic32s->tx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static void pic32_spi_dma_rx_notify(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct pic32_spi *pic32s = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) complete(&pic32s->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int pic32_spi_dma_transfer(struct pic32_spi *pic32s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct spi_master *master = pic32s->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct dma_async_tx_descriptor *desc_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct dma_async_tx_descriptor *desc_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!master->dma_rx || !master->dma_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) xfer->rx_sg.sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) xfer->rx_sg.nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (!desc_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) goto err_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) xfer->tx_sg.sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) xfer->tx_sg.nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (!desc_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) goto err_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Put callback on the RX transfer, that should finish last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) desc_rx->callback = pic32_spi_dma_rx_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) desc_rx->callback_param = pic32s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) cookie = dmaengine_submit(desc_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret = dma_submit_error(cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) goto err_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) cookie = dmaengine_submit(desc_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ret = dma_submit_error(cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) goto err_dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dma_async_issue_pending(master->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dma_async_issue_pending(master->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) err_dma_tx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dmaengine_terminate_all(master->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) err_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int pic32_spi_dma_config(struct pic32_spi *pic32s, u32 dma_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int buf_offset = offsetof(struct pic32_spi_regs, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct spi_master *master = pic32s->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct dma_slave_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) memset(&cfg, 0, sizeof(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) cfg.device_fc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) cfg.src_addr = pic32s->dma_base + buf_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) cfg.dst_addr = pic32s->dma_base + buf_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) cfg.src_maxburst = pic32s->fifo_n_elm / 2; /* fill one-half */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) cfg.dst_maxburst = pic32s->fifo_n_elm / 2; /* drain one-half */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) cfg.src_addr_width = dma_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) cfg.dst_addr_width = dma_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* tx channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) cfg.slave_id = pic32s->tx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) cfg.direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = dmaengine_slave_config(master->dma_tx, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dev_err(&master->dev, "tx channel setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* rx channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) cfg.slave_id = pic32s->rx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) cfg.direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ret = dmaengine_slave_config(master->dma_rx, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev_err(&master->dev, "rx channel setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int pic32_spi_set_word_size(struct pic32_spi *pic32s, u8 bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) enum dma_slave_buswidth dmawidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 buswidth, v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) switch (bits_per_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) pic32s->rx_fifo = pic32_spi_rx_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) pic32s->tx_fifo = pic32_spi_tx_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) buswidth = PIC32_BPW_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dmawidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pic32s->rx_fifo = pic32_spi_rx_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) pic32s->tx_fifo = pic32_spi_tx_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) buswidth = PIC32_BPW_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dmawidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pic32s->rx_fifo = pic32_spi_rx_dword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pic32s->tx_fifo = pic32_spi_tx_dword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) buswidth = PIC32_BPW_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dmawidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* calculate maximum number of words fifos can hold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) pic32s->fifo_n_elm = DIV_ROUND_UP(pic32s->fifo_n_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) bits_per_word / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* set word size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) v = readl(&pic32s->regs->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) v &= ~(CTRL_BPW_MASK << CTRL_BPW_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) v |= buswidth << CTRL_BPW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) writel(v, &pic32s->regs->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* re-configure dma width, if required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (test_bit(PIC32F_DMA_PREP, &pic32s->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) pic32_spi_dma_config(pic32s, dmawidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int pic32_spi_prepare_hardware(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct pic32_spi *pic32s = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pic32_spi_enable(pic32s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int pic32_spi_prepare_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct pic32_spi *pic32s = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct spi_device *spi = msg->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* set device specific bits_per_word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (pic32s->bits_per_word != spi->bits_per_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pic32_spi_set_word_size(pic32s, spi->bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) pic32s->bits_per_word = spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* device specific speed change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (pic32s->speed_hz != spi->max_speed_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) pic32_spi_set_clk_rate(pic32s, spi->max_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) pic32s->speed_hz = spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* device specific mode change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (pic32s->mode != spi->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) val = readl(&pic32s->regs->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) val |= CTRL_CKP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) val &= ~CTRL_CKP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* tx on rising edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) val &= ~CTRL_CKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) val |= CTRL_CKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* rx at end of tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) val |= CTRL_SMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) writel(val, &pic32s->regs->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pic32s->mode = spi->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static bool pic32_spi_can_dma(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct pic32_spi *pic32s = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* skip using DMA on small size transfer to avoid overhead.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return (xfer->len >= PIC32_DMA_LEN_MIN) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) test_bit(PIC32F_DMA_PREP, &pic32s->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int pic32_spi_one_transfer(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct spi_transfer *transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct pic32_spi *pic32s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) bool dma_issued = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) pic32s = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* handle transfer specific word size change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (transfer->bits_per_word &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) (transfer->bits_per_word != pic32s->bits_per_word)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ret = pic32_spi_set_word_size(pic32s, transfer->bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pic32s->bits_per_word = transfer->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* handle transfer specific speed change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (transfer->speed_hz && (transfer->speed_hz != pic32s->speed_hz)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pic32_spi_set_clk_rate(pic32s, transfer->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pic32s->speed_hz = transfer->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) reinit_completion(&pic32s->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* transact by DMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (transfer->rx_sg.nents && transfer->tx_sg.nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = pic32_spi_dma_transfer(pic32s, transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dev_err(&spi->dev, "dma submit error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* DMA issued */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) dma_issued = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* set current transfer information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) pic32s->tx = (const void *)transfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) pic32s->rx = (const void *)transfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pic32s->tx_end = pic32s->tx + transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pic32s->rx_end = pic32s->rx + transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pic32s->len = transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* transact by interrupt driven PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) enable_irq(pic32s->fault_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) enable_irq(pic32s->rx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) enable_irq(pic32s->tx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* wait for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) timeout = wait_for_completion_timeout(&pic32s->xfer_done, 2 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev_err(&spi->dev, "wait error/timedout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (dma_issued) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dmaengine_terminate_all(master->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dmaengine_terminate_all(master->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static int pic32_spi_unprepare_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static int pic32_spi_unprepare_hardware(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct pic32_spi *pic32s = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pic32_spi_disable(pic32s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* This may be called multiple times by same spi dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int pic32_spi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (!spi->max_speed_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) dev_err(&spi->dev, "No max speed HZ parameter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* PIC32 spi controller can drive /CS during transfer depending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * on tx fifo fill-level. /CS will stay asserted as long as TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * fifo is non-empty, else will be deasserted indicating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * completion of the ongoing transfer. This might result into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * unreliable/erroneous SPI transactions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * To avoid that we will always handle /CS by toggling GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!gpio_is_valid(spi->cs_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static void pic32_spi_cleanup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* de-activate cs-gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static int pic32_spi_dma_prep(struct pic32_spi *pic32s, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct spi_master *master = pic32s->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) master->dma_rx = dma_request_chan(dev, "spi-rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (IS_ERR(master->dma_rx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev_warn(dev, "RX channel not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) master->dma_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) master->dma_tx = dma_request_chan(dev, "spi-tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (IS_ERR(master->dma_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) dev_warn(dev, "TX channel not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) master->dma_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (pic32_spi_dma_config(pic32s, DMA_SLAVE_BUSWIDTH_1_BYTE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* DMA chnls allocated and prepared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) set_bit(PIC32F_DMA_PREP, &pic32s->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (master->dma_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dma_release_channel(master->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) master->dma_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (master->dma_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dma_release_channel(master->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) master->dma_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static void pic32_spi_dma_unprep(struct pic32_spi *pic32s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (!test_bit(PIC32F_DMA_PREP, &pic32s->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) clear_bit(PIC32F_DMA_PREP, &pic32s->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (pic32s->master->dma_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dma_release_channel(pic32s->master->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (pic32s->master->dma_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dma_release_channel(pic32s->master->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static void pic32_spi_hw_init(struct pic32_spi *pic32s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* disable hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) pic32_spi_disable(pic32s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ctrl = readl(&pic32s->regs->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* enable enhanced fifo of 128bit deep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ctrl |= CTRL_ENHBUF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) pic32s->fifo_n_byte = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* disable framing mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ctrl &= ~CTRL_FRMEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* enable master mode while disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ctrl |= CTRL_MSTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* set tx fifo threshold interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ctrl &= ~(0x3 << CTRL_TX_INT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ctrl |= (TX_FIFO_HALF_EMPTY << CTRL_TX_INT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* set rx fifo threshold interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ctrl &= ~(0x3 << CTRL_RX_INT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ctrl |= (RX_FIFO_NOT_EMPTY << CTRL_RX_INT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* select clk source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ctrl &= ~CTRL_MCLKSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* set manual /CS mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ctrl &= ~CTRL_MSSEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) writel(ctrl, &pic32s->regs->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* enable error reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ctrl = CTRL2_TX_UR_EN | CTRL2_RX_OV_EN | CTRL2_FRM_ERR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) writel(ctrl, &pic32s->regs->ctrl2_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static int pic32_spi_hw_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct pic32_spi *pic32s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) pic32s->regs = devm_ioremap_resource(&pdev->dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (IS_ERR(pic32s->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return PTR_ERR(pic32s->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) pic32s->dma_base = mem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* get irq resources: err-irq, rx-irq, tx-irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) pic32s->fault_irq = platform_get_irq_byname(pdev, "fault");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (pic32s->fault_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return pic32s->fault_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) pic32s->rx_irq = platform_get_irq_byname(pdev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (pic32s->rx_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return pic32s->rx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) pic32s->tx_irq = platform_get_irq_byname(pdev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (pic32s->tx_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return pic32s->tx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* get clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) pic32s->clk = devm_clk_get(&pdev->dev, "mck0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (IS_ERR(pic32s->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dev_err(&pdev->dev, "clk not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ret = PTR_ERR(pic32s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) goto err_unmap_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ret = clk_prepare_enable(pic32s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) goto err_unmap_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) pic32_spi_hw_init(pic32s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) err_unmap_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dev_err(&pdev->dev, "%s failed, err %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static int pic32_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct pic32_spi *pic32s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) master = spi_alloc_master(&pdev->dev, sizeof(*pic32s));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) pic32s = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) pic32s->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ret = pic32_spi_hw_probe(pdev, pic32s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) goto err_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) master->mode_bits = SPI_MODE_3 | SPI_MODE_0 | SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) master->num_chipselect = 1; /* single chip-select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) master->max_speed_hz = clk_get_rate(pic32s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) master->setup = pic32_spi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) master->cleanup = pic32_spi_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) master->flags = SPI_MASTER_MUST_TX | SPI_MASTER_MUST_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) SPI_BPW_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) master->transfer_one = pic32_spi_one_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) master->prepare_message = pic32_spi_prepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) master->unprepare_message = pic32_spi_unprepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) master->prepare_transfer_hardware = pic32_spi_prepare_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) master->unprepare_transfer_hardware = pic32_spi_unprepare_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* optional DMA support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ret = pic32_spi_dma_prep(pic32s, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) goto err_bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (test_bit(PIC32F_DMA_PREP, &pic32s->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) master->can_dma = pic32_spi_can_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) init_completion(&pic32s->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) pic32s->mode = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* install irq handlers (with irq-disabled) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) irq_set_status_flags(pic32s->fault_irq, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ret = devm_request_irq(&pdev->dev, pic32s->fault_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) pic32_spi_fault_irq, IRQF_NO_THREAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_name(&pdev->dev), pic32s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev_err(&pdev->dev, "request fault-irq %d\n", pic32s->rx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) goto err_bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* receive interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) irq_set_status_flags(pic32s->rx_irq, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ret = devm_request_irq(&pdev->dev, pic32s->rx_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) pic32_spi_rx_irq, IRQF_NO_THREAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dev_name(&pdev->dev), pic32s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) dev_err(&pdev->dev, "request rx-irq %d\n", pic32s->rx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) goto err_bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* transmit interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) irq_set_status_flags(pic32s->tx_irq, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ret = devm_request_irq(&pdev->dev, pic32s->tx_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) pic32_spi_tx_irq, IRQF_NO_THREAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) dev_name(&pdev->dev), pic32s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dev_err(&pdev->dev, "request tx-irq %d\n", pic32s->tx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) goto err_bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* register master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ret = devm_spi_register_master(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dev_err(&master->dev, "failed registering spi master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) goto err_bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) platform_set_drvdata(pdev, pic32s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) err_bailout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) pic32_spi_dma_unprep(pic32s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) clk_disable_unprepare(pic32s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) err_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static int pic32_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct pic32_spi *pic32s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) pic32s = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) pic32_spi_disable(pic32s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) clk_disable_unprepare(pic32s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) pic32_spi_dma_unprep(pic32s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static const struct of_device_id pic32_spi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {.compatible = "microchip,pic32mzda-spi",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) MODULE_DEVICE_TABLE(of, pic32_spi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static struct platform_driver pic32_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .name = "spi-pic32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .of_match_table = of_match_ptr(pic32_spi_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .probe = pic32_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .remove = pic32_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) module_platform_driver(pic32_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) MODULE_AUTHOR("Purna Chandra Mandal <purna.mandal@microchip.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) MODULE_DESCRIPTION("Microchip SPI driver for PIC32 SPI controller.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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